Single-cycle-RISCV-processor

Verilog code for a 32-bit pipelined Single Cycle RISC-V processor (RV32I) processor.

The project is implemented using Vivado software

RTL Schematic of processor

RISCV processor with Controlpath and Datapath Modules

Testbench results

Reference material:

Computer Organization and Design: The Hardware/Software Interface RISC-V edition Authors - DAVID A PATTERSON , JOHN L HENNESSY

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALU.v		ALU.v
Control_path.v		Control_path.v
Data_Memory.v		Data_Memory.v
Datapath.v		Datapath.v
Extend.v		Extend.v
Instruction_Memory.v		Instruction_Memory.v
Program_Counter.v		Program_Counter.v
README.md		README.md
Registers.v		Registers.v
Top.v		Top.v
core.v		core.v
tb.v		tb.v

Navigation Menu