This project details the custom IC design, layout, and simulation of a 4-bit synchronous up-counter utilizing a 180nm CMOS process technology (GPDK180). The design methodology follows a bottom-up approach, beginning with the transistor-level realization of fundamental standard cells, including a True Single-Phase Clock (TSPC) D flip-flop, XOR gate, and NAND-based AND logic. These cells are subsequently integrated to form a synchronous counting architecture featuring Enable (EN) control and asynchronous clear (clr) signals, free of the cumulative propagation delays typical of asynchronous ripple counters.
- Technology Node: Designed entirely utilizing 180nm CMOS process (GPDK180).
- Synchronous Architecture: All flip-flops are driven simultaneously by a single, common clock pulse to eliminate glitching and ripple delays.
- Low Voltage Operation: Optimized for reliable performance at a 1.8V supply voltage.
- Full Custom Layout: Hand-routed physical layouts following the sea of gate arrays concept to minimize area and mitigate parasitic latch-up.
- Highly Efficient Logic: Utilizes a TSPC configuration for the flip-flops, drastically reducing the overall transistor count and saving physical layout area.
The circuit architecture is built using a bottom-up approach, consisting of four main standard cells:
Realized by cascading a 2-input NAND gate with a standard Inverter.
- Transistors: 6 (4 discrete transistors + 1 standard inverter)
- Design: Sized to balance drive strength across pull-up and pull-down networks.
Achieves the exclusive-OR function using an optimized arrangement of CMOS logic and two inverters.
- Transistors: 12 (8 discrete transistors + 2 standard inverters)
- Design: Utilizes a channel length of 180nm and a total width of 2µm for reliable switching.
The state-holding element, designed using a True Single-Phase Clock (TSPC) configuration for high efficiency and low area.
- Transistors: 11 (5 PMOS and 6 NMOS)
- Operation: Captures input on the HIGH clock and transfers data to output precisely on the falling edge. This custom design significantly reduces the transistor count compared to a standard 42-transistor NAND-based master-slave configuration.
Integrates 4 TSPC D flip-flops, 4 XOR gates, and 4 AND gates.
- Total Transistors: 116
- Sequence: Counts sequentially from 0000 up to 1111 before resetting.
Schematic capture, physical layout, and transient analysis were all performed using the Cadence Virtuoso suite.
| Component | Propagation Delay | Power Consumption | Transistor Count |
|---|---|---|---|
| AND Gate | 195.50 ps | 7.87 µW | 6 |
| XOR Gate | 5.985 ns | 9.93 µW | 12 |
| D Flip-Flop | 11.22 ns | 26.23 µW | 11 |
| Top-Level Counter | 20.39 ns | 97.90 µW | 110 |
Verdict:
- ✅ Pass: Post-simulation results confirm highly reliable synchronous counting behavior at 1.8V.
- ✅ DRC & LVS Cleared: Layout successfully resolved standard VLSI errors, including broken nets, net shorts, and stamp errors (bulk-tap connections).
- EDA Tool: Cadence Virtuoso (Schematic Editor & Layout Suite)
- Process File: GPDK180 Technology file
- Analysis: Post-layout transient simulation and Design Rule Checks (DRC)
- Kavya G
- Mahadev Yankanna Malali
Under the guidance of Dr. Yajunath K, Assistant Professor. Department of Electronics and Communication Engineering, The National Institute of Engineering, Mysuru.