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perf(dsv41): prompt-chunk partials over a reduce-scatter, the same bits from 3/4 of the bytes - #49

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imD-5:perf/dsv41-reduce-scatter
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imD-5 wants to merge 1 commit into
Elevatormusic:deepseek-v41-tp2from
imD-5:perf/dsv41-reduce-scatter

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@imD-5

@imD-5 imD-5 commented Oct 28, 2026

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Effect

  • Cold 64K prefill, two GB10 (TP2): 30.8-31.0 s with TF_DS_RS=1, 31.7-32.0 s with it off, in alternating rounds.
  • Replies byte-identical with it on and off (26 greedy prompts), and --alone --serial equal in every cell.
  • Decode and the other prefill lengths are within noise.

Reproduce

TF_DS_RS=1 python3 tools/prefill_cold.py run http://<head>:8100 <MODEL> prompts.json out.json   # then TF_DS_RS=0, same prompts rebuilt
python3 tools/bench_concurrent.py http://<head>:8100 <MODEL> --alone --serial
  • Fresh prompts and a restart per round (TF_DS_SPILL_GIB=0), two rounds each way.

Change

  • NCCL.reduce_scatter and Comm.reduced: prompt partials reach the mHC post as bf16(p0 + p1) from an fp32 reduce-scatter and a bf16 all-gather, 3/4 of the bytes.

Why

  • The post kernels add the two ranks' rows and round to bf16, which is one fp32 add of two operands: the same bits in either order.

Type

  • type: feature: new code (a feature, tool or add-on)

Tests

  • tests/test_dsv41_reduced.py: 5 passed in the engine image, 2 skipped without torch or triton.

Checklist

  • No personal data, machine names, internal hosts or local paths. No AI attribution lines.
AI disclosure

AI: Claude Opus 5.5 via Hermes Agent
Checked: by author

…ts from 3/4 of the bytes

TF_DS_RS=1 (two ranks, off by default): a prompt chunk's attention and MoE partials reach the mHC post as
bf16(p0 + p1), from an fp32 reduce-scatter and a bf16 all-gather, instead of the fp32 all-gather. The post kernels
add the two ranks' rows and round to bf16; one fp32 add of two operands has the same bits in either order, so they
form the same y. Odd row counts, rows the RDMA gather holds, and one rank keep the gather.
@imD-5
imD-5 requested a review from Elevatormusic as a code owner October 28, 2026 06:08
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