2-Tap Analog LMS Filter Implementation

This repository contains the simulation files, schematics, and the technical report for the design and implementation of a continuous-time 2-Tap Least Mean Squares (LMS) Adaptive Filter using analog components.

Project Overview

Adaptive filters are key components in modern signal processing, dynamically adjusting their parameters in time-varying environments. While digital implementations are ubiquitous, analog adaptive filters offer distinct advantages in continuous-time processing, high-frequency operation, and lower power consumption.

This project implements the mathematical operations of the LMS algorithm (multiplication, integration, subtraction, and summation) in the analog domain using operational amplifiers (UA741) and discrete transistors (BJTs).

Novelty & Design Uniqueness

• Fully Continuous-Time Processing: Unlike digital LMS implementations which rely on ADCs/DACs, digital signal processors, and discrete-time clocking, this filter processes continuous-time signals natively. This completely eliminates sampling latency, clock jitter, and quantization noise.
• Physical Four-Quadrant BJT Multiplier: Signal multiplication is performed in the analog domain using the exponential transconductance characteristics of a transistor translinear core. The design uses matched resistors ($R_1\text{--}R_4 = 1,\text{k}\Omega$, $R_5\text{--}R_8 = 2,\text{k}\Omega$, $R_9 = 20,\text{k}\Omega$) and BJTs to execute real-time multiplication rather than digital arithmetic.
• Analog Weight Update Loop: The LMS correlation and adaptation feedback loop is closed physically. Active integrators accumulate the correlation between the error signal and tap inputs directly using feedback capacitors ($C = 330,\text{nF}$ and $R = 4.7,\text{k}\Omega$ for a time constant $\tau = 1.55,\text{ms}$).

Setbacks, Bottlenecks & Practical Challenges

• Scaling and Attenuation Errors: The translinear multiplier suffers from scale attenuation due to non-idealities. For input signals of $V_1 = 2,\text{V}$ and $V_2 = 100,\text{mV}$, the expected mathematical output is $200,\text{mV}$. However, LTSpice simulations and hardware tests yield approximately $180,\text{mV}$, representing a $10%$ scaling error.
• Input Feedthrough: The Fourier analysis (FFT) of the multiplier output reveals feedthrough peaks at the fundamental frequencies ($1,\text{kHz}$ and $10,\text{kHz}$). This is caused by incomplete current cancellation in the translinear BJT core, which arises due to transistor mismatch.
• Device and Component Mismatches: Slight differences in BJT parameters (such as saturation current $I_s$ and current gain $\beta$) and resistor tolerances directly degrade the accuracy of the mathematical operations, particularly the subtractor's Common-Mode Rejection Ratio (CMRR).
• Op-amp Non-Idealities: The use of UA741 op-amps (powered by $\pm 12,\text{V}$ rails) introduces finite open-loop gain, input offset voltage, and finite bandwidth. These factors limit the high-frequency range of the delay line (which uses $R = 16,\text{k}\Omega$ and $C = 313.5,\text{nF}$ for a nominal group delay $\tau_g \approx 2RC \approx 10,\text{ms}$) and cause DC drift in the integrators.

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Directory Structure

The folder is organized as follows:

├── readme.md                      # Project description and guide
├── report_final.pdf               # Complete compiled project report PDF
└── Simulation/
    ├── Models/
    │   ├── UA741.301              # SPICE model for the UA741 operational amplifier
    │   ├── UA741.asy              # SPICE symbol for the UA741
    │   ├── TSMC_180nm.txt         # Transistor technology model file
    │   ├── tip31a.lib             # NPN power BJT library
    │   └── tip32a.lib             # PNP power BJT library
    │
    ├── 1_Multiplier/
    │   ├── multi-v3.asc           # Final translinear multiplier schematic
    │   ├── multi-v3.asy           # Multiplier subcircuit symbol
    │   ├── multi_opamp.asc        # Alternative op-amp based multiplier schematic
    │   └── mult-v1_block_test.asc # Multiplier block testbench
    │
    ├── 2_Delay_Block/
    │   ├── delay_block.asc        # First-order active all-pass filter schematic (APF)
    │   ├── delay_block.asy        # Delay block subcircuit symbol
    │   └── delay_block_test.asc   # Delay block characterization testbench
    │
    ├── 3_Integrator/
    │   ├── integrator.asc         # Active op-amp integrator schematic
    │   ├── integrator.asy         # Integrator subcircuit symbol
    │   └── integrator_block_test.asc # Integrator block testbench
    │
    ├── 4_Subtractor/
    │   ├── subtractor.asc         # Op-amp difference amplifier schematic
    │   ├── subtractor.asy         # Subtractor subcircuit symbol
    │   └── subtractor_block_test.asc # Subtractor block testbench
    │
    ├── 5_Summing_Amplifier/
    │   ├── summ_amp.asc           # Inverting summing amplifier schematic
    │   ├── summ_amp.asy           # Summing amplifier subcircuit symbol
    │   └── summ_amp_block_test.asc # Summing amplifier block testbench
    │
    ├── 6_Full_System/
    │   └── full-v3.asc            # Integrated 2-Tap LMS Filter schematic
    │
    └── Drafts/                    # Project drafts and design iterations
        ├── Draft1.asc
        ├── Draft2.asc
        ├── Draft3.asc
        └── test-v1.asc

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Circuit Components

1. Multiplier Block: A four-quadrant translinear BJT multiplier utilizing the exponential current-voltage relationship of transistors to perform real-time signal multiplication.
2. Delay Block: A first-order active all-pass filter network providing a frequency-dependent phase shift that yields a group delay ($\tau_g \approx 2RC$) for low-frequency signals.
3. Integrator: An active op-amp integrator with a capacitor in the feedback path, executing the weight updating equation by accumulating error correlation.
4. Subtractor: An op-amp difference amplifier configured to compute the instantaneous error signal ($e(t) = d(t) - y(t)$).
5. Summing Amplifier: An inverting summing amplifier designed to aggregate individual weighted tap signals to form the overall filter output.

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How to Simulate

All schematics are designed for LTSpice. To simulate any component:

1. Open the desired testbench (e.g., Simulation/3_Integrator/integrator_block_test.asc) in LTSpice.
2. Ensure the relative paths resolve (they are configured to locate model libraries in Simulation/Models/ automatically).
3. Click the Run button to perform the transient analysis and plot the output nodes.

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Technical Report

The final compiled project report is included directly in this folder as report_final.pdf. It contains the complete theoretical derivations, block-by-block circuit analysis, LTSpice simulation waveforms, and laboratory hardware results.

Authors

• Nikhil Venkat Atkuru (IIIT Hyderabad, ECE)
• Abhinav Venkata Kota (IIIT Hyderabad, ECE)