feat(vsss): poly-driven input labels for garble mode

[cyphersnake]

Background

Currently, GarbleMode::issue_garbled_wire() generates input wire labels using a simple RNG-based approach. We need to integrate VSSS #62 to enable secure input label generation that supports verification and secret reconstruction.

Problem

• Each input wire needs consistent labels across all 181 circuit instances
• Labels must be generated from polynomial shares for VSSS properties
• Must maintain Free-XOR property: label1 = label0 ⊕ delta
• Current GarbleMode instances are isolated - no shared state between circuits instances

Proposed Solution

Implement a two-polynomial-per-wire approach with pre-generation:

1. Pre-generate polynomials before GarbleMode instantiation:

• Generate two polynomials per input wire (degree k = 174 for n = 181)
• First polynomial: randomly generated for label0 from the Seed
• Second polynomial: backward interpolated from label1 = label0 ⊕ delta[i]
• Store polynomial commitments for verification

2. Pass pre-computed shares to each GarbleMode:

• Extract shares for specific circuit_id from polynomials
• Convert shares to labels (Fr → S conversion)
• Each GarbleMode receives its pre-computed labels

Implementation Tasks

• Create vsss::InputPolynomials struct in 'src/cut_and_choose/soldering/'

pub struct VSSSInputPolynomials {
  wire_polynomials: Vec<(Polynomial<Fr>, Polynomial<Fr>)>,
  deltas: Vec<Delta>,
  commitments: Vec<(PolynomialCommits, PolynomialCommits)>,
}

• Implement polynomial generation with backward interpolation:
• Generate random polynomial for label0
• Generate random deltas
• Compute all label1 values via Free-XOR
• Interpolate second polynomial from label1 values
• Add share-to-label conversion functions:
• Modify GarbleMode to accept pre-computed label0's:

pub fn new_from_labels(
  capacity: usize,
  delta: Delta,
  input_labels: Vec<S>,
  output_handler: CTH
) -> Self

• Update issue_garbled_wire() to use pre-computed labels when available
• Add integration in C&C module:
• Pre-generate polynomials once
• Distribute shares to all GarbleMode instances
• Include polynomial commitments in output for verification

Key Design Decisions

1. Field conversion: Use embedding approach - 128-bit S into 256-bit Fr with zero padding
2. Polynomial storage: Pre-generate all polynomials upfront for clean separation
3. Verification: Evaluator can verify both polynomial commitments and Free-XOR relationship

Success Criteria

• Input labels generated from VSSS polynomials
• Free-XOR property maintained across all circuits
• Polynomial commitments enable verification
• Backward compatibility with non-VSSS mode

References

• VSSS implementation: src/cut_and_choose/soldering/vsss.rs
• Current garble mode: src/circuit/modes/garble_mode.rs
• Paper: https://hackmd.io/@alpen/B1QfSSO5gg