diff --git a/sdram/rtl/sdram.v b/sdram/rtl/sdram.v
index 66284f6..94ceb12 100644
--- a/sdram/rtl/sdram.v
+++ b/sdram/rtl/sdram.v
@@ -51,31 +51,29 @@ module sdram
 // Ports
 //-----------------------------------------------------------------
 (
-    input           clk_i,
-    input           rst_i,
-
-    // Wishbone Interface
-    input           stb_i,
-    input           we_i,
-    input [3:0]     sel_i,
-    input           cyc_i,
-    input [31:0]    addr_i,
-    input [31:0]    data_i,
-    output [31:0]   data_o,
-    output          stall_o,
-    output          ack_o,
-    
-    // SDRAM Interface
-    output          sdram_clk_o,
-    output          sdram_cke_o,
-    output          sdram_cs_o,
-    output          sdram_ras_o,
-    output          sdram_cas_o,
-    output          sdram_we_o,
-    output [1:0]    sdram_dqm_o,
-    output [12:0]   sdram_addr_o,
-    output [1:0]    sdram_ba_o,
-    inout [15:0]    sdram_data_io
+    clk_i,
+    rst_i,
+
+    stb_i,
+    we_i,
+    sel_i,
+    cyc_i,
+    addr_i,
+    data_i,
+    data_o,
+    stall_o,
+    ack_o,
+
+    sdram_clk_o,
+    sdram_cke_o,
+    sdram_cs_o,
+    sdram_ras_o,
+    sdram_cas_o,
+    sdram_we_o,
+    sdram_dqm_o,
+    sdram_addr_o,
+    sdram_ba_o,
+    sdram_data_io
 );
 
 //-----------------------------------------------------------------
@@ -91,8 +89,8 @@ localparam CMD_PRECHARGE     = 4'b0010;
 localparam CMD_REFRESH       = 4'b0001;
 localparam CMD_LOAD_MODE     = 4'b0000;
 
-// Mode: Burst Length = 4 bytes, CAS=2
-localparam MODE_REG          = {3'b000,1'b0,2'b00,3'b010,1'b0,3'b001};
+// Mode: Burst Length = 4 bytes
+localparam MODE_REG          = {3'b000,1'b0,2'b00,SDRAM_READ_LATENCY[2:0],1'b0,3'b001};
 
 // SM states
 localparam STATE_W           = 4;
@@ -110,7 +108,7 @@ localparam STATE_REFRESH     = 4'd9;
 localparam AUTO_PRECHARGE    = 10;
 localparam ALL_BANKS         = 10;
 
-localparam SDRAM_DATA_W      = 16;
+localparam SDRAM_DATA_W      = (SDRAM_DQM_W * 8);
 
 localparam CYCLE_TIME_NS     = 1000 / SDRAM_MHZ;
 
@@ -119,6 +117,32 @@ localparam SDRAM_TRCD_CYCLES = (20 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
 localparam SDRAM_TRP_CYCLES  = (20 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
 localparam SDRAM_TRFC_CYCLES = (60 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
 
+input wire clk_i;
+input wire rst_i;
+
+// Wishbone Interface
+input  wire        stb_i;
+input  wire        we_i;
+input  wire [3:0]  sel_i;
+input  wire        cyc_i;
+input  wire [31:0] addr_i;
+input  wire [31:0] data_i;
+output wire [31:0] data_o;
+output wire        stall_o;
+output wire        ack_o;
+
+// SDRAM Interface
+output wire                    sdram_clk_o;
+output wire                    sdram_cke_o;
+output wire                    sdram_cs_o;
+output wire                    sdram_ras_o;
+output wire                    sdram_cas_o;
+output wire                    sdram_we_o;
+output wire [SDRAM_DQM_W-1:0]  sdram_dqm_o;
+output wire [SDRAM_ROW_W-1:0]  sdram_addr_o;
+output wire [SDRAM_BANK_W-1:0] sdram_ba_o;
+inout  wire [SDRAM_DATA_W-1:0] sdram_data_io;
+
 //-----------------------------------------------------------------
 // Registers / Wires
 //-----------------------------------------------------------------