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BOM Line consolidation / DFM Optimization #16

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@lethalbit

Currently for rev2, and it's supporting boards there is a bit of a chunky BOM, and while some items are shared between the connector boards, the PHYs and the main board, it could be improved.

The following things could vastly simplify the BOM at the cost of ease of assembly:

  • Standardize to smallest package size where possible
    • This would mean that all passives would be 0201 or 0402 where possible
  • Normalize derating for capacitors
    • The capacitors on the board have been derated by at least 150%, which might be overkill but results in larger packages, which also leads into the first item

Those are the first two things that come to mind, there are also some DFM optimizations that would need to be made to make assembly easier, that ties into the BOM consolidation, but there are some other things as well:

  • Remove as many THT parts as possible to remove as much manual assembly as possible
    • Currently there are only 2(?) parts that are through hole, the DC jack and the rest button, we could possibly swap the reset button to an SMD variant and normalize it with the DFU trigger button, which also eliminates a BOM line item.
  • Ensure all ground connections for through-hole parts have thermal spokes
    • Due to the main board being 8-layers and having very substantial ground planes, trying to solder any leads that are connected to ground just soak up heat making it hard to solder.

The following other misc items are also tied in but don't fall exactly in line with DFM, if we want to have a case, it would be cheaper to go for a standard extruded aluminum shell, but this limits our ability to do module stacking like planned, meaning you need to pull the device out of the case to swap things like PHYs or connectors, which is a big downside, but on the upside it would mean you don't need custom milled cases for each part.

We could also possibly squish the board a big to make it less long, compress the power supply area a bit to save board space.

Also possibly rotating the design a bit to have a more standard flow-through so the USB and power connectors are on the bottom rather than side, we would also need to rotate the FPGA anyway if we keep using the ECP5 so we can use the high-speed IO on the SCSI PHY connector.

Thoughts/additions @dragonmux, @esden?

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