diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 146819335..650cc3127 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -119,6 +119,7 @@ run_vsim: - axi_modify_address - axi_serializer - axi_sim_mem + - axi_to_apb # Modules that pull in shared submodules keep explicit additional dependencies # to avoid missing a rerun when a shared submodule changes. diff --git a/Bender.lock b/Bender.lock index da9205fe2..ac28e3059 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,7 +1,7 @@ packages: common_cells: - revision: 9ca8a7655f741e7dd5736669a20a301325194c28 - version: 1.39.0 + revision: 03d98106aa19952a10360d2230def85144a0008b + version: null source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -14,8 +14,8 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] tech_cells_generic: - revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf - version: 0.2.13 + revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845 + version: 0.2.14 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: diff --git a/Bender.yml b/Bender.yml index 7105eca20..7587ca337 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,10 +20,13 @@ package: - "Nils Wistoff " - "Florian Zaruba " +remotes: + pulp: https://github.com/pulp-platform + dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.39.0 } - common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.5 } - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: v2.0.0-beta.2 } + common_verification: 0.2.5 + tech_cells_generic: 0.2.14 export_include_dirs: - include @@ -91,6 +94,7 @@ sources: - src/axi_interleaved_xbar.sv - src/axi_iw_converter.sv - src/axi_lite_xbar.sv + - src/axi_to_apb.sv - src/axi_xbar_unmuxed.sv - src/axi_to_mem_banked.sv - src/axi_to_mem_interleaved.sv @@ -131,6 +135,7 @@ sources: - test/tb_axi_lite_regs.sv - test/tb_axi_iw_converter.sv - test/tb_axi_lite_to_apb.sv + - test/tb_axi_to_apb.sv - test/tb_axi_lite_to_axi.sv - test/tb_axi_lite_xbar.sv - test/tb_axi_modify_address.sv diff --git a/CHANGELOG.md b/CHANGELOG.md index c47ae6a05..d95ea9abf 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased +### Added +- `axi_to_apb`: AXI4+ATOP to APB4 bridge supporting data-width downsizing and address truncation, + built on `axi_to_detailed_mem`. Adds the `axi_to_apb_intf` interface variant and the + `tb_axi_to_apb` testbench. + ## 0.39.10 - 2026-06-19 ### Added diff --git a/Makefile b/Makefile index 98c1d3e00..b67e1c557 100644 --- a/Makefile +++ b/Makefile @@ -35,6 +35,7 @@ TBS ?= axi_addr_test \ axi_modify_address \ axi_serializer \ axi_sim_mem \ + axi_to_apb \ axi_to_axi_lite \ axi_to_mem_banked \ axi_xbar diff --git a/README.md b/README.md index 8408d861f..dea48b70c 100644 --- a/README.md +++ b/README.md @@ -67,6 +67,7 @@ In addition to the documents linked in the following table, we are setting up [d | [`axi_serializer`](src/axi_serializer.sv) | Serializes transactions with different IDs to the same ID. | | | [`axi_throttle`](src/axi_throttle.sv) | Limits the maximum number of outstanding transfers sent to the downstream logic. | | | [`axi_test`](src/axi_test.sv) | A set of testbench utilities for AXI interfaces. | | +| [`axi_to_apb`](src/axi_to_apb.sv) | AXI4 to APB4 protocol converter with data-width downsizing and optional address decoding. | | | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv) | AXI4 to AXI4-Lite protocol converter. | | | [`axi_to_mem`](src/axi_to_mem.sv) | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked, interleaved, split variant. | | | [`axi_xbar`](src/axi_xbar.sv) | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) | @@ -143,3 +144,4 @@ All code in each release and on the default branch is tested on a recent version [doc.axi_id_serialize]: https://pulp-platform.github.io/axi/master/module.axi_id_serialize [doc.axi_iw_converter]: https://pulp-platform.github.io/axi/master/module.axi_iw_converter [doc.axi_lite_regs]: https://pulp-platform.github.io/axi/master/module.axi_lite_regs +[doc.axi_lite_dw_converter]: https://pulp-platform.github.io/axi/master/module.axi_lite_dw_converter \ No newline at end of file diff --git a/axi.core b/axi.core index 1c8b25040..5ed06d8dd 100644 --- a/axi.core +++ b/axi.core @@ -84,7 +84,7 @@ filesets: - src/axi_xp.sv file_type : systemVerilogSource depend : - - ">=pulp-platform.org::common_cells:1.31.1" + - ">=pulp-platform.org::common_cells:1.39.0" benchs: files: - test/tb_axi_dw_pkg.sv diff --git a/doc/axi_demux.md b/doc/axi_demux.md index 4b8b964ed..ac28fcd99 100644 --- a/doc/axi_demux.md +++ b/doc/axi_demux.md @@ -45,7 +45,6 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple |:----------------------------------|:------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. | | `slv_{aw,ar}_select_i` | Index of the master port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | | `mst_*` | Array of master ports of the demultiplexer. The array index of each port is the index of the master port. | diff --git a/doc/axi_lite_demux.md b/doc/axi_lite_demux.md index cafbf267a..b08bffc9f 100644 --- a/doc/axi_lite_demux.md +++ b/doc/axi_lite_demux.md @@ -38,7 +38,6 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple |:----------------------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. | | `slv_{aw,ar}_select_i` | Index of the master port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | | `mst_*` | Array of master ports of the demultiplexer. The array index of each port is the index of the master port. | diff --git a/doc/axi_lite_mailbox.md b/doc/axi_lite_mailbox.md index 7d5e2de52..e636e052f 100644 --- a/doc/axi_lite_mailbox.md +++ b/doc/axi_lite_mailbox.md @@ -27,7 +27,6 @@ This table describes the ports of the module. |:---------------|:---------------------------|:-------------------------------------------------------| | `clk_i` | `input logic` | clock | | `rst_ni` | `input logic` | asynchronous reset active low | -| `test_i` | `input logic` | testmode enable | | `slv_reqs_i` | `input req_lite_t [1:0]` | requests of the two AXI4-Lite ports | | `slv_resps_o` | `output resp_lite_t [1:0]` | responses of the two AXI4-Lite ports | | `irq_o` | `output logic [1:0]` | interrupt output for each port | diff --git a/doc/axi_lite_xbar.md b/doc/axi_lite_xbar.md index 047b3966d..af515e32d 100644 --- a/doc/axi_lite_xbar.md +++ b/doc/axi_lite_xbar.md @@ -55,7 +55,6 @@ If two crossbars are connected in both directions, meaning both have one of thei |:------------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_ports_*` | Array of slave ports of the crossbar. The array index of each port is the index of the slave port. This index will be prepended to all requests at one of the master ports. | | `mst_ports_*` | Array of master ports of the crossbar. The array index of each port is the index of the master port. | | `addr_map_i` | Address map of the crossbar (see section *Address Map* above). | diff --git a/doc/axi_xbar.md b/doc/axi_xbar.md index ca0c12108..ef33dda9a 100644 --- a/doc/axi_xbar.md +++ b/doc/axi_xbar.md @@ -71,7 +71,6 @@ If two crossbars are connected in both directions, meaning both have one of thei |:------------------------|:------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_ports_*` | Array of slave ports of the crossbar. The array index of each port is the index of the slave port. This index will be prepended to all requests at one of the master ports. | | `mst_ports_*` | Array of master ports of the crossbar. The array index of each port is the index of the master port. | | `addr_map_i` | Address map of the crossbar (see section *Address Map* above). | diff --git a/ips_list.yml b/ips_list.yml index 81f9ef6b0..8c6cbae5f 100644 --- a/ips_list.yml +++ b/ips_list.yml @@ -1,5 +1,5 @@ common_cells: - commit: v1.39.0 + commit: v2.0.0-beta.2 group: pulp-platform common_verification: @@ -7,5 +7,5 @@ common_verification: group: pulp-platform tech_cells_generic: - commit: v0.2.2 + commit: v0.2.14 group: pulp-platform diff --git a/scripts/axi_intercon_gen.py b/scripts/axi_intercon_gen.py index 9e8e606d5..2880cf965 100644 --- a/scripts/axi_intercon_gen.py +++ b/scripts/axi_intercon_gen.py @@ -150,7 +150,6 @@ def assigns(w, max_idw, masters, slaves): def instance_ports(w, id_width, masters, slaves): ports = [Port('clk_i' , 'clk_i'), Port('rst_ni', 'rst_ni'), - Port('test_i', "1'b0"), Port('slv_ports_req_i' , 'masters_req'), Port('slv_ports_resp_o', 'masters_resp'), Port('mst_ports_req_o' , 'slaves_req'), diff --git a/scripts/compile_vsim.sh b/scripts/compile_vsim.sh index 7109858f9..4244e3a54 100755 --- a/scripts/compile_vsim.sh +++ b/scripts/compile_vsim.sh @@ -18,7 +18,7 @@ set -e [ ! -z "$VSIM" ] || VSIM=vsim -bender script vsim -t test -t rtl \ +bender script vsim -t test -t rtl -t cc_no_deprecated \ --vlog-arg="-svinputport=compat" \ --vlog-arg="-override_timescale 1ns/1ps" \ --vlog-arg="-suppress 2583" \ diff --git a/scripts/run_verilator.sh b/scripts/run_verilator.sh index c6681e6d0..df7c0aeab 100755 --- a/scripts/run_verilator.sh +++ b/scripts/run_verilator.sh @@ -21,7 +21,7 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) [ ! -z "$VERILATOR" ] || VERILATOR="verilator" -bender script verilator -t synthesis -t synth_test > ./verilator.f +bender script verilator -t synthesis -t synth_test -t cc_no_deprecated > ./verilator.f VERILATOR_FLAGS=() VERILATOR_FLAGS+=(-Wno-fatal) diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index aaf8c3f22..b95d99836 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -241,6 +241,12 @@ exec_test() { done done ;; + axi_to_apb) + for DW in 32 64; do + call_vsim tb_axi_to_apb -gTbAxiDataWidth=$DW \ + -t 1ns -coverage -voptargs="+acc +cover=bcesfx" + done + ;; *) call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx" ;; diff --git a/scripts/run_yosys_slang.sh b/scripts/run_yosys_slang.sh index ad575c72a..f1d7d86ff 100755 --- a/scripts/run_yosys_slang.sh +++ b/scripts/run_yosys_slang.sh @@ -18,6 +18,6 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) [ ! -z "$YOSYS" ] || YOSYS="yosys" -bender script flist-plus -t synthesis -t synth_test > ./slang.flist +bender script flist-plus -t synthesis -t synth_test -t cc_no_deprecated > ./slang.flist $YOSYS -m slang -p "read_slang -Werror -f slang.flist --allow-use-before-declare --keep-hierarchy --top axi_synth_bench; hierarchy" diff --git a/scripts/synth.sh b/scripts/synth.sh index 70cb86a89..407ff9870 100755 --- a/scripts/synth.sh +++ b/scripts/synth.sh @@ -20,7 +20,7 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) [ ! -z "$SYNOPSYS_DC" ] || SYNOPSYS_DC="synopsys dc_shell -64" echo 'remove_design -all' > ./synth.tcl -bender script synopsys -t synth_test >> ./synth.tcl +bender script synopsys -t synth_test -t tech_cells_generic_exclude_tc_sram -t cc_no_deprecated >> ./synth.tcl echo 'elaborate axi_synth_bench' >> ./synth.tcl cat ./synth.tcl | $SYNOPSYS_DC | tee synth.log 2>&1 diff --git a/src/axi_atop_filter.sv b/src/axi_atop_filter.sv index 55ad491b2..d42549083 100644 --- a/src/axi_atop_filter.sv +++ b/src/axi_atop_filter.sv @@ -345,13 +345,12 @@ module axi_atop_filter #( end end - stream_register #( - .T(r_resp_cmd_t) + cc_stream_register #( + .data_t (r_resp_cmd_t) ) r_resp_cmd ( .clk_i (clk_i), .rst_ni (rst_ni), .clr_i (1'b0), - .testmode_i (1'b0), .valid_i (r_resp_cmd_push_valid), .ready_o (r_resp_cmd_push_ready), .data_i (r_resp_cmd_push), diff --git a/src/axi_burst_splitter_gran.sv b/src/axi_burst_splitter_gran.sv index 2ae847a4d..f58be9f1f 100644 --- a/src/axi_burst_splitter_gran.sv +++ b/src/axi_burst_splitter_gran.sv @@ -92,7 +92,6 @@ module axi_burst_splitter_gran #( ) i_demux_supported_vs_unsupported ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( slv_req ), .slv_aw_select_i ( sel_aw_unsupported ), .slv_ar_select_i ( sel_ar_unsupported ), @@ -148,7 +147,6 @@ module axi_burst_splitter_gran #( ) i_err_slv ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( unsupported_req ), .slv_resp_o ( unsupported_resp ) ); @@ -384,18 +382,18 @@ module axi_burst_splitter_gran #( // -------------------------------------------------- // Flip-Flops // -------------------------------------------------- - `FFARN(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) - `FFARN(b_state_q, b_state_d, BReady, clk_i, rst_ni) - `FFARN(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) - `FFARN(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) - `FFARN(w_len_q, w_len_d, 8'h00, clk_i, rst_ni) - `FFARN(w_len_vld_q, w_len_vld_d, 1'b0, clk_i, rst_ni) + `FF(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) + `FF(b_state_q, b_state_d, BReady, clk_i, rst_ni) + `FF(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) + `FF(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) + `FF(w_len_q, w_len_d, 8'h00, clk_i, rst_ni) + `FF(w_len_vld_q, w_len_vld_d, 1'b0, clk_i, rst_ni) // -------------------------------------------------- // Assumptions and assertions // -------------------------------------------------- `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR // pragma translate_off default disable iff (!rst_ni); // Inputs @@ -572,9 +570,9 @@ module axi_burst_splitter_gran_ax_chan #( end // registers - `FFARN(ax_q, ax_d, '0, clk_i, rst_ni) - `FFARN(state_q, state_d, Idle, clk_i, rst_ni) - `FFARN(num_beats_q, num_beats_d, 9'h000, clk_i, rst_ni) + `FF(ax_q, ax_d, '0, clk_i, rst_ni) + `FF(state_q, state_d, Idle, clk_i, rst_ni) + `FF(num_beats_q, num_beats_d, 9'h000, clk_i, rst_ni) endmodule @@ -621,12 +619,13 @@ module axi_burst_splitter_gran_counters #( assign alloc_pld_in.len = alloc_len_i; if (CutPath) begin : gen_spill - spill_register #( - .T ( alloc_pld_t ), + cc_spill_register #( + .data_t ( alloc_pld_t ), .Bypass ( 1'b0 ) ) i_spill_register_alloc ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( alloc_req_i ), .ready_o ( alloc_gnt_o ), .data_i ( alloc_pld_in ), @@ -647,12 +646,12 @@ module axi_burst_splitter_gran_counters #( cnt_t [MaxTxns-1:0] cnt_oup; cnt_idx_t cnt_free_idx, cnt_r_idx; for (genvar i = 0; i < MaxTxns; i++) begin : gen_cnt - delta_counter #( - .WIDTH ( $bits(cnt_t) ) + cc_delta_counter #( + .Width ( $bits(cnt_t) ) ) i_cnt ( .clk_i, .rst_ni, - .clear_i ( cnt_clr[i] ), + .clr_i ( cnt_clr[i] ), .en_i ( cnt_dec[i] ), .load_i ( cnt_set[i] ), .down_i ( 1'b1 ), @@ -665,9 +664,9 @@ module axi_burst_splitter_gran_counters #( end assign cnt_inp = {1'b0, alloc_pld_out.len} + 1; - lzc #( - .WIDTH ( MaxTxns ), - .MODE ( 1'b0 ) // start counting at index 0 + cc_lzc #( + .Width ( MaxTxns ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc ( .in_i ( cnt_free ), .cnt_o ( cnt_free_idx ), @@ -676,14 +675,15 @@ module axi_burst_splitter_gran_counters #( logic idq_inp_req, idq_inp_gnt, idq_oup_gnt, idq_oup_valid, idq_oup_pop; - id_queue #( - .ID_WIDTH ( $bits(id_t) ), - .CAPACITY ( MaxTxns ), - .FULL_BW ( FullBW ), + cc_id_queue #( + .IdWidth ( $bits(id_t) ), + .Capacity ( MaxTxns ), + .FullBw ( FullBW ), .data_t ( cnt_idx_t ) ) i_idq ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .inp_id_i ( alloc_pld_out.id ), .inp_data_i ( cnt_free_idx ), .inp_req_i ( idq_inp_req ), @@ -731,7 +731,7 @@ module axi_burst_splitter_gran_counters #( end // registers - `FFARN(err_q, err_d, '0, clk_i, rst_ni) + `FF(err_q, err_d, '0, clk_i, rst_ni) `ifndef VERILATOR // pragma translate_off diff --git a/src/axi_burst_unwrap.sv b/src/axi_burst_unwrap.sv index 70f8cc9eb..8ff4d9509 100644 --- a/src/axi_burst_unwrap.sv +++ b/src/axi_burst_unwrap.sv @@ -85,7 +85,6 @@ module axi_burst_unwrap #( ) i_demux_supported_vs_unsupported ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i, .slv_aw_select_i ( sel_aw_unsupported ), .slv_ar_select_i ( sel_ar_unsupported ), @@ -123,7 +122,6 @@ module axi_burst_unwrap #( ) i_err_slv ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( unsupported_req ), .slv_resp_o ( unsupported_resp ) ); @@ -135,11 +133,11 @@ module axi_burst_unwrap #( logic w_cnt_dec, w_cnt_req, w_cnt_gnt; axi_pkg::len_t b_cnt_len, w_cnt_len; axi_burst_unwrap_ax_chan #( - .AwChan ( 1'b1 ), - .chan_t ( aw_chan_t ), + .AwChan ( 1'b1 ), + .chan_t ( aw_chan_t ), .AddrWidth ( AddrWidth ), - .IdWidth ( IdWidth ), - .MaxTxns ( MaxWriteTxns ) + .IdWidth ( IdWidth ), + .MaxTxns ( MaxWriteTxns ) ) i_axi_burst_unwrap_aw_chan ( .clk_i, .rst_ni, @@ -353,18 +351,18 @@ module axi_burst_unwrap #( // -------------------------------------------------- // Flip-Flops // -------------------------------------------------- - `FFARN(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) - `FFARN(b_state_q, b_state_d, BReady, clk_i, rst_ni) - `FFARN(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) - `FFARN(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) - `FFARN(w_last_q, w_last_d, 1'b0, clk_i, rst_ni) - `FFARN(w_state_q, w_state_d, WReady, clk_i, rst_ni) + `FF(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) + `FF(b_state_q, b_state_d, BReady, clk_i, rst_ni) + `FF(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) + `FF(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) + `FF(w_last_q, w_last_d, 1'b0, clk_i, rst_ni) + `FF(w_state_q, w_state_d, WReady, clk_i, rst_ni) // -------------------------------------------------- // Assumptions and assertions // -------------------------------------------------- `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR // pragma translate_off default disable iff (!rst_ni); // Inputs @@ -533,8 +531,8 @@ module axi_burst_unwrap_ax_chan #( end // registers - `FFARN(ax_q, ax_d, '0, clk_i, rst_ni) - `FFARN(state_q, state_d, Idle, clk_i, rst_ni) + `FF(ax_q, ax_d, '0, clk_i, rst_ni) + `FF(state_q, state_d, Idle, clk_i, rst_ni) endmodule /// Internal module of [`axi_burst_splitter`](module.axi_burst_splitter) to order transactions. @@ -567,12 +565,12 @@ module axi_burst_counters #( cnt_t [MaxTxns-1:0] cnt_oup; cnt_idx_t cnt_free_idx, cnt_r_idx; for (genvar i = 0; i < MaxTxns; i++) begin : gen_cnt - counter #( - .WIDTH ( $bits(cnt_t) ) + cc_counter #( + .Width ( $bits(cnt_t) ) ) i_cnt ( .clk_i, .rst_ni, - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( cnt_dec[i] ), .load_i ( cnt_set[i] ), .down_i ( 1'b1 ), @@ -584,9 +582,9 @@ module axi_burst_counters #( end assign cnt_inp = {1'b0, alloc_len_i} + 1; - lzc #( - .WIDTH ( MaxTxns ), - .MODE ( 1'b0 ) // start counting at index 0 + cc_lzc #( + .Width ( MaxTxns ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) // start counting at index 0 ) i_lzc ( .in_i ( cnt_free ), .cnt_o ( cnt_free_idx ), @@ -595,13 +593,14 @@ module axi_burst_counters #( logic idq_inp_req, idq_inp_gnt, idq_oup_gnt, idq_oup_valid, idq_oup_pop; - id_queue #( - .ID_WIDTH ( $bits(id_t) ), - .CAPACITY ( MaxTxns ), + cc_id_queue #( + .IdWidth ( $bits(id_t) ), + .Capacity ( MaxTxns ), .data_t ( cnt_idx_t ) ) i_idq ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .inp_id_i ( alloc_id_i ), .inp_data_i ( cnt_free_idx ), .inp_req_i ( idq_inp_req ), @@ -649,6 +648,6 @@ module axi_burst_counters #( end // registers - `FFARN(err_q, err_d, '0, clk_i, rst_ni) + `FF(err_q, err_d, '0, clk_i, rst_ni) endmodule diff --git a/src/axi_bus_compare.sv b/src/axi_bus_compare.sv index e1a3426ee..5f14677b6 100644 --- a/src/axi_bus_compare.sv +++ b/src/axi_bus_compare.sv @@ -45,8 +45,6 @@ module axi_bus_compare #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4+ATOP A channel request in input axi_req_t axi_a_req_i, /// AXI4+ATOP A channel response out @@ -164,55 +162,60 @@ module axi_bus_compare #( //----------------------------------- // Channel A stream forks //----------------------------------- - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_aw_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_req_i.aw_valid ), .ready_o ( axi_a_rsp_o.aw_ready ), .valid_o ( {fifo_sel_valid_aw_a, axi_a_req_o.aw_valid} ), .ready_i ( {fifo_sel_ready_aw_a, axi_a_rsp_i.aw_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_w_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_req_i.w_valid ), .ready_o ( axi_a_rsp_o.w_ready ), .valid_o ( {fifo_sel_valid_w_a, axi_a_req_o.w_valid} ), .ready_i ( {fifo_sel_ready_w_a, axi_a_rsp_i.w_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_b_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_rsp_i.b_valid ), .ready_o ( axi_a_req_o.b_ready ), .valid_o ( {fifo_sel_valid_b_a, axi_a_rsp_o.b_valid} ), .ready_i ( {fifo_sel_ready_b_a, axi_a_req_i.b_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_ar_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_req_i.ar_valid ), .ready_o ( axi_a_rsp_o.ar_ready ), .valid_o ( {fifo_sel_valid_ar_a, axi_a_req_o.ar_valid} ), .ready_i ( {fifo_sel_ready_ar_a, axi_a_rsp_i.ar_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_r_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_rsp_i.r_valid ), .ready_o ( axi_a_req_o.r_ready ), .valid_o ( {fifo_sel_valid_r_a, axi_a_rsp_o.r_valid} ), @@ -225,15 +228,15 @@ module axi_bus_compare #( //----------------------------------- for (genvar id = 0; id < 2**AxiIdWidth; id++) begin : gen_fifos_a - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_aw_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_aw_chan_t ) ) i_stream_fifo_aw_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_req_i.aw ), @@ -244,15 +247,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_aw_a [id] & fifo_cmp_valid_aw_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_b_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_b_chan_t ) ) i_stream_fifo_b_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_rsp_i.b ), @@ -263,15 +266,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_b_a [id] & fifo_cmp_valid_b_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_ar_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_ar_chan_t ) ) i_stream_fifo_ar_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_req_i.ar ), @@ -283,15 +286,14 @@ module axi_bus_compare #( ); if (UseSize) begin : gen_r_size - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( $clog2(DataWidth/8)+3 ), - // .DATA_WIDTH ( 7+3 ), - .DEPTH ( 2*FifoDepth ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( $clog2(DataWidth/8)+3 ), + .Depth ( 2*FifoDepth ) ) i_stream_fifo_w_size ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o (), .data_i ( {axi_a_req_i.ar.addr[$clog2(DataWidth/8)-1:0], axi_a_req_i.ar.size} ), @@ -322,15 +324,15 @@ module axi_bus_compare #( end - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_r_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_r_chan_t ) ) i_stream_fifo_r_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_rsp_i.r ), @@ -343,15 +345,14 @@ module axi_bus_compare #( end if (UseSize) begin : gen_w_size - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( $clog2(DataWidth/8)+3 ), - // .DATA_WIDTH ( 7+3 ), - .DEPTH ( FifoDepth ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( $clog2(DataWidth/8)+3 ), + .Depth ( FifoDepth ) ) i_stream_fifo_w_size ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o (), .data_i ( {axi_a_req_i.aw.addr[$clog2(DataWidth/8)-1:0], axi_a_req_i.aw.size} ), @@ -381,15 +382,15 @@ module axi_bus_compare #( assign w_lower = '0; end - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_w_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_w_chan_t ) ) i_stream_fifo_w_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_req_i.w ), @@ -443,55 +444,60 @@ module axi_bus_compare #( //----------------------------------- // Channel B stream forks //----------------------------------- - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_aw_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_req_i.aw_valid ), .ready_o ( axi_b_rsp_o.aw_ready ), .valid_o ( {fifo_sel_valid_aw_b, axi_b_req_o.aw_valid} ), .ready_i ( {fifo_sel_ready_aw_b, axi_b_rsp_i.aw_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_w_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_req_i.w_valid ), .ready_o ( axi_b_rsp_o.w_ready ), .valid_o ( {fifo_sel_valid_w_b, axi_b_req_o.w_valid} ), .ready_i ( {fifo_sel_ready_w_b, axi_b_rsp_i.w_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_b_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_rsp_i.b_valid ), .ready_o ( axi_b_req_o.b_ready ), .valid_o ( {fifo_sel_valid_b_b, axi_b_rsp_o.b_valid} ), .ready_i ( {fifo_sel_ready_b_b, axi_b_req_i.b_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_ar_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_req_i.ar_valid ), .ready_o ( axi_b_rsp_o.ar_ready ), .valid_o ( {fifo_sel_valid_ar_b, axi_b_req_o.ar_valid} ), .ready_i ( {fifo_sel_ready_ar_b, axi_b_rsp_i.ar_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_r_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_rsp_i.r_valid ), .ready_o ( axi_b_req_o.r_ready ), .valid_o ( {fifo_sel_valid_r_b, axi_b_rsp_o.r_valid} ), @@ -504,15 +510,15 @@ module axi_bus_compare #( //----------------------------------- for (genvar id = 0; id < 2**AxiIdWidth; id++) begin : gen_fifos_b - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_aw_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_aw_chan_t ) ) i_stream_fifo_aw_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_req_i.aw ), @@ -523,15 +529,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_aw_a [id] & fifo_cmp_valid_aw_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_b_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_b_chan_t ) ) i_stream_fifo_b_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_rsp_i.b ), @@ -542,15 +548,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_b_a [id] & fifo_cmp_valid_b_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_ar_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_ar_chan_t ) ) i_stream_fifo_ar_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_req_i.ar ), @@ -561,15 +567,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_ar_a [id] & fifo_cmp_valid_ar_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_r_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_r_chan_t ) ) i_stream_fifo_r_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_rsp_i.r ), @@ -581,15 +587,15 @@ module axi_bus_compare #( ); end - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_w_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_w_chan_t ) ) i_stream_fifo_w_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_req_i.w ), diff --git a/src/axi_cdc_dst.sv b/src/axi_cdc_dst.sv index c3e76bfc1..cb831869f 100644 --- a/src/axi_cdc_dst.sv +++ b/src/axi_cdc_dst.sv @@ -57,16 +57,16 @@ module axi_cdc_dst #( input axi_resp_t dst_resp_i ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA // Workaround for a bug in Questa: Pass flat logic vector instead of struct to type parameter. - .T ( logic [$bits(aw_chan_t)-1:0] ), + .data_t ( logic [$bits(aw_chan_t)-1:0] ), `else // Other tools, such as VCS, have problems with type parameters constructed through `$bits()`. - .T ( aw_chan_t ), + .data_t ( aw_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_aw ( .async_data_i ( async_data_slave_aw_data_i ), .async_wptr_i ( async_data_slave_aw_wptr_i ), @@ -78,14 +78,14 @@ module axi_cdc_dst #( .dst_ready_i ( dst_resp_i.aw_ready ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(w_chan_t)-1:0] ), + .data_t ( logic [$bits(w_chan_t)-1:0] ), `else - .T ( w_chan_t ), + .data_t ( w_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_w ( .async_data_i ( async_data_slave_w_data_i ), .async_wptr_i ( async_data_slave_w_wptr_i ), @@ -97,14 +97,14 @@ module axi_cdc_dst #( .dst_ready_i ( dst_resp_i.w_ready ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(b_chan_t)-1:0] ), + .data_t ( logic [$bits(b_chan_t)-1:0] ), `else - .T ( b_chan_t ), + .data_t ( b_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_b ( .src_clk_i ( dst_clk_i ), .src_rst_ni ( dst_rst_ni ), @@ -116,14 +116,14 @@ module axi_cdc_dst #( .async_rptr_i ( async_data_slave_b_rptr_i ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(ar_chan_t)-1:0] ), + .data_t ( logic [$bits(ar_chan_t)-1:0] ), `else - .T ( ar_chan_t ), + .data_t ( ar_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_ar ( .dst_clk_i, .dst_rst_ni, @@ -135,14 +135,14 @@ module axi_cdc_dst #( .async_rptr_o ( async_data_slave_ar_rptr_o ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(r_chan_t)-1:0] ), + .data_t ( logic [$bits(r_chan_t)-1:0] ), `else - .T ( r_chan_t ), + .data_t ( r_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_r ( .src_clk_i ( dst_clk_i ), .src_rst_ni ( dst_rst_ni ), diff --git a/src/axi_cdc_src.sv b/src/axi_cdc_src.sv index 36e4e6119..902f5136e 100644 --- a/src/axi_cdc_src.sv +++ b/src/axi_cdc_src.sv @@ -57,15 +57,15 @@ module axi_cdc_src #( output logic [LogDepth:0] async_data_master_r_rptr_o ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( // Workaround for a bug in Questa (see comment in `axi_cdc_dst` for details). `ifdef QUESTA - .T ( logic [$bits(aw_chan_t)-1:0] ), + .data_t ( logic [$bits(aw_chan_t)-1:0] ), `else - .T ( aw_chan_t ), + .data_t ( aw_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_aw ( .src_clk_i, .src_rst_ni, @@ -77,14 +77,14 @@ module axi_cdc_src #( .async_rptr_i ( async_data_master_aw_rptr_i ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(w_chan_t)-1:0] ), + .data_t ( logic [$bits(w_chan_t)-1:0] ), `else - .T ( w_chan_t ), + .data_t ( w_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_w ( .src_clk_i, .src_rst_ni, @@ -96,14 +96,14 @@ module axi_cdc_src #( .async_rptr_i ( async_data_master_w_rptr_i ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(b_chan_t)-1:0] ), + .data_t ( logic [$bits(b_chan_t)-1:0] ), `else - .T ( b_chan_t ), + .data_t ( b_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_b ( .dst_clk_i ( src_clk_i ), .dst_rst_ni ( src_rst_ni ), @@ -115,14 +115,14 @@ module axi_cdc_src #( .async_rptr_o ( async_data_master_b_rptr_o ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(ar_chan_t)-1:0] ), + .data_t ( logic [$bits(ar_chan_t)-1:0] ), `else - .T ( ar_chan_t ), + .data_t ( ar_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_ar ( .src_clk_i, .src_rst_ni, @@ -134,14 +134,14 @@ module axi_cdc_src #( .async_rptr_i ( async_data_master_ar_rptr_i ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(r_chan_t)-1:0] ), + .data_t ( logic [$bits(r_chan_t)-1:0] ), `else - .T ( r_chan_t ), + .data_t ( r_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_r ( .dst_clk_i ( src_clk_i ), .dst_rst_ni ( src_rst_ni ), diff --git a/src/axi_cut.sv b/src/axi_cut.sv index ace6d7497..17309198d 100644 --- a/src/axi_cut.sv +++ b/src/axi_cut.sv @@ -46,12 +46,13 @@ module axi_cut #( ); // a spill register for each channel - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( BypassAw ) ) i_reg_aw ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_resp_o.aw_ready ), .data_i ( slv_req_i.aw ), @@ -60,12 +61,13 @@ module axi_cut #( .data_o ( mst_req_o.aw ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( BypassW ) ) i_reg_w ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -74,12 +76,13 @@ module axi_cut #( .data_o ( mst_req_o.w ) ); - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( BypassB ) ) i_reg_b ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -88,12 +91,13 @@ module axi_cut #( .data_o ( slv_resp_o.b ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( BypassAr ) ) i_reg_ar ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_resp_o.ar_ready ), .data_i ( slv_req_i.ar ), @@ -102,12 +106,13 @@ module axi_cut #( .data_o ( mst_req_o.ar ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( BypassR ) ) i_reg_r ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv index 8d217d14e..3b34ed259 100644 --- a/src/axi_delayer.sv +++ b/src/axi_delayer.sv @@ -40,13 +40,14 @@ module axi_delayer #( input axi_resp_t mst_resp_i ); // AW - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomInput ), .FixedDelay ( FixedDelayInput ), .payload_t ( aw_chan_t ) ) i_stream_delay_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( slv_req_i.aw ), .ready_o ( slv_resp_o.aw_ready ), .valid_i ( slv_req_i.aw_valid ), @@ -56,13 +57,14 @@ module axi_delayer #( ); // AR - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomInput ), .FixedDelay ( FixedDelayInput ), .payload_t ( ar_chan_t ) ) i_stream_delay_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( slv_req_i.ar ), .ready_o ( slv_resp_o.ar_ready ), .valid_i ( slv_req_i.ar_valid ), @@ -72,13 +74,14 @@ module axi_delayer #( ); // W - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomInput ), .FixedDelay ( FixedDelayInput ), .payload_t ( w_chan_t ) ) i_stream_delay_w ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( slv_req_i.w ), .ready_o ( slv_resp_o.w_ready ), .valid_i ( slv_req_i.w_valid ), @@ -88,13 +91,14 @@ module axi_delayer #( ); // B - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomOutput ), .FixedDelay ( FixedDelayOutput ), .payload_t ( b_chan_t ) ) i_stream_delay_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( mst_resp_i.b ), .ready_o ( mst_req_o.b_ready ), .valid_i ( mst_resp_i.b_valid ), @@ -104,13 +108,14 @@ module axi_delayer #( ); // R - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomOutput ), .FixedDelay ( FixedDelayOutput ), .payload_t ( r_chan_t ) ) i_stream_delay_r ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( mst_resp_i.r ), .ready_o ( mst_req_o.r_ready ), .valid_i ( mst_resp_i.r_valid ), diff --git a/src/axi_demux.sv b/src/axi_demux.sv index 899d83521..c32efca10 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -64,7 +64,6 @@ module axi_demux #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, // Slave Port input axi_req_t slv_req_i, input select_t slv_aw_select_i, @@ -86,12 +85,13 @@ module axi_demux #( select_t slv_aw_select, slv_ar_select; - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_aw_ready_chan ), .data_i ( slv_req_i.aw ), @@ -99,12 +99,13 @@ module axi_demux #( .ready_i ( slv_resp_cut.aw_ready ), .data_o ( slv_req_cut.aw ) ); - spill_register #( - .T ( select_t ), + cc_spill_register #( + .data_t ( select_t ), .Bypass ( ~SpillAw ) ) i_aw_select_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_aw_ready_sel ), .data_i ( slv_aw_select_i ), @@ -116,12 +117,13 @@ module axi_demux #( assign slv_resp_o.aw_ready = slv_aw_ready_chan & slv_aw_ready_sel; assign slv_req_cut.aw_valid = slv_aw_valid_chan & slv_aw_valid_sel; - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -129,12 +131,13 @@ module axi_demux #( .ready_i ( slv_resp_cut.w_ready ), .data_o ( slv_req_cut.w ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_ar_ready_chan ), .data_i ( slv_req_i.ar ), @@ -142,12 +145,13 @@ module axi_demux #( .ready_i ( slv_resp_cut.ar_ready ), .data_o ( slv_req_cut.ar ) ); - spill_register #( - .T ( select_t ), + cc_spill_register #( + .data_t ( select_t ), .Bypass ( ~SpillAr ) ) i_ar_sel_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_ar_ready_sel ), .data_i ( slv_ar_select_i ), @@ -159,12 +163,13 @@ module axi_demux #( assign slv_resp_o.ar_ready = slv_ar_ready_chan & slv_ar_ready_sel; assign slv_req_cut.ar_valid = slv_ar_valid_chan & slv_ar_valid_sel; - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_resp_cut.b_valid ), .ready_o ( slv_req_cut.b_ready ), .data_i ( slv_resp_cut.b ), @@ -172,12 +177,13 @@ module axi_demux #( .ready_i ( slv_req_i.b_ready ), .data_o ( slv_resp_o.b ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_resp_cut.r_valid ), .ready_o ( slv_req_cut.r_ready ), .data_i ( slv_resp_cut.r ), @@ -198,7 +204,6 @@ module axi_demux #( ) i_demux_simple ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( slv_req_cut ), .slv_aw_select_i ( slv_aw_select ), @@ -234,7 +239,6 @@ module axi_demux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable input select_t slv_aw_select_i, // has to be stable, when aw_valid input select_t slv_ar_select_i, // has to be stable, when ar_valid AXI_BUS.Slave slv, // slave port @@ -289,7 +293,6 @@ module axi_demux_intf #( ) i_axi_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable // slave port .slv_req_i ( slv_req ), .slv_aw_select_i ( slv_aw_select_i ), diff --git a/src/axi_demux_id_counters.sv b/src/axi_demux_id_counters.sv index 7e8c88da5..776bfe8b2 100644 --- a/src/axi_demux_id_counters.sv +++ b/src/axi_demux_id_counters.sv @@ -109,13 +109,13 @@ module axi_demux_id_counters #( endcase end - delta_counter #( - .WIDTH ( CounterWidth ), - .STICKY_OVERFLOW ( 1'b0 ) + cc_delta_counter #( + .Width ( CounterWidth ), + .StickyOverflow ( 1'b0 ) ) i_in_flight_cnt ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( cnt_en ), .load_i ( 1'b0 ), .down_i ( cnt_down ), @@ -128,11 +128,11 @@ module axi_demux_id_counters #( assign cnt_full[i] = overflow | (&in_flight); // holds the selection signal for this id - `FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni) + `FFL(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni) // pragma translate_off `ifndef VERILATOR -`ifndef XSIM +`ifndef XILINX_SIMULATOR // Validate parameters. cnt_underflow: assert property( @(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else diff --git a/src/axi_demux_simple.sv b/src/axi_demux_simple.sv index 3f854c14f..714a5675e 100644 --- a/src/axi_demux_simple.sv +++ b/src/axi_demux_simple.sv @@ -55,7 +55,6 @@ module axi_demux_simple #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, // Slave Port input axi_req_t slv_req_i, input select_t slv_aw_select_i, @@ -66,7 +65,7 @@ module axi_demux_simple #( input axi_resp_t [NoMstPorts-1:0] mst_resps_i ); - localparam int unsigned IdCounterWidth = cf_math_pkg::idx_width(MaxTrans); + localparam int unsigned IdCounterWidth = cc_pkg::idx_width(MaxTrans); typedef logic [IdCounterWidth-1:0] id_cnt_t; // pass through if only one master port @@ -195,7 +194,7 @@ module axi_demux_simple #( // lock the valid signal, as the selection gets pushed into the W FIFO on first assertion, // prevent further pushing - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) if (UniqueIds) begin : gen_unique_ids_aw // If the `UniqueIds` parameter is set, each write transaction has an ID that is unique among @@ -234,13 +233,13 @@ module axi_demux_simple #( // `w_select` determines, which handshaking is connected. // AWs are only forwarded, if the counter is empty, or `w_select_q` is the same as // `slv_aw_select_i`. - counter #( - .WIDTH ( IdCounterWidth ), - .STICKY_OVERFLOW ( 1'b0 ) + cc_counter #( + .Width ( IdCounterWidth ), + .StickyOverflow ( 1'b0 ) ) i_counter_open_w ( .clk_i, .rst_ni, - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( w_cnt_up ^ w_cnt_down ), .load_i ( 1'b0 ), .down_i ( w_cnt_down ), @@ -249,7 +248,7 @@ module axi_demux_simple #( .overflow_o ( /*not used*/ ) ); - `FFLARN(w_select_q, slv_aw_select_i, w_cnt_up, select_t'(0), clk_i, rst_ni) + `FFL(w_select_q, slv_aw_select_i, w_cnt_up, select_t'(0), clk_i, rst_ni) assign w_select = (|w_open) ? w_select_q : slv_aw_select_i; assign w_select_valid = w_cnt_up | (|w_open); @@ -260,18 +259,18 @@ module axi_demux_simple #( //-------------------------------------- // B Channel //-------------------------------------- - logic [cf_math_pkg::idx_width(NoMstPorts)-1:0] b_idx; + logic [cc_pkg::idx_width(NoMstPorts)-1:0] b_idx; // Arbitration of the different B responses - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn ( NoMstPorts ), - .DataType ( logic ), + .data_t ( logic ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) ) i_b_mux ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( mst_b_valids ), .gnt_o ( mst_b_readies ), @@ -341,7 +340,7 @@ module axi_demux_simple #( end // this ff is needed so that ar does not get de-asserted if an atop gets injected - `FFLARN(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni) + `FFL(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni) if (UniqueIds) begin : gen_unique_ids_ar // If the `UniqueIds` parameter is set, each read transaction has an ID that is unique among @@ -379,18 +378,18 @@ module axi_demux_simple #( // R Channel //-------------------------------------- - logic [cf_math_pkg::idx_width(NoMstPorts)-1:0] r_idx; + logic [cc_pkg::idx_width(NoMstPorts)-1:0] r_idx; // Arbitration of the different r responses - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn ( NoMstPorts ), - .DataType ( logic ), + .data_t ( logic ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) ) i_r_mux ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( mst_r_valids ), .gnt_o ( mst_r_readies ), @@ -468,7 +467,7 @@ module axi_demux_simple #( AXI_ID_BITS: assume (AxiIdWidth >= AxiLookBits) else $fatal(1, "AxiIdBits has to be equal or smaller than AxiIdWidth."); end -`ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> (slv_aw_select_i < NoMstPorts))) else diff --git a/src/axi_dw_converter.sv b/src/axi_dw_converter.sv index 7e6f6dad3..3f1dff199 100644 --- a/src/axi_dw_converter.sv +++ b/src/axi_dw_converter.sv @@ -11,9 +11,9 @@ // Authors: // - Matheus Cavalcante -// NOTE: The upsizer does not support WRAP bursts, and will answer with SLVERR -// upon receiving a burst of such type. In addition to that, the downsizer also -// does not support FIXED bursts with incoming axlen != 0. +// Burst support: INCR fully supported. FIXED passed through when upsizing, +// single-beat only when downsizing (multi-beat answers with SLVERR). WRAP not +// supported, answers with SLVERR (single-beat WRAP tolerated when upsizing). module axi_dw_converter #( parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv index b508e31ca..aaee12d20 100644 --- a/src/axi_dw_downsizer.sv +++ b/src/axi_dw_downsizer.sv @@ -15,10 +15,8 @@ // Data width downsize conversion. // Connects a wide master to a narrower slave. -// NOTE: The downsizer does not support WRAP bursts, and will answer with SLVERR -// upon receiving a burst of such type. The downsizer does support FIXED -// bursts, but only if they consist of a single beat; it will answer with SLVERR -// on multi-beat FIXED bursts. +// Burst support: INCR fully supported. FIXED single-beat only, multi-beat +// answers with SLVERR. WRAP not supported, answers with SLVERR. module axi_dw_downsizer #( parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads parameter int unsigned AxiSlvPortDataWidth = 8 , // Data width of the slv port @@ -53,7 +51,7 @@ module axi_dw_downsizer #( import axi_pkg::aligned_addr; import axi_pkg::modifiable ; - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // Type used to index which adapter is handling each outstanding transaction. localparam TranIdWidth = AxiMaxReads > 1 ? $clog2(AxiMaxReads) : 1; @@ -96,16 +94,16 @@ module axi_dw_downsizer #( logic [AxiMaxReads-1:0] slv_r_valid_tran; logic [AxiMaxReads-1:0] slv_r_ready_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads ), - .DataType (slv_r_chan_t), + .data_t ( slv_r_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_slv_r_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (slv_r_valid_tran ), .gnt_o (slv_r_ready_tran ), @@ -132,7 +130,7 @@ module axi_dw_downsizer #( assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (2 ), .DataWidth (AxiIdWidth), .ExtPrio (1'b0 ), @@ -141,7 +139,7 @@ module axi_dw_downsizer #( ) i_slv_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i (1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid} ), .gnt_o ({inject_aw_into_ar_gnt, slv_resp_o.ar_ready}), @@ -158,16 +156,16 @@ module axi_dw_downsizer #( logic [AxiMaxReads-1:0] mst_ar_ready_tran; tran_id_t mst_req_idx; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads), - .DataType (ar_chan_t ), + .data_t ( ar_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_mst_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (mst_ar_valid_tran), .gnt_o (mst_ar_ready_tran), @@ -193,7 +191,6 @@ module axi_dw_downsizer #( ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .slv_req_i (axi_err_req ), .slv_resp_o(axi_err_resp) ); @@ -224,7 +221,6 @@ module axi_dw_downsizer #( ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .mst_reqs_o ({axi_err_req, mst_req_o} ), .mst_resps_i ({axi_err_resp, mst_resp_i} ), .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), @@ -276,8 +272,9 @@ module axi_dw_downsizer #( // Find an idle downsizer to handle this transaction tran_id_t idx_idle_downsizer; - lzc #( - .WIDTH(AxiMaxReads) + cc_lzc #( + .Width (AxiMaxReads), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_idle_lzc ( .in_i (idle_read_downsizer), .cnt_o (idx_idle_downsizer ), @@ -291,11 +288,11 @@ module axi_dw_downsizer #( assign id_clash_downsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_downsizer[t]; end - onehot_to_bin #( - .ONEHOT_WIDTH(AxiMaxReads) + cc_onehot_to_bin #( + .OnehotWidth (AxiMaxReads) ) i_id_clash_onehot_to_bin ( - .onehot(id_clash_downsizer ), - .bin (idx_id_clash_downsizer) + .onehot_i (id_clash_downsizer ), + .bin_o (idx_id_clash_downsizer) ); // Choose an idle downsizer, unless there is an id clash @@ -309,13 +306,14 @@ module axi_dw_downsizer #( tran_id_t idqueue_id; logic idqueue_valid; - id_queue #( - .ID_WIDTH(AxiIdWidth ), - .CAPACITY(AxiMaxReads), + cc_id_queue #( + .IdWidth ( AxiIdWidth ), + .Capacity ( AxiMaxReads ), .data_t (tran_id_t ) ) i_read_id_queue ( .clk_i (clk_i ), .rst_ni (rst_ni ), + .clr_i ( 1'b0 ), .inp_id_i (arb_slv_ar_id ), .inp_data_i (idx_ar_downsizer), .inp_req_i (|idqueue_push ), @@ -679,15 +677,15 @@ module axi_dw_downsizer #( logic forward_b_beat_pop; logic forward_b_beat_full; - fifo_v3 #( - .DATA_WIDTH (1 ), - .DEPTH (AxiMaxReads), - .FALL_THROUGH(1'b1 ) + cc_fifo #( + .DataWidth (1 ), + .Depth (AxiMaxReads), + .FallThrough (1'b1 ) ) i_forward_b_beats_queue ( .clk_i (clk_i ), .rst_ni (rst_ni ), + .clr_i ( 1'b0 ), .flush_i (1'b0 ), - .testmode_i(1'b0 ), .data_i (forward_b_beat_i ), .push_i (forward_b_beat_push ), .full_o (forward_b_beat_full ), diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv index 623df8235..1d2e3fe79 100644 --- a/src/axi_dw_upsizer.sv +++ b/src/axi_dw_upsizer.sv @@ -15,8 +15,8 @@ // Data width upsize conversion. // Connects a narrow master to a wider slave. -// NOTE: The upsizer does not support WRAP bursts, and will answer with SLVERR -// upon receiving a burst of such type. +// Burst support: INCR fully supported. FIXED passed through unmodified. +// WRAP not supported, answers with SLVERR (single-beat WRAP is tolerated). module axi_dw_upsizer #( parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads @@ -53,7 +53,7 @@ module axi_dw_upsizer #( import axi_pkg::beat_addr ; import axi_pkg::modifiable ; - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // Type used to index which adapter is handling each outstanding transaction. localparam TranIdWidth = AxiMaxReads > 1 ? $clog2(AxiMaxReads) : 1; @@ -93,16 +93,16 @@ module axi_dw_upsizer #( logic [AxiMaxReads-1:0] slv_r_valid_tran; logic [AxiMaxReads-1:0] slv_r_ready_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads ), - .DataType (slv_r_chan_t), + .data_t ( slv_r_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_slv_r_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (slv_r_valid_tran ), .gnt_o (slv_r_ready_tran ), @@ -129,7 +129,7 @@ module axi_dw_upsizer #( assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (2 ), .DataWidth (AxiIdWidth), .ExtPrio (1'b0 ), @@ -138,7 +138,7 @@ module axi_dw_upsizer #( ) i_slv_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid} ), .gnt_o ({inject_aw_into_ar_gnt, slv_resp_o.ar_ready}), @@ -155,16 +155,16 @@ module axi_dw_upsizer #( logic [AxiMaxReads-1:0] mst_ar_ready_tran; tran_id_t mst_req_idx; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads), - .DataType (ar_chan_t ), + .data_t ( ar_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_mst_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (mst_ar_valid_tran), .gnt_o (mst_ar_ready_tran), @@ -190,7 +190,6 @@ module axi_dw_upsizer #( ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .slv_req_i (axi_err_req ), .slv_resp_o(axi_err_resp) ); @@ -221,7 +220,6 @@ module axi_dw_upsizer #( ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .mst_reqs_o ({axi_err_req, mst_req_o} ), .mst_resps_i ({axi_err_resp, mst_resp_i} ), .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), @@ -260,8 +258,9 @@ module axi_dw_upsizer #( // Find an idle upsizer to handle this transaction tran_id_t idx_idle_upsizer; - lzc #( - .WIDTH(AxiMaxReads) + cc_lzc #( + .Width (AxiMaxReads), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_idle_lzc ( .in_i (idle_read_upsizer), .cnt_o (idx_idle_upsizer ), @@ -275,11 +274,11 @@ module axi_dw_upsizer #( assign id_clash_upsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_upsizer[t]; end - onehot_to_bin #( - .ONEHOT_WIDTH(AxiMaxReads) + cc_onehot_to_bin #( + .OnehotWidth (AxiMaxReads) ) i_id_clash_onehot_to_bin ( - .onehot(id_clash_upsizer ), - .bin (idx_id_clash_upsizer) + .onehot_i (id_clash_upsizer ), + .bin_o (idx_id_clash_upsizer) ); // Choose an idle upsizer, unless there is an id clash @@ -300,11 +299,11 @@ module axi_dw_upsizer #( assign rid_upsizer_match[t] = (mst_resp.r.id == mst_ar_id[t]) && !idle_read_upsizer[t]; end - onehot_to_bin #( - .ONEHOT_WIDTH(AxiMaxReads) + cc_onehot_to_bin #( + .OnehotWidth (AxiMaxReads) ) i_rid_upsizer_lzc ( - .onehot(rid_upsizer_match), - .bin (idx_r_upsizer ) + .onehot_i (rid_upsizer_match), + .bin_o (idx_r_upsizer ) ); typedef struct packed { diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index 9035d9a80..f0be32914 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -28,7 +28,6 @@ module axi_err_slv #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave port input axi_req_t slv_req_i, output axi_resp_t slv_resp_o @@ -87,15 +86,15 @@ module axi_err_slv #( assign w_fifo_push = err_req.aw_valid & ~w_fifo_full; assign err_resp.aw_ready = ~w_fifo_full; - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( MaxTrans ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( MaxTrans ), + .data_t ( id_t ) ) i_w_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( test_i ), .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( ), @@ -120,15 +119,15 @@ module axi_err_slv #( end end - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( unsigned'(2) ), // two placed so that w can eat beats if b is not sent - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( unsigned'(2) ), // two placed so that w can eat beats if b is not sent + .data_t ( id_t ) ) i_b_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( test_i ), .full_o ( b_fifo_full ), .empty_o ( b_fifo_empty ), .usage_o ( ), @@ -162,15 +161,15 @@ module axi_err_slv #( assign r_fifo_inp.id = err_req.ar.id; assign r_fifo_inp.len = err_req.ar.len; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MaxTrans ), - .dtype ( r_data_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MaxTrans ), + .data_t ( r_data_t ) ) i_r_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( r_fifo_full ), .empty_o ( r_fifo_empty ), .usage_o ( ), @@ -228,12 +227,12 @@ module axi_err_slv #( end end - counter #( - .WIDTH ($bits(axi_pkg::len_t)) + cc_counter #( + .Width ($bits(axi_pkg::len_t)) ) i_r_counter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( r_cnt_clear ), + .clr_i ( r_cnt_clear ), .en_i ( r_cnt_en ), .load_i ( r_cnt_load ), .down_i ( 1'b1 ), @@ -248,7 +247,7 @@ module axi_err_slv #( assert (Resp == axi_pkg::RESP_DECERR || Resp == axi_pkg::RESP_SLVERR) else $fatal(1, "This module may only generate RESP_DECERR or RESP_SLVERR responses!"); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); if (!ATOPs) begin : gen_assert_atops_unsupported assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0)) else diff --git a/src/axi_fifo.sv b/src/axi_fifo.sv index 8e4cbdfb1..0b854b82a 100644 --- a/src/axi_fifo.sv +++ b/src/axi_fifo.sv @@ -33,7 +33,6 @@ module axi_fifo #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // slave port input axi_req_t slv_req_i, output axi_resp_t slv_resp_o, @@ -63,15 +62,15 @@ module axi_fifo #( assign mst_req_o.b_ready = ~b_fifo_full; // A FiFo for each channel - fifo_v3 #( - .dtype(aw_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (aw_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_aw_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (aw_fifo_full), .empty_o (aw_fifo_empty), .usage_o (), @@ -80,15 +79,15 @@ module axi_fifo #( .data_o (mst_req_o.aw), .pop_i (mst_req_o.aw_valid && mst_resp_i.aw_ready) ); - fifo_v3 #( - .dtype(ar_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (ar_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_ar_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (ar_fifo_full), .empty_o (ar_fifo_empty), .usage_o (), @@ -97,15 +96,15 @@ module axi_fifo #( .data_o (mst_req_o.ar), .pop_i (mst_req_o.ar_valid && mst_resp_i.ar_ready) ); - fifo_v3 #( - .dtype(w_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (w_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_w_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (w_fifo_full), .empty_o (w_fifo_empty), .usage_o (), @@ -114,15 +113,15 @@ module axi_fifo #( .data_o (mst_req_o.w), .pop_i (mst_req_o.w_valid && mst_resp_i.w_ready) ); - fifo_v3 #( - .dtype(r_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (r_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_r_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (r_fifo_full), .empty_o (r_fifo_empty), .usage_o (), @@ -131,15 +130,15 @@ module axi_fifo #( .data_o (slv_resp_o.r), .pop_i (slv_resp_o.r_valid && slv_req_i.r_ready) ); - fifo_v3 #( - .dtype(b_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (b_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_b_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (b_fifo_full), .empty_o (b_fifo_empty), .usage_o (), @@ -174,7 +173,6 @@ module axi_fifo_intf #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_BUS.Slave slv, AXI_BUS.Master mst ); @@ -215,7 +213,6 @@ module axi_fifo_intf #( ) i_axi_fifo ( .clk_i, .rst_ni, - .test_i, .slv_req_i (slv_req), .slv_resp_o(slv_resp), .mst_req_o (mst_req), diff --git a/src/axi_fifo_delay_dyn.sv b/src/axi_fifo_delay_dyn.sv index c06db637d..870efb5a6 100644 --- a/src/axi_fifo_delay_dyn.sv +++ b/src/axi_fifo_delay_dyn.sv @@ -283,7 +283,7 @@ module stream_fifo_delay_dyn #( `endif `endif - if (Depth & (Depth - 1) == 0) + if (Depth == 0 || (Depth & (Depth - 1)) != 0) $fatal(1, "Depth must be a power of two"); localparam int unsigned BookeepingBits = $clog2(Depth) + 1; @@ -327,12 +327,12 @@ module stream_fifo_delay_dyn #( assign payload_o = head_data; - counter #( - .WIDTH ( CounterWidth ) + cc_counter #( + .Width ( CounterWidth ) ) i_counter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( 1'b1 ), .load_i ( 1'b0 ), .down_i ( 1'b0 ), @@ -374,15 +374,15 @@ module stream_fifo_delay_dyn #( .dout ( head_data ) ); `else - fifo_v3 #( - .DATA_WIDTH ( $bits(payload_t) ), - .DEPTH ( Depth ), - .FALL_THROUGH ( 1'b0 ) + cc_fifo #( + .DataWidth ( $bits(payload_t) ), + .Depth ( Depth ), + .FallThrough ( 1'b0 ) ) data_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( payload_i ), .push_i ( fifo_data_push ), .full_o ( fifo_data_full ), @@ -426,15 +426,15 @@ module stream_fifo_delay_dyn #( .dout ( head_deadline ) ); `else - fifo_v3 #( - .DATA_WIDTH ( CounterWidth ), - .DEPTH ( Depth ), - .FALL_THROUGH ( 1'b0 ) + cc_fifo #( + .DataWidth ( CounterWidth ), + .Depth ( Depth ), + .FallThrough ( 1'b0 ) ) deadline_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( tail_deadline ), .push_i ( fifo_dead_push ), .full_o ( fifo_dead_full ), diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv index f97c52fd1..00782f630 100644 --- a/src/axi_id_remap.sv +++ b/src/axi_id_remap.sv @@ -128,7 +128,7 @@ module axi_id_remap #( // Remap tables keep track of in-flight bursts and their input and output IDs. - localparam int unsigned IdxWidth = cf_math_pkg::idx_width(AxiSlvPortMaxUniqIds); + localparam int unsigned IdxWidth = cc_pkg::idx_width(AxiSlvPortMaxUniqIds); typedef logic [AxiSlvPortMaxUniqIds-1:0] field_t; typedef logic [AxiSlvPortIdWidth-1:0] id_inp_t; typedef logic [IdxWidth-1:0] idx_t; @@ -185,9 +185,9 @@ module axi_id_remap #( .pop_inp_id_o ( slv_resp_o.r.id ) ); assign both_free = wr_free & rd_free; - lzc #( - .WIDTH ( AxiSlvPortMaxUniqIds ), - .MODE ( 1'b0 ) + cc_lzc #( + .Width ( AxiSlvPortMaxUniqIds ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc ( .in_i ( both_free ), .cnt_o ( both_free_oup_id ), @@ -415,10 +415,10 @@ module axi_id_remap #( end // Registers - `FFARN(ar_id_q, ar_id_d, '0, clk_i, rst_ni) - `FFARN(ar_prio_q, ar_prio_d, 1'b0, clk_i, rst_ni) - `FFARN(aw_id_q, aw_id_d, '0, clk_i, rst_ni) - `FFARN(state_q, state_d, Ready, clk_i, rst_ni) + `FF(ar_id_q, ar_id_d, '0, clk_i, rst_ni) + `FF(ar_prio_q, ar_prio_d, 1'b0, clk_i, rst_ni) + `FF(aw_id_q, aw_id_d, '0, clk_i, rst_ni) + `FF(state_q, state_d, Ready, clk_i, rst_ni) // pragma translate_off `ifndef VERILATOR @@ -452,7 +452,7 @@ module axi_id_remap #( assert ($bits(mst_req_o.ar.id) == AxiMstPortIdWidth); assert ($bits(mst_resp_i.r.id) == AxiMstPortIdWidth); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assert property (@(posedge clk_i) slv_req_i.aw_valid && slv_resp_o.aw_ready |-> mst_req_o.aw_valid && mst_resp_i.aw_ready); @@ -505,7 +505,7 @@ module axi_id_remap_table #( localparam type id_inp_t = logic [InpIdWidth-1:0], /// Derived (**=do not override**) width of table index (ceiled binary logarithm of /// `MaxUniqInpIds`). - localparam int unsigned IdxWidth = cf_math_pkg::idx_width(MaxUniqInpIds), + localparam int unsigned IdxWidth = cc_pkg::idx_width(MaxUniqInpIds), /// Derived (**=do not override**) type of table index (width = `IdxWidth`). localparam type idx_t = logic [IdxWidth-1:0], /// Derived (**=do not override**) type with one bit per table entry (thus also output ID). @@ -569,9 +569,9 @@ module axi_id_remap_table #( for (genvar i = 0; i < MaxUniqInpIds; i++) begin : gen_free_o assign free_o[i] = table_q[i].cnt == '0; end - lzc #( - .WIDTH ( MaxUniqInpIds ), - .MODE ( 1'b0 ) + cc_lzc #( + .Width ( MaxUniqInpIds ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc_free ( .in_i ( free_o ), .cnt_o ( free_oup_id_o ), @@ -591,9 +591,9 @@ module axi_id_remap_table #( assign match[i] = table_q[i].cnt > 0 && table_q[i].inp_id == exists_inp_id_i; end logic no_match; - lzc #( - .WIDTH ( MaxUniqInpIds ), - .MODE ( 1'b0 ) + cc_lzc #( + .Width ( MaxUniqInpIds ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc_match ( .in_i ( match ), .cnt_o ( exists_oup_id_o ), @@ -619,12 +619,12 @@ module axi_id_remap_table #( end // Registers - `FFARN(table_q, table_d, '0, clk_i, rst_ni) + `FF(table_q, table_d, '0, clk_i, rst_ni) // Assertions // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assume property (@(posedge clk_i) push_i |-> table_q[push_oup_id_i].cnt == '0 || table_q[push_oup_id_i].inp_id == push_inp_id_i) diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index 94051786c..9cfc82651 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -83,7 +83,7 @@ module axi_id_serialize #( ); /// Number of bits of the slave port ID that determine the mapping to the master port ID - localparam int unsigned SelectWidth = cf_math_pkg::idx_width(AxiMstPortMaxUniqIds); + localparam int unsigned SelectWidth = cc_pkg::idx_width(AxiMstPortMaxUniqIds); /// Slice of slave port IDs that determines the master port ID typedef logic [SelectWidth-1:0] select_t; @@ -200,7 +200,6 @@ module axi_id_serialize #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( slv_req_i ), .slv_aw_select_i ( slv_aw_select ), .slv_ar_select_i ( slv_ar_select ), @@ -270,7 +269,6 @@ module axi_id_serialize #( ) i_axi_mux ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_reqs_i ( from_serializer_reqs ), .slv_resps_o ( from_serializer_resps ), .mst_req_o ( axi_mux_req ), diff --git a/src/axi_interleaved_xbar.sv b/src/axi_interleaved_xbar.sv index 83d215df7..2d04680a7 100644 --- a/src/axi_interleaved_xbar.sv +++ b/src/axi_interleaved_xbar.sv @@ -17,7 +17,7 @@ /// Interleaved version of the crossbar. This module is experimental; use at your own risk. module axi_interleaved_xbar -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter bit ATOPs = 1'b1, @@ -42,7 +42,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_i, input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, output mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, @@ -118,7 +117,7 @@ import cf_math_pkg::idx_width; end end - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .NoRules ( Cfg.NoAddrRules ), .addr_t ( addr_t ), @@ -133,7 +132,7 @@ import cf_math_pkg::idx_width; .default_idx_i ( default_mst_port_i[i] ) ); - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NoAddrRules ), @@ -163,7 +162,7 @@ import cf_math_pkg::idx_width; // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -210,7 +209,6 @@ import cf_math_pkg::idx_width; ) i_axi_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable .slv_req_i ( slv_reqs_mod[i] ), .slv_aw_select_i ( slv_aw_select ), .slv_ar_select_i ( slv_ar_select ), @@ -231,7 +229,6 @@ import cf_math_pkg::idx_width; ) i_axi_err_slv ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable // slave port .slv_req_i ( slv_reqs[i][Cfg.NoMstPorts] ), .slv_resp_o ( slv_resps[i][cfg_NoMstPorts] ) @@ -257,7 +254,6 @@ import cf_math_pkg::idx_width; ) i_axi_err_slv ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( slv_reqs[i][j] ), .slv_resp_o ( slv_resps[i][j] ) ); @@ -292,7 +288,6 @@ import cf_math_pkg::idx_width; ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable .slv_reqs_i ( mst_reqs[i] ), .slv_resps_o ( mst_resps[i] ), .mst_req_o ( mst_ports_req_o[i] ), @@ -302,7 +297,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin : check_params id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); @@ -318,7 +313,7 @@ endmodule : axi_interleaved_xbar `include "axi/typedef.svh" module axi_interleaved_xbar_intf -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter int unsigned AXI_USER_WIDTH = 0, @@ -332,7 +327,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, @@ -404,7 +398,6 @@ import cf_math_pkg::idx_width; ) i_interleaved_xbar ( .clk_i, .rst_ni, - .test_i, .slv_ports_req_i (slv_reqs ), .slv_ports_resp_o (slv_resps), .mst_ports_req_o (mst_reqs ), diff --git a/src/axi_inval_filter.sv b/src/axi_inval_filter.sv index 272f9043f..fc651ae67 100644 --- a/src/axi_inval_filter.sv +++ b/src/axi_inval_filter.sv @@ -35,7 +35,7 @@ module axi_inval_filter #( input logic inval_ready_i ); - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // Includes `include "axi/typedef.svh" @@ -127,15 +127,15 @@ module axi_inval_filter #( end end - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( MaxTxns ), - .dtype ( aw_chan_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( MaxTxns ), + .data_t ( aw_chan_t ) ) i_aw_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( aw_fifo_full ), .empty_o ( aw_fifo_empty ), .usage_o ( ), diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index cb9a14852..6891b8527 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -115,7 +115,6 @@ module axi_isolate #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i, .slv_aw_select_i ( isolated_o ), .slv_ar_select_i ( isolated_o ), @@ -135,7 +134,6 @@ module axi_isolate #( ) i_axi_err_slv ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( demux_req[1] ), .slv_resp_o ( demux_rsp[1] ) ); @@ -200,11 +198,11 @@ module axi_isolate_inner #( cnt_t pending_ar_d, pending_ar_q; logic update_ar_cnt; - `FFLARN(pending_aw_q, pending_aw_d, update_aw_cnt, '0, clk_i, rst_ni) - `FFLARN(pending_w_q, pending_w_d, update_w_cnt, '0, clk_i, rst_ni) - `FFLARN(pending_ar_q, pending_ar_d, update_ar_cnt, '0, clk_i, rst_ni) - `FFLARN(state_aw_q, state_aw_d, update_aw_state, Isolate, clk_i, rst_ni) - `FFLARN(state_ar_q, state_ar_d, update_ar_state, Isolate, clk_i, rst_ni) + `FFL(pending_aw_q, pending_aw_d, update_aw_cnt, '0, clk_i, rst_ni) + `FFL(pending_w_q, pending_w_d, update_w_cnt, '0, clk_i, rst_ni) + `FFL(pending_ar_q, pending_ar_d, update_ar_cnt, '0, clk_i, rst_ni) + `FFL(state_aw_q, state_aw_d, update_aw_state, Isolate, clk_i, rst_ni) + `FFL(state_ar_q, state_ar_d, update_ar_state, Isolate, clk_i, rst_ni) // Update counters. always_comb begin @@ -392,7 +390,7 @@ module axi_isolate_inner #( initial begin assume (NumPending > 0) else $fatal(1, "At least one pending transaction required."); end -`ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_overflow: assert property (@(posedge clk_i) (pending_aw_q == '1) |=> (pending_aw_q != '0)) else diff --git a/src/axi_lfsr.sv b/src/axi_lfsr.sv index 2085a76fe..530d581d3 100644 --- a/src/axi_lfsr.sv +++ b/src/axi_lfsr.sv @@ -33,8 +33,6 @@ module axi_lfsr #( input logic clk_i, /// Active-low reset input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4 request struct input axi_req_t req_i, /// AXI4 response struct @@ -93,7 +91,6 @@ module axi_lfsr #( ) i_axi_to_axi_lite ( .clk_i, .rst_ni, - .test_i ( testmode_i ), .slv_req_i ( req_i ), .slv_resp_o ( rsp_o ), .mst_req_o ( axi_lite_req ), @@ -107,7 +104,6 @@ module axi_lfsr #( ) i_axi_lite_lfsr ( .clk_i, .rst_ni, - .testmode_i, .w_ser_data_i, .w_ser_data_o, .w_ser_en_i, diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv index 1b979d874..edc5a3d2a 100644 --- a/src/axi_lite_demux.sv +++ b/src/axi_lite_demux.sv @@ -45,7 +45,6 @@ module axi_lite_demux #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, // slave port (AXI4-Lite input), connect master module here input axi_req_t slv_req_i, input select_t slv_aw_select_i, @@ -70,12 +69,13 @@ module axi_lite_demux #( if (NoMstPorts == 32'd1) begin : gen_no_demux // degenerate case, connect slave to master port - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_resp_o.aw_ready ), .data_i ( slv_req_i.aw ), @@ -83,12 +83,13 @@ module axi_lite_demux #( .ready_i ( mst_resps_i[0].aw_ready ), .data_o ( mst_reqs_o[0].aw ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -96,12 +97,13 @@ module axi_lite_demux #( .ready_i ( mst_resps_i[0].w_ready ), .data_o ( mst_reqs_o[0].w ) ); - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resps_i[0].b_valid ), .ready_o ( mst_reqs_o[0].b_ready ), .data_i ( mst_resps_i[0].b ), @@ -109,12 +111,13 @@ module axi_lite_demux #( .ready_i ( slv_req_i.b_ready ), .data_o ( slv_resp_o.b ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_resp_o.ar_ready ), .data_i ( slv_req_i.ar ), @@ -122,12 +125,13 @@ module axi_lite_demux #( .ready_i ( mst_resps_i[0].ar_ready ), .data_o ( mst_reqs_o[0].ar ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resps_i[0].r_valid ), .ready_o ( mst_reqs_o[0].r_ready ), .data_i ( mst_resps_i[0].r ), @@ -194,7 +198,7 @@ module axi_lite_demux #( //-------------------------------------- `ifdef TARGET_VSIM // Workaround for bug in Questa 2020.2 and 2021.1: Flatten the struct into a logic vector before - // instantiating `spill_register`. + // instantiating `cc_spill_register`. typedef logic [$bits(aw_chan_select_t)-1:0] aw_chan_select_flat_t; `else // Other tools, such as VCS, have problems with `$bits()`, so the workaround cannot be used @@ -204,12 +208,13 @@ module axi_lite_demux #( aw_chan_select_flat_t slv_aw_chan_select_in_flat, slv_aw_chan_select_out_flat; assign slv_aw_chan_select_in_flat = {slv_req_i.aw, slv_aw_select_i}; - spill_register #( - .T ( aw_chan_select_flat_t ), + cc_spill_register #( + .data_t ( aw_chan_select_flat_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_resp_o.aw_ready ), .data_i ( slv_aw_chan_select_in_flat ), @@ -265,17 +270,17 @@ module axi_lite_demux #( // lock the valid signal, as the selection gets pushed into the W FIFO on first assertion, // prevent further pushing - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) - fifo_v3 #( - .FALL_THROUGH( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_w_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemtion rule - .testmode_i ( test_i ), .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( /*not used*/ ), @@ -288,12 +293,13 @@ module axi_lite_demux #( //-------------------------------------- // W Channel //-------------------------------------- - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -311,15 +317,15 @@ module axi_lite_demux #( assign slv_w_ready = ~w_fifo_empty & ~b_fifo_full & mst_resps_i[w_select].w_ready; assign w_fifo_pop = slv_w_valid & slv_w_ready; - fifo_v3 #( - .FALL_THROUGH( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_b_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption - .testmode_i ( test_i ), .full_o ( b_fifo_full ), .empty_o ( b_fifo_empty ), .usage_o ( /*not used*/ ), @@ -332,12 +338,13 @@ module axi_lite_demux #( //-------------------------------------- // B Channel //-------------------------------------- - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_b_valid ), .ready_o ( slv_b_ready ), .data_i ( slv_b_chan ), @@ -366,12 +373,13 @@ module axi_lite_demux #( ar_chan_select_flat_t slv_ar_chan_select_in_flat, slv_ar_chan_select_out_flat; assign slv_ar_chan_select_in_flat = {slv_req_i.ar, slv_ar_select_i}; - spill_register #( - .T ( ar_chan_select_flat_t ), + cc_spill_register #( + .data_t ( ar_chan_select_flat_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_resp_o.ar_ready ), .data_i ( slv_ar_chan_select_in_flat ), @@ -390,15 +398,15 @@ module axi_lite_demux #( assign slv_ar_ready = ~r_fifo_full & mst_resps_i[slv_ar_chan.select].ar_ready; assign r_fifo_push = slv_ar_valid & slv_ar_ready; - fifo_v3 #( - .FALL_THROUGH( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_r_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption rule - .testmode_i ( test_i ), .full_o ( r_fifo_full ), .empty_o ( r_fifo_empty ), .usage_o ( /*not used*/ ), @@ -411,12 +419,13 @@ module axi_lite_demux #( //-------------------------------------- // R Channel //-------------------------------------- - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_r_valid ), .ready_o ( slv_r_ready ), .data_i ( slv_r_chan ), @@ -442,7 +451,7 @@ module axi_lite_demux #( // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> (slv_aw_select_i < NoMstPorts))) else @@ -498,7 +507,6 @@ module axi_lite_demux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable input select_t slv_aw_select_i, // has to be stable, when aw_valid input select_t slv_ar_select_i, // has to be stable, when ar_valid AXI_LITE.Slave slv, // slave port @@ -547,7 +555,6 @@ module axi_lite_demux_intf #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i, // slave Port .slv_req_i ( slv_req ), .slv_aw_select_i ( slv_aw_select_i ), // must be stable while slv_aw_valid_i diff --git a/src/axi_lite_dw_converter.sv b/src/axi_lite_dw_converter.sv index 139c2d313..daf20fd23 100644 --- a/src/axi_lite_dw_converter.sv +++ b/src/axi_lite_dw_converter.sv @@ -133,12 +133,13 @@ module axi_lite_dw_converter #( axi_lite_aw_t aw_chan_spill; logic aw_chan_spill_valid, aw_chan_spill_ready; - spill_register #( - .T ( axi_lite_aw_t ), + cc_spill_register #( + .data_t ( axi_lite_aw_t ), .Bypass ( 1'b0 ) ) i_spill_register_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_res_o.aw_ready ), .data_i ( slv_req_i.aw ), @@ -160,17 +161,18 @@ module axi_lite_dw_converter #( assign aw_sel_load = mst_req_o.aw_valid & mst_res_i.aw_ready; assign aw_sel_d = sel_t'(aw_sel_q + 1'b1); - `FFLARN(aw_sel_q, aw_sel_d, aw_sel_load, '0, clk_i, rst_ni) + `FFL(aw_sel_q, aw_sel_d, aw_sel_load, '0, clk_i, rst_ni) // Input spill register of the W channel. axi_lite_slv_w_t w_chan_spill; logic w_chan_spill_valid, w_chan_spill_ready; - spill_register #( - .T ( axi_lite_slv_w_t ), + cc_spill_register #( + .data_t ( axi_lite_slv_w_t ), .Bypass ( 1'b0 ) ) i_spill_register_w ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_res_o.w_ready ), .data_i ( slv_req_i.w ), @@ -193,7 +195,7 @@ module axi_lite_dw_converter #( assign w_sel_load = mst_req_o.w_valid & mst_res_i.w_ready; assign w_sel_d = sel_t'(w_sel_q + 1'b1); - `FFLARN(w_sel_q, w_sel_d, w_sel_load, '0, clk_i, rst_ni) + `FFL(w_sel_q, w_sel_d, w_sel_load, '0, clk_i, rst_ni) // B response aggregation // Slave port B output is the aggregated error of the last few B responses. @@ -216,20 +218,21 @@ module axi_lite_dw_converter #( assign b_sel_d = sel_t'(b_sel_q + 1'b1); assign b_resp_d = (&b_sel_q) ? axi_pkg::RESP_OKAY : (b_resp_q | mst_res_i.b.resp); assign b_resp_load = mst_res_i.b_valid & mst_req_o.b_ready; - `FFLARN(b_sel_q, b_sel_d, b_resp_load, '0, clk_i, rst_ni) - `FFLARN(b_resp_q, b_resp_d, b_resp_load, axi_pkg::RESP_OKAY, clk_i, rst_ni) + `FFL(b_sel_q, b_sel_d, b_resp_load, '0, clk_i, rst_ni) + `FFL(b_resp_q, b_resp_d, b_resp_load, axi_pkg::RESP_OKAY, clk_i, rst_ni) // Read channels. // Input spill register of the AW channel. axi_lite_ar_t ar_chan_spill; logic ar_chan_spill_valid, ar_chan_spill_ready; - spill_register #( - .T ( axi_lite_ar_t ), + cc_spill_register #( + .data_t ( axi_lite_ar_t ), .Bypass ( 1'b0 ) ) i_spill_register_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_res_o.ar_ready ), .data_i ( slv_req_i.ar ), @@ -251,7 +254,7 @@ module axi_lite_dw_converter #( assign ar_sel_load = mst_req_o.ar_valid & mst_res_i.ar_ready; assign ar_sel_d = sel_t'(ar_sel_q + 1'b1); - `FFLARN(ar_sel_q, ar_sel_d, ar_sel_load, '0, clk_i, rst_ni) + `FFL(ar_sel_q, ar_sel_d, ar_sel_load, '0, clk_i, rst_ni) // Responses have to be aggregated, one FF less, as the last data is feed directly through. sel_t r_sel_q, r_sel_d; @@ -260,11 +263,11 @@ module axi_lite_dw_converter #( logic [DownsizeFactor-2:0] r_chan_mst_load; for (genvar i = 0; unsigned'(i) < (DownsizeFactor-1); i++) begin : gen_r_chan_ff assign r_chan_mst_load[i] = (sel_t'(i) == r_sel_q) & mst_res_i.r_valid & mst_req_o.r_ready; - `FFLARN(r_chan_mst_q[i], mst_res_i.r, r_chan_mst_load[i], axi_lite_mst_r_t'{default: '0}, clk_i, rst_ni) + `FFL(r_chan_mst_q[i], mst_res_i.r, r_chan_mst_load[i], axi_lite_mst_r_t'{default: '0}, clk_i, rst_ni) end assign r_sel_load = mst_res_i.r_valid & mst_req_o.r_ready; assign r_sel_d = sel_t'(r_sel_q + 1'b1); - `FFLARN(r_sel_q, r_sel_d, r_sel_load, '0, clk_i, rst_ni) + `FFL(r_sel_q, r_sel_d, r_sel_load, '0, clk_i, rst_ni) always_comb begin : proc_r_chan_oup slv_res_o.r = axi_lite_slv_r_t'{ @@ -332,20 +335,20 @@ module axi_lite_dw_converter #( end end assign lock_aw_d = ~lock_aw_q; - `FFLARN(lock_aw_q, lock_aw_d, load_aw_lock, 1'b0, clk_i, rst_ni) + `FFL(lock_aw_q, lock_aw_d, load_aw_lock, 1'b0, clk_i, rst_ni) // The selection comes from part of the AW address. assign aw_sel = sel_t'(slv_req_i.aw.addr >> SelOffset); - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( UpsizeFactor ), - .dtype ( sel_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( UpsizeFactor ), + .data_t ( sel_t ) ) i_fifo_w_sel ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( w_full ), .empty_o ( w_empty ), .usage_o ( /*not used*/ ), @@ -414,20 +417,20 @@ module axi_lite_dw_converter #( end end assign lock_ar_d = ~lock_ar_q; - `FFLARN(lock_ar_q, lock_ar_d, load_ar_lock, 1'b0, clk_i, rst_ni) + `FFL(lock_ar_q, lock_ar_d, load_ar_lock, 1'b0, clk_i, rst_ni) // The selection comes from part of the AW address. assign ar_sel = sel_t'(slv_req_i.ar.addr >> SelOffset); - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( UpsizeFactor ), - .dtype ( sel_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( UpsizeFactor ), + .data_t ( sel_t ) ) i_fifo_r_sel ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( r_full ), .empty_o ( r_empty ), .usage_o ( /*not used*/ ), @@ -464,7 +467,7 @@ module axi_lite_dw_converter #( assume ($onehot(AxiSlvPortDataWidth)) else $fatal(1, "AxiSlvPortDataWidth must be power of 2"); assume ($onehot(AxiMstPortDataWidth)) else $fatal(1, "AxiMstPortDataWidth must be power of 2"); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); stable_aw: assert property (@(posedge clk_i) (mst_req_o.aw_valid && !mst_res_i.aw_ready) |=> $stable(mst_req_o.aw)) else diff --git a/src/axi_lite_from_mem.sv b/src/axi_lite_from_mem.sv index 2b7e9e38c..1d2d76619 100644 --- a/src/axi_lite_from_mem.sv +++ b/src/axi_lite_from_mem.sv @@ -170,21 +170,21 @@ module axi_lite_from_mem #( end end - `FFARN(aw_sent_q, aw_sent_d, 1'b0, clk_i, rst_ni) - `FFARN(w_sent_q, w_sent_d, 1'b0, clk_i, rst_ni) + `FF(aw_sent_q, aw_sent_d, 1'b0, clk_i, rst_ni) + `FF(w_sent_q, w_sent_d, 1'b0, clk_i, rst_ni) // Select which response should be forwarded. `1` write response, `0` read response. logic rsp_sel; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), // No fallthrough for one cycle delay before ready on AXI. - .DEPTH ( MaxRequests ), - .dtype ( logic ) + cc_fifo #( + .FallThrough ( 1'b0 ), // No fallthrough for one cycle delay before ready on AXI. + .Depth ( MaxRequests ), + .data_t ( logic ) ) i_fifo_rsp_mux ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( fifo_full ), .empty_o ( fifo_empty ), .usage_o ( /*not used*/ ), @@ -235,7 +235,7 @@ module axi_lite_from_mem #( assert (DataWidth == $bits(axi_rsp_i.r.data)) else $fatal(1, "DataWidth has to match axi_rsp_i.r.data!"); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); assert property (@(posedge clk_i) (mem_req_i && !mem_gnt_o) |=> mem_req_i) else $fatal(1, "It is not allowed to deassert the request if it was not granted!"); diff --git a/src/axi_lite_lfsr.sv b/src/axi_lite_lfsr.sv index 7d4710d5f..e557257e2 100644 --- a/src/axi_lite_lfsr.sv +++ b/src/axi_lite_lfsr.sv @@ -27,8 +27,6 @@ module axi_lite_lfsr #( input logic clk_i, /// Active-low reset input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4 Lite request struct input axi_lite_req_t req_i, /// AXI4 Lite response struct @@ -93,14 +91,14 @@ module axi_lite_lfsr #( end // B - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 'd1 ), - .DEPTH ( 'd2 ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 'd1 ), + .Depth ( 'd2 ) ) i_stream_fifo_w_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( 1'b0 ), @@ -156,7 +154,7 @@ module axi_opt_lfsr #( ); /// Number of bits required to hold the LFSR tab configuration - localparam int unsigned LfsrIdxWidth = cf_math_pkg::idx_width(Width); + localparam int unsigned LfsrIdxWidth = cc_pkg::idx_width(Width); /// Maximum number of tabs localparam int unsigned MaxNumTabs = 4; diff --git a/src/axi_lite_mailbox.sv b/src/axi_lite_mailbox.sv index 13d0785c6..4877e601d 100644 --- a/src/axi_lite_mailbox.sv +++ b/src/axi_lite_mailbox.sv @@ -31,7 +31,6 @@ module axi_lite_mailbox #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave ports [1:0] input req_lite_t [1:0] slv_reqs_i, output resp_lite_t [1:0] slv_resps_o, @@ -120,46 +119,41 @@ module axi_lite_mailbox #( .clear_irq_o ( clear_irq[1] ) ); - // the usage gets concatinated with the full flag to have consistent threshold detection - logic [FifoUsageWidth-1:0] mbox_0_to_1_usage, mbox_1_to_0_usage; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MailboxDepth ), - .dtype ( data_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MailboxDepth ), + .data_t ( data_t ) ) i_mbox_0_to_1 ( .clk_i, .rst_ni, - .testmode_i( test_i ), + .clr_i ( 1'b0 ), .flush_i ( w_mbox_flush[0] | r_mbox_flush[1] ), .full_o ( mbox_full[0] ), .empty_o ( mbox_empty[0] ), - .usage_o ( mbox_0_to_1_usage ), + .usage_o ( mbox_usage[0] ), .data_i ( mbox_w_data[0] ), .push_i ( mbox_push[0] ), .data_o ( mbox_r_data[1] ), .pop_i ( mbox_pop[1] ) ); - // assign the MSB of the FIFO to the correct usage signal - assign mbox_usage[0] = {mbox_full[0], mbox_0_to_1_usage}; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MailboxDepth ), - .dtype ( data_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MailboxDepth ), + .data_t ( data_t ) ) i_mbox_1_to_0 ( .clk_i, .rst_ni, - .testmode_i( test_i ), + .clr_i ( 1'b0 ), .flush_i ( w_mbox_flush[1] | r_mbox_flush[0] ), .full_o ( mbox_full[1] ), .empty_o ( mbox_empty[1] ), - .usage_o ( mbox_1_to_0_usage ), + .usage_o ( mbox_usage[1] ), .data_i ( mbox_w_data[1] ), .push_i ( mbox_push[1] ), .data_o ( mbox_r_data[0] ), .pop_i ( mbox_pop[0] ) ); - assign mbox_usage[1] = {mbox_full[1], mbox_1_to_0_usage}; for (genvar i = 0; i < 2; i++) begin : gen_irq_conversion if (IrqEdgeTrig) begin : gen_irq_edge @@ -181,7 +175,7 @@ module axi_lite_mailbox #( end end - `FFLARN(irq_q, irq_d, update_irq, '0, clk_i, rst_ni) + `FFL(irq_q, irq_d, update_irq, '0, clk_i, rst_ni) end else begin : gen_irq_level assign irq_o[i] = (IrqActHigh) ? slv_irq[i] : ~slv_irq[i]; end @@ -191,6 +185,8 @@ module axi_lite_mailbox #( `ifndef VERILATOR initial begin : proc_check_params mailbox_depth: assert (MailboxDepth > 1) else $fatal(1, "MailboxDepth has to be at least 2"); + mailbox_depth_pow2: assert ((MailboxDepth & (MailboxDepth - 1)) == 0) + else $fatal(1, "MailboxDepth has to be a power of two (usage_t sizing relies on it)."); axi_addr_width: assert (AxiAddrWidth > 0) else $fatal(1, "AxiAddrWidth has to be > 0"); axi_data_width: assert (AxiDataWidth > 0) else $fatal(1, "AxiDataWidth has to be > 0"); end @@ -292,11 +288,11 @@ module axi_lite_mailbox_slave #( logic update_regs; // register enable signal // register instantiation - `FFLARN(error_q, error_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(wirqt_q, wirqt_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(rirqt_q, rirqt_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(irqs_q, irqs_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(irqen_q, irqen_d, update_regs, '0, clk_i, rst_ni) + `FFL(error_q, error_d, update_regs, '0, clk_i, rst_ni) + `FFL(wirqt_q, wirqt_d, update_regs, '0, clk_i, rst_ni) + `FFL(rirqt_q, rirqt_d, update_regs, '0, clk_i, rst_ni) + `FFL(irqs_q, irqs_d, update_regs, '0, clk_i, rst_ni) + `FFL(irqen_q, irqen_d, update_regs, '0, clk_i, rst_ni) // Mailbox FIFO data assignments for (genvar i = 0; i < (AxiDataWidth/8); i++) begin : gen_w_mbox_data @@ -489,7 +485,7 @@ module axi_lite_mailbox_slave #( // address decoder and response FIFOs for the LITE channel, the port can take a new transaction if // these FIFOs are not full, not fall through to prevent combinational paths to the return path - addr_decode #( + cc_addr_decode #( .NoIndices( NoRegs ), .NoRules ( NoRegs ), .addr_t ( addr_t ), @@ -503,11 +499,12 @@ module axi_lite_mailbox_slave #( .en_default_idx_i ( 1'b0 ), .default_idx_i ( '0 ) ); - spill_register #( - .T ( b_chan_lite_t ) + cc_spill_register #( + .data_t ( b_chan_lite_t ) ) i_b_chan_outp ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( b_valid ), .ready_o ( b_ready ), .data_i ( b_chan ), @@ -515,7 +512,7 @@ module axi_lite_mailbox_slave #( .ready_i ( slv_req_i.b_ready ), .data_o ( slv_resp_o.b ) ); - addr_decode #( + cc_addr_decode #( .NoIndices( NoRegs ), .NoRules ( NoRegs ), .addr_t ( addr_t ), @@ -529,11 +526,12 @@ module axi_lite_mailbox_slave #( .en_default_idx_i ( 1'b0 ), .default_idx_i ( '0 ) ); - spill_register #( - .T ( r_chan_lite_t ) + cc_spill_register #( + .data_t ( r_chan_lite_t ) ) i_r_chan_outp ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( r_valid ), .ready_o ( r_ready ), .data_i ( r_chan ), @@ -566,7 +564,6 @@ module axi_lite_mailbox_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable AXI_LITE.Slave slv [1:0], // slave ports [1:0] output logic [1:0] irq_o, // interrupt output for each port input addr_t [1:0] base_addr_i // base address for each port @@ -600,7 +597,6 @@ module axi_lite_mailbox_intf #( ) i_axi_lite_mailbox ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable // slave ports [1:0] .slv_reqs_i ( slv_reqs ), .slv_resps_o ( slv_resps ), diff --git a/src/axi_lite_mux.sv b/src/axi_lite_mux.sv index 26f97b589..a6820555f 100644 --- a/src/axi_lite_mux.sv +++ b/src/axi_lite_mux.sv @@ -44,7 +44,6 @@ module axi_lite_mux #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable // slave ports (AXI4-Lite inputs), connect master modules here input axi_req_t [NoSlvPorts-1:0] slv_reqs_i, output axi_resp_t [NoSlvPorts-1:0] slv_resps_o, @@ -54,12 +53,13 @@ module axi_lite_mux #( ); // pass through if only one slave port if (NoSlvPorts == 32'h1) begin : gen_no_mux - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].aw_valid ), .ready_o ( slv_resps_o[0].aw_ready ), .data_i ( slv_reqs_i[0].aw ), @@ -67,12 +67,13 @@ module axi_lite_mux #( .ready_i ( mst_resp_i.aw_ready ), .data_o ( mst_req_o.aw ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].w_valid ), .ready_o ( slv_resps_o[0].w_ready ), .data_i ( slv_reqs_i[0].w ), @@ -80,12 +81,13 @@ module axi_lite_mux #( .ready_i ( mst_resp_i.w_ready ), .data_o ( mst_req_o.w ) ); - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -93,12 +95,13 @@ module axi_lite_mux #( .ready_i ( slv_reqs_i[0].b_ready ), .data_o ( slv_resps_o[0].b ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].ar_valid ), .ready_o ( slv_resps_o[0].ar_ready ), .data_i ( slv_reqs_i[0].ar ), @@ -106,12 +109,13 @@ module axi_lite_mux #( .ready_i ( mst_resp_i.ar_ready ), .data_o ( mst_req_o.ar ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), @@ -196,15 +200,15 @@ module axi_lite_mux #( assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid; assign slv_resps_o[i].aw_ready = slv_aw_readies[i]; end - rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( aw_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + cc_rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .data_t ( aw_chan_t ), + .AxiVldRdy ( 1'b1 ), + .LockIn ( 1'b1 ) ) i_aw_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( slv_aw_valids ), .gnt_o ( slv_aw_readies ), @@ -247,17 +251,17 @@ module axi_lite_mux #( end end - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_w_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( ), @@ -267,12 +271,13 @@ module axi_lite_mux #( .pop_i ( w_fifo_pop ) ); - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_aw_valid ), .ready_o ( mst_aw_ready ), .data_i ( mst_aw_chan ), @@ -293,15 +298,15 @@ module axi_lite_mux #( end assign w_fifo_pop = mst_w_valid & mst_w_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_b_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( b_fifo_full ), .empty_o ( b_fifo_empty ), .usage_o ( ), @@ -311,12 +316,13 @@ module axi_lite_mux #( .pop_i ( b_fifo_pop ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_w_valid ), .ready_o ( mst_w_ready ), .data_i ( mst_w_chan ), @@ -336,12 +342,13 @@ module axi_lite_mux #( assign mst_b_ready = ~b_fifo_empty & slv_reqs_i[b_select].b_ready; assign b_fifo_pop = mst_b_valid & mst_b_ready; - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -359,15 +366,15 @@ module axi_lite_mux #( assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid; assign slv_resps_o[i].ar_ready = slv_ar_readies[i]; end - rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( ar_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + cc_rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .data_t ( ar_chan_t ), + .AxiVldRdy ( 1'b1 ), + .LockIn ( 1'b1 ) ) i_ar_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( slv_ar_valids ), .gnt_o ( slv_ar_readies ), @@ -384,15 +391,15 @@ module axi_lite_mux #( assign ar_ready = (!r_fifo_full) ? mst_ar_ready : 1'b0; assign r_fifo_push = mst_ar_valid & mst_ar_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_r_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( r_fifo_full ), .empty_o ( r_fifo_empty ), .usage_o ( ), @@ -402,12 +409,13 @@ module axi_lite_mux #( .pop_i ( r_fifo_pop ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_ar_valid ), .ready_o ( mst_ar_ready ), .data_i ( mst_ar_chan ), @@ -427,12 +435,13 @@ module axi_lite_mux #( assign mst_r_ready = ~r_fifo_empty & slv_reqs_i[r_select].r_ready; assign r_fifo_pop = mst_r_valid & mst_r_ready; - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), @@ -474,7 +483,6 @@ module axi_lite_mux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable AXI_LITE.Slave slv [NoSlvPorts-1:0], // slave ports AXI_LITE.Master mst // master port ); @@ -523,7 +531,6 @@ module axi_lite_mux_intf #( ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable .slv_reqs_i ( slv_reqs ), .slv_resps_o ( slv_resps ), .mst_req_o ( mst_req ), diff --git a/src/axi_lite_regs.sv b/src/axi_lite_regs.sv index 392bd17f1..a6d294f73 100644 --- a/src/axi_lite_regs.sv +++ b/src/axi_lite_regs.sv @@ -141,7 +141,7 @@ module axi_lite_regs #( // Reg byte: B A 9 8 7 6 5 4 3 2 1 0 // | chunk_2 | chunk_1 | chunk_0 | localparam int unsigned AxiStrbWidth = AxiDataWidth / 32'd8; - localparam int unsigned NumChunks = cf_math_pkg::ceil_div(RegNumBytes, AxiStrbWidth); + localparam int unsigned NumChunks = cc_pkg::ceil_div(RegNumBytes, AxiStrbWidth); localparam int unsigned ChunkIdxWidth = (NumChunks > 32'd1) ? $clog2(NumChunks) : 32'd1; // Type of the index to identify a specific register chunk. typedef logic [ChunkIdxWidth-1:0] chunk_idx_t; @@ -313,11 +313,11 @@ module axi_lite_regs #( // Register array mapping, even read only register can be loaded over `reg_load_i`. for (genvar i = 0; i < RegNumBytes; i++) begin : gen_rw_regs - `FFLARN(reg_q[i], reg_d[i], reg_update[i], RegRstVal[i], clk_i, rst_ni) + `FFL(reg_q[i], reg_d[i], reg_update[i], RegRstVal[i], clk_i, rst_ni) assign reg_q_o[i] = reg_q[i]; end - addr_decode #( + cc_addr_decode #( .NoIndices ( NumChunks ), .NoRules ( NumChunks ), .addr_t ( addr_t ), @@ -332,7 +332,7 @@ module axi_lite_regs #( .default_idx_i ( '0 ) ); - addr_decode #( + cc_addr_decode #( .NoIndices ( NumChunks ), .NoRules ( NumChunks ), .addr_t ( addr_t ), @@ -348,12 +348,13 @@ module axi_lite_regs #( ); // Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs. - spill_register #( - .T ( b_chan_lite_t ), + cc_spill_register #( + .data_t ( b_chan_lite_t ), .Bypass ( 1'b0 ) ) i_b_spill_register ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( b_valid ), .ready_o ( b_ready ), .data_i ( b_chan ), @@ -363,12 +364,13 @@ module axi_lite_regs #( ); // Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs. - spill_register #( - .T ( r_chan_lite_t ), + cc_spill_register #( + .data_t ( r_chan_lite_t ), .Bypass ( 1'b0 ) ) i_r_spill_register ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( r_valid ), .ready_o ( r_ready ), .data_i ( r_chan ), @@ -380,7 +382,7 @@ module axi_lite_regs #( // Validate parameters. // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin: p_assertions assert (RegNumBytes > 32'd0) else $fatal(1, "The number of bytes must be at least 1!"); diff --git a/src/axi_lite_to_apb.sv b/src/axi_lite_to_apb.sv index 4d58d0c4a..b35d5e0fe 100644 --- a/src/axi_lite_to_apb.sv +++ b/src/axi_lite_to_apb.sv @@ -146,16 +146,16 @@ module axi_lite_to_apb #( int_resp_t apb_rresp; logic apb_rresp_valid, apb_rresp_ready; - rr_arb_tree #( - .NumIn ( 32'd2 ), - .DataType ( int_req_t ), - .ExtPrio ( 1'b0 ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + cc_rr_arb_tree #( + .NumIn ( 32'd2 ), + .data_t ( int_req_t ), + .ExtPrio ( 1'b0 ), + .AxiVldRdy ( 1'b1 ), + .LockIn ( 1'b1 ) ) i_req_arb ( .clk_i, .rst_ni, - .flush_i ( '0 ), + .clr_i ( '0 ), .rr_i ( '0 ), .req_i ( axi_req_valid ), .gnt_o ( axi_req_ready ), @@ -167,12 +167,13 @@ module axi_lite_to_apb #( ); if (PipelineRequest) begin : gen_req_spill - spill_register #( - .T ( int_req_t ), + cc_spill_register #( + .data_t ( int_req_t ), .Bypass ( 1'b0 ) ) i_req_spill ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( arb_req_valid ), .ready_o ( arb_req_ready ), .data_i ( arb_req ), @@ -181,13 +182,12 @@ module axi_lite_to_apb #( .data_o ( apb_req ) ); end else begin : gen_req_ft_reg - fall_through_register #( - .T ( int_req_t ) + cc_fall_through_register #( + .data_t ( int_req_t ) ) i_req_ft_reg ( .clk_i, .rst_ni, .clr_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .valid_i ( arb_req_valid ), .ready_o ( arb_req_ready ), .data_i ( arb_req ), @@ -198,12 +198,13 @@ module axi_lite_to_apb #( end if (PipelineResponse) begin : gen_resp_spill - spill_register #( - .T ( axi_pkg::resp_t ), + cc_spill_register #( + .data_t ( axi_pkg::resp_t ), .Bypass ( 1'b0 ) ) i_write_resp_spill ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( apb_wresp_valid ), .ready_o ( apb_wresp_ready ), .data_i ( apb_wresp ), @@ -211,12 +212,13 @@ module axi_lite_to_apb #( .ready_i ( axi_lite_req_i.b_ready ), .data_o ( axi_bresp ) ); - spill_register #( - .T ( int_resp_t ), + cc_spill_register #( + .data_t ( int_resp_t ), .Bypass ( 1'b0 ) ) i_read_resp_spill ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( apb_rresp_valid ), .ready_o ( apb_rresp_ready ), .data_i ( apb_rresp ), @@ -225,13 +227,12 @@ module axi_lite_to_apb #( .data_o ( axi_rresp ) ); end else begin : gen_resp_ft_reg - fall_through_register #( - .T ( axi_pkg::resp_t ) + cc_fall_through_register #( + .data_t ( axi_pkg::resp_t ) ) i_write_resp_ft_reg ( .clk_i, .rst_ni, .clr_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .valid_i ( apb_wresp_valid ), .ready_o ( apb_wresp_ready ), .data_i ( apb_wresp ), @@ -239,13 +240,12 @@ module axi_lite_to_apb #( .ready_i ( axi_lite_req_i.b_ready ), .data_o ( axi_bresp ) ); - fall_through_register #( - .T ( int_resp_t ) + cc_fall_through_register #( + .data_t ( int_resp_t ) ) i_read_resp_ft_reg ( .clk_i, .rst_ni, .clr_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .valid_i ( apb_rresp_valid ), .ready_o ( apb_rresp_ready ), .data_i ( apb_rresp ), @@ -264,7 +264,7 @@ module axi_lite_to_apb #( // output of address decoder to determine PSELx signal logic apb_dec_valid; sel_idx_t apb_sel_idx; - addr_decode #( + cc_addr_decode #( .NoIndices( NoApbSlaves ), .NoRules ( NoRules ), .addr_t ( addr_t ), @@ -360,7 +360,7 @@ module axi_lite_to_apb #( endcase end - `FFLARN(apb_state_q, apb_state_d, apb_update, Setup, clk_i, rst_ni) + `FFL(apb_state_q, apb_state_d, apb_update, Setup, clk_i, rst_ni) // parameter check // pragma translate_off @@ -451,11 +451,11 @@ module axi_lite_to_apb_intf #( `AXI_LITE_ASSIGN_TO_REQ(axi_req, slv) `AXI_LITE_ASSIGN_FROM_RESP(slv, axi_resp) - onehot_to_bin #( - .ONEHOT_WIDTH ( NoApbSlaves ) + cc_onehot_to_bin #( + .OnehotWidth ( NoApbSlaves ) ) i_onehot_to_bin ( - .onehot ( pselx_o ), - .bin ( apb_sel ) + .onehot_i ( pselx_o ), + .bin_o ( apb_sel ) ); assign paddr_o = apb_req[apb_sel].paddr; diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv index 72d1e0356..7ce9d5bfa 100644 --- a/src/axi_lite_xbar.sv +++ b/src/axi_lite_xbar.sv @@ -34,7 +34,6 @@ module axi_lite_xbar #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, input axi_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, output axi_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, output axi_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, @@ -76,7 +75,7 @@ module axi_lite_xbar #( full_req_t decerr_req; full_resp_t decerr_resp; - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .NoRules ( Cfg.NoAddrRules ), .addr_t ( addr_t ), @@ -91,7 +90,7 @@ module axi_lite_xbar #( .default_idx_i ( default_mst_port_i[i] ) ); - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NoAddrRules ), @@ -114,7 +113,7 @@ module axi_lite_xbar #( // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -158,7 +157,6 @@ module axi_lite_xbar #( ) i_axi_lite_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable .slv_req_i ( slv_ports_req_i[i] ), .slv_aw_select_i ( slv_aw_select ), .slv_ar_select_i ( slv_ar_select ), @@ -195,7 +193,6 @@ module axi_lite_xbar #( ) i_axi_err_slv ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low - .test_i ( test_i ), // Testmode enable // slave port .slv_req_i ( decerr_req ), .slv_resp_o ( decerr_resp ) @@ -230,7 +227,6 @@ module axi_lite_xbar #( ) i_axi_lite_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable .slv_reqs_i ( mst_reqs[i] ), .slv_resps_o ( mst_resps[i] ), .mst_req_o ( mst_ports_req_o[i] ), @@ -247,7 +243,6 @@ module axi_lite_xbar_intf #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_LITE.Slave slv_ports [Cfg.NoSlvPorts-1:0], AXI_LITE.Master mst_ports [Cfg.NoMstPorts-1:0], input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, @@ -294,7 +289,6 @@ module axi_lite_xbar_intf #( ) i_xbar ( .clk_i, .rst_ni, - .test_i, .slv_ports_req_i (slv_reqs ), .slv_ports_resp_o (slv_resps), .mst_ports_req_o (mst_reqs ), diff --git a/src/axi_mux.sv b/src/axi_mux.sv index da17e2b8c..f194b9cb1 100644 --- a/src/axi_mux.sv +++ b/src/axi_mux.sv @@ -56,7 +56,6 @@ module axi_mux #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable // slave ports (AXI inputs), connect master modules here input slv_req_t [NoSlvPorts-1:0] slv_reqs_i, output slv_resp_t [NoSlvPorts-1:0] slv_resps_o, @@ -70,12 +69,13 @@ module axi_mux #( // pass through if only one slave port if (NoSlvPorts == 32'h1) begin : gen_no_mux - spill_register #( - .T ( mst_aw_chan_t ), + cc_spill_register #( + .data_t ( mst_aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].aw_valid ), .ready_o ( slv_resps_o[0].aw_ready ), .data_i ( slv_reqs_i[0].aw ), @@ -83,12 +83,13 @@ module axi_mux #( .ready_i ( mst_resp_i.aw_ready ), .data_o ( mst_req_o.aw ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].w_valid ), .ready_o ( slv_resps_o[0].w_ready ), .data_i ( slv_reqs_i[0].w ), @@ -96,12 +97,13 @@ module axi_mux #( .ready_i ( mst_resp_i.w_ready ), .data_o ( mst_req_o.w ) ); - spill_register #( - .T ( mst_b_chan_t ), + cc_spill_register #( + .data_t ( mst_b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -109,12 +111,13 @@ module axi_mux #( .ready_i ( slv_reqs_i[0].b_ready ), .data_o ( slv_resps_o[0].b ) ); - spill_register #( - .T ( mst_ar_chan_t ), + cc_spill_register #( + .data_t ( mst_ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].ar_valid ), .ready_o ( slv_resps_o[0].ar_ready ), .data_i ( slv_reqs_i[0].ar ), @@ -122,12 +125,13 @@ module axi_mux #( .ready_i ( mst_resp_i.ar_ready ), .data_o ( mst_req_o.ar ) ); - spill_register #( - .T ( mst_r_chan_t ), + cc_spill_register #( + .data_t ( mst_r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), @@ -261,15 +265,15 @@ module axi_mux #( //-------------------------------------- // AW Channel //-------------------------------------- - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn ( NoSlvPorts ), - .DataType ( mst_aw_chan_t ), + .data_t ( mst_aw_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) ) i_aw_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( slv_aw_valids ), .gnt_o ( slv_aw_readies ), @@ -312,17 +316,17 @@ module axi_mux #( end end - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxWTrans ), - .dtype ( switch_id_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxWTrans ), + .data_t ( switch_id_t ) ) i_w_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( ), @@ -332,12 +336,13 @@ module axi_mux #( .pop_i ( w_fifo_pop ) ); - spill_register #( - .T ( mst_aw_chan_t ), + cc_spill_register #( + .data_t ( mst_aw_chan_t ), .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_aw_valid ), .ready_o ( mst_aw_ready ), .data_i ( mst_aw_chan ), @@ -366,12 +371,13 @@ module axi_mux #( end end - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_w_valid ), .ready_o ( mst_w_ready ), .data_i ( mst_w_chan ), @@ -389,12 +395,13 @@ module axi_mux #( assign switch_b_id = mst_b_chan.id[SlvAxiIDWidth+:MstIdxBits]; assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0; - spill_register #( - .T ( mst_b_chan_t ), + cc_spill_register #( + .data_t ( mst_b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -406,15 +413,15 @@ module axi_mux #( //-------------------------------------- // AR Channel //-------------------------------------- - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn ( NoSlvPorts ), - .DataType ( mst_ar_chan_t ), + .data_t ( mst_ar_chan_t ), .AxiVldRdy( 1'b1 ), .LockIn ( 1'b1 ) ) i_ar_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( slv_ar_valids ), .gnt_o ( slv_ar_readies ), @@ -425,12 +432,13 @@ module axi_mux #( .idx_o ( ) ); - spill_register #( - .T ( mst_ar_chan_t ), + cc_spill_register #( + .data_t ( mst_ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( ar_valid ), .ready_o ( ar_ready ), .data_i ( mst_ar_chan ), @@ -448,12 +456,13 @@ module axi_mux #( assign switch_r_id = mst_r_chan.id[SlvAxiIDWidth+:MstIdxBits]; assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0; - spill_register #( - .T ( mst_r_chan_t ), + cc_spill_register #( + .data_t ( mst_r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), @@ -518,7 +527,6 @@ module axi_mux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports AXI_BUS.Master mst // master port ); @@ -589,7 +597,6 @@ module axi_mux_intf #( ) i_axi_mux ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low - .test_i ( test_i ), // Test Mode enable .slv_reqs_i ( slv_reqs ), .slv_resps_o ( slv_resps ), .mst_req_o ( mst_req ), diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv index 317faa062..5db18c77f 100644 --- a/src/axi_serializer.sv +++ b/src/axi_serializer.sv @@ -146,15 +146,15 @@ module axi_serializer #( mst_req_o.r_ready = slv_req_i.r_ready & ~rd_fifo_empty; end - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), // No fall-through as response has to come a cycle later anyway - .DEPTH ( MaxReadTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), // No fall-through as response has to come a cycle later anyway + .Depth ( MaxReadTxns ), + .data_t ( id_t ) ) i_rd_id_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( ar_id ), .push_i ( rd_fifo_push ), .full_o ( rd_fifo_full ), @@ -166,15 +166,15 @@ module axi_serializer #( // Assign as this condition is needed in FSM assign rd_fifo_pop = slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MaxWriteTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MaxWriteTxns ), + .data_t ( id_t ) ) i_wr_id_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( slv_req_i.aw.id ), .push_i ( wr_fifo_push ), .full_o ( wr_fifo_full ), @@ -186,7 +186,7 @@ module axi_serializer #( // Assign as this condition is needed in FSM assign wr_fifo_pop = slv_resp_o.b_valid & slv_req_i.b_ready; - `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni) + `FF(state_q, state_d, AtopIdle, clk_i, rst_ni) // pragma translate_off `ifndef VERILATOR @@ -197,7 +197,7 @@ module axi_serializer #( assert (MaxWriteTxns >= 1) else $fatal(1, "Maximum number of write transactions must be >= 1!"); end -`ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (~rst_ni); aw_lost : assert property( @(posedge clk_i) (slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready)) diff --git a/src/axi_slave_compare.sv b/src/axi_slave_compare.sv index 6cda82e05..fd91b2a01 100644 --- a/src/axi_slave_compare.sv +++ b/src/axi_slave_compare.sv @@ -47,8 +47,6 @@ module axi_slave_compare #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4+ATOP channel request in input axi_req_t axi_mst_req_i, /// AXI4+ATOP channel response out @@ -92,33 +90,36 @@ module axi_slave_compare #( logic w_ready_mst; logic ar_ready_mst; - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_mst_req_i.aw_valid ), .ready_o ( aw_ready_mst ), .valid_o ( { aw_valid_ref, aw_valid_test } ), .ready_i ( { aw_ready_ref, aw_ready_test } ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_mst_req_i.ar_valid ), .ready_o ( ar_ready_mst ), .valid_o ( { ar_valid_ref, ar_valid_test } ), .ready_i ( { ar_ready_ref, ar_ready_test } ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_w ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_mst_req_i.w_valid ), .ready_o ( w_ready_mst ), .valid_o ( { w_valid_ref, w_valid_test } ), @@ -170,7 +171,6 @@ module axi_slave_compare #( ) i_axi_bus_compare ( .clk_i, .rst_ni, - .testmode_i, .aw_mismatch_o, .w_mismatch_o, .b_mismatch_o, diff --git a/src/axi_test.sv b/src/axi_test.sv index a782422c2..6c059dd4d 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -1253,7 +1253,7 @@ package axi_test; automatic logic [AXI_STRB_WIDTH-1:0] rand_strb, strb_mask; addr = axi_pkg::beat_addr(aw_beat.ax_addr, aw_beat.ax_size, aw_beat.ax_len, aw_beat.ax_burst, i); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); @@ -1416,7 +1416,7 @@ package axi_test; wait (ar_queue.size > 0); ar_beat = ar_queue.peek(); byte_addr = axi_pkg::aligned_addr(ar_beat.ax_addr, axi_pkg::size_t'($clog2(DW/8))); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(r_beat) may behave differently to r_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(r_beat); assert(rand_success); @@ -1516,7 +1516,7 @@ package axi_test; automatic logic rand_success; wait (b_wait_cnt > 0 && (aw_queue.size() != 0)); aw_beat = aw_queue.pop_front(); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(b_beat) may behave differently to b_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(b_beat); assert (rand_success); diff --git a/src/axi_throttle.sv b/src/axi_throttle.sv index 3e7973a08..05f006b91 100644 --- a/src/axi_throttle.sv +++ b/src/axi_throttle.sv @@ -19,9 +19,9 @@ module axi_throttle #( /// AXI4+ATOP response type parameter type axi_rsp_t = logic, /// The width of the write credit counter (*DO NOT OVERWRITE*) - parameter int unsigned WCntWidth = cf_math_pkg::idx_width(MaxNumAwPending), + parameter int unsigned WCntWidth = cc_pkg::idx_width(MaxNumAwPending), /// The width of the read credit counter (*DO NOT OVERWRITE*) - parameter int unsigned RCntWidth = cf_math_pkg::idx_width(MaxNumArPending), + parameter int unsigned RCntWidth = cc_pkg::idx_width(MaxNumArPending), /// The type of the write credit counter (*DO NOT OVERWRITE*) parameter type w_credit_t = logic [WCntWidth-1:0], /// The type of the read credit counter (*DO NOT OVERWRITE*) @@ -56,11 +56,12 @@ module axi_throttle #( logic throttled_ar_ready; // limit Aw requests -> wait for b - stream_throttle #( + cc_stream_throttle #( .MaxNumPending ( MaxNumAwPending ) ) i_stream_throttle_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .req_valid_i ( req_i.aw_valid ), .req_valid_o ( throttled_aw_valid ), .req_ready_i ( rsp_i.aw_ready ), @@ -71,11 +72,12 @@ module axi_throttle #( ); // limit Ar requests -> wait for r.last - stream_throttle #( + cc_stream_throttle #( .MaxNumPending ( MaxNumArPending ) ) i_stream_throttle_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .req_valid_i ( req_i.ar_valid ), .req_valid_o ( throttled_ar_valid ), .req_ready_i ( rsp_i.ar_ready ), diff --git a/src/axi_to_apb.sv b/src/axi_to_apb.sv new file mode 100644 index 000000000..e1c3885c9 --- /dev/null +++ b/src/axi_to_apb.sv @@ -0,0 +1,433 @@ +// Copyright (c) 2024 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Tim Fischer + +// Description: AXI4 to APB4 bridge +// +// Bridges one AXI4 slave port onto one or more APB4 slaves, supporting data-width downsizing +// (`AxiDataWidth` -> `ApbDataWidth`) and address truncation (`AxiAddrWidth` -> `ApbAddrWidth`). It +// composes an `axi_to_detailed_mem` front-end with an inline APB master. +// +// Behaviour notes: +// - ATOPs are not supported (by this module and also APB), and are filtered out with an `axi_atop_filter`. +// - Only `INCR` bursts are supported (`axi_to_detailed_mem` restriction). +// - A wide access is serialized into one APB transfer per active bank, selected via `lzc`. +// Zero-strobe write lanes are dropped by `axi_to_detailed_mem` (`HideStrb`) and never reach the +// bus. For reads, *all* banks are read (even lanes outside a narrow beat's byte range), so avoid +// mapping read-sensitive registers into unaddressed lanes. +// - Address-decode misses are reported as `RESP_SLVERR` (not `RESP_DECERR`; `axi_to_detailed_mem` +// has no decode-error path) and exclusive accesses complete as `RESP_OKAY` (no `EXOKAY`). + +`include "axi/typedef.svh" +`include "axi/assign.svh" +`include "common_cells/registers.svh" + +module axi_to_apb #( + /// Number of connected APB slaves. + parameter int unsigned NoApbSlaves = 32'd1, + /// Number of APB address-decode rules. Set to `0` to omit the address decoder entirely. + ///`NoRules == `0` is only legal with `NoApbSlaves == 1`. + parameter int unsigned NoRules = 32'd1, + /// AXI4 address width. Decoding uses the full width; `paddr` is truncated to `ApbAddrWidth`. + parameter int unsigned AxiAddrWidth = 32'd0, + /// AXI4 data width. Must be an integer power-of-two multiple of `ApbDataWidth`. + parameter int unsigned AxiDataWidth = 32'd0, + /// AXI4 ID width. + parameter int unsigned AxiIdWidth = 32'd0, + /// AXI4 user width. + parameter int unsigned AxiUserWidth = 32'd0, + /// Maximum number of outstanding writes tracked by the `axi_atop_filter`. + parameter int unsigned AxiMaxWriteTxns = 32'd1, + /// Response buffer depth of the internal `axi_to_detailed_mem`. + parameter int unsigned BufDepth = 32'd1, + /// Output FIFO depth of the internal `axi_to_detailed_mem`. + parameter int unsigned OutFifoDepth = 32'd1, + /// APB4 address width. Must be `<= AxiAddrWidth`; the upper AXI address bits are discarded. + parameter int unsigned ApbAddrWidth = 32'd0, + /// APB4 data width. Must be a multiple of 8 and `<= 32` (`ApbDataWidth == 8` is supported). + parameter int unsigned ApbDataWidth = 32'd0, + /// AXI4+ATOP request struct, see `axi/typedef.svh`. + parameter type axi_req_t = logic, + /// AXI4+ATOP response struct, see `axi/typedef.svh`. + parameter type axi_resp_t = logic, + /// APB4 request struct. + parameter type apb_req_t = logic, + /// APB4 response struct. + parameter type apb_resp_t = logic, + /// Address-decode rule struct from `common_cells` (`addr_decode`). + parameter type rule_t = logic +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // AXI4+ATOP slave port + input axi_req_t axi_req_i, + output axi_resp_t axi_resp_o, + // APB master port + output apb_req_t [NoApbSlaves-1:0] apb_req_o, + input apb_resp_t [NoApbSlaves-1:0] apb_resp_i, + // APB slave address map (unused when `NoRules == 0`) + input rule_t [((NoRules > 0) ? NoRules : 1)-1:0] addr_map_i +); + + // Build the address decoder only when rules are provided; otherwise forward everything to slave 0. + localparam bit UseAddrDecode = (NoRules > 32'd0); + + localparam int unsigned NumBanks = AxiDataWidth / ApbDataWidth; + localparam int unsigned SelIdxWidth = (NoApbSlaves > 32'd1) ? $clog2(NoApbSlaves) : 32'd1; + localparam int unsigned BankIdxWidth = (NumBanks > 32'd1) ? $clog2(NumBanks) : 32'd1; + + typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [ApbAddrWidth-1:0] apb_addr_t; + typedef logic [ApbDataWidth-1:0] apb_data_t; + typedef logic [ApbDataWidth/8-1:0] apb_strb_t; + typedef logic [SelIdxWidth-1:0] sel_idx_t; + + typedef enum logic { + Setup = 1'b0, // APB idle / setup phase + Access = 1'b1 // APB access phase + } apb_state_e; + + // 1. Reject atomics with a slave error (APB has no atomic support). + axi_req_t filtered_req; + axi_resp_t filtered_resp; + + axi_atop_filter #( + .AxiIdWidth ( AxiIdWidth ), + .AxiMaxWriteTxns ( AxiMaxWriteTxns ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) + ) i_axi_atop_filter ( + .clk_i, + .rst_ni, + .slv_req_i ( axi_req_i ), + .slv_resp_o ( axi_resp_o ), + .mst_req_o ( filtered_req ), + .mst_resp_i ( filtered_resp ) + ); + + // 2. AXI bursts -> single-word memory stream, with data-width downsize via banking. + logic [NumBanks-1:0] mem_req, mem_gnt; + axi_addr_t [NumBanks-1:0] mem_addr; + apb_data_t [NumBanks-1:0] mem_wdata; + apb_strb_t [NumBanks-1:0] mem_strb; + logic [NumBanks-1:0] mem_we; + axi_pkg::prot_t [NumBanks-1:0] mem_prot; + logic [NumBanks-1:0] mem_rvalid; + apb_data_t [NumBanks-1:0] mem_rdata; + logic [NumBanks-1:0] mem_err; + logic [NumBanks-1:0] mem_exokay; + + axi_to_detailed_mem #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .AddrWidth ( AxiAddrWidth ), + .DataWidth ( AxiDataWidth ), + .IdWidth ( AxiIdWidth ), + .UserWidth ( AxiUserWidth ), + .NumBanks ( NumBanks ), + .BufDepth ( BufDepth ), + .HideStrb ( 1'b1 ), // drop zero-strobe write lanes so they issue no APB access + .OutFifoDepth ( OutFifoDepth ) + ) i_axi_to_detailed_mem ( + .clk_i, + .rst_ni, + .busy_o ( /* unused */ ), + .axi_req_i ( filtered_req ), + .axi_resp_o ( filtered_resp ), + .mem_req_o ( mem_req ), + .mem_gnt_i ( mem_gnt ), + .mem_addr_o ( mem_addr ), + .mem_wdata_o ( mem_wdata ), + .mem_strb_o ( mem_strb ), + .mem_atop_o ( /* unused */ ), + .mem_lock_o ( /* unused */ ), + .mem_we_o ( mem_we ), + .mem_id_o ( /* unused */ ), + .mem_user_o ( /* unused */ ), + .mem_cache_o ( /* unused */ ), + .mem_prot_o ( mem_prot ), + .mem_qos_o ( /* unused */ ), + .mem_region_o ( /* unused */ ), + .mem_rvalid_i ( mem_rvalid ), + .mem_rdata_i ( mem_rdata ), + .mem_err_i ( mem_err ), + .mem_exokay_i ( mem_exokay ) + ); + + // 3. Inline APB master: serialize the active bank requests onto the single APB bus. + apb_state_e apb_state_q, apb_state_d; + logic [BankIdxWidth-1:0] bank_sel, bank_sel_q, bank_sel_d; + logic no_req; + logic dec_err_q, dec_err_d; + + // Select the lowest-index lane that still has a pending request. Lanes with no request - + // including zero-strobe write lanes dropped by `axi_to_detailed_mem` (`HideStrb`) - are skipped + // for free (no wasted cycles). + cc_lzc #( + .Width ( NumBanks ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) // count trailing zeros -> lowest set bit + ) i_bank_sel ( + .in_i ( mem_req ), + .cnt_o ( bank_sel ), + .empty_o ( no_req ) + ); + + // Address decode on the selected lane's (full-width) address. With no rules (`NoRules == 0`) the + // decoder is bypassed: the lone APB slave is always selected and every address is a hit. + logic apb_dec_valid; + sel_idx_t apb_sel_idx, apb_sel_idx_q, apb_sel_idx_d; + if (UseAddrDecode) begin : gen_addr_decode + cc_addr_decode #( + .NoIndices ( NoApbSlaves ), + .NoRules ( NoRules ), + .addr_t ( axi_addr_t ), + .rule_t ( rule_t ) + ) i_apb_decode ( + .addr_i ( mem_addr[bank_sel] ), + .addr_map_i ( addr_map_i ), + .idx_o ( apb_sel_idx ), + .dec_valid_o ( apb_dec_valid ), + .dec_error_o ( /* unused */ ), + .en_default_idx_i ( 1'b0 ), + .default_idx_i ( '0 ) + ); + end else begin : gen_no_decode + assign apb_sel_idx = '0; // only slave 0 exists + assign apb_dec_valid = 1'b1; // every transaction is a hit + end + + always_comb begin + // Default assignments. + apb_state_d = apb_state_q; + bank_sel_d = bank_sel_q; + apb_sel_idx_d = apb_sel_idx_q; + dec_err_d = dec_err_q; + apb_req_o = '0; + mem_gnt = '0; + mem_rvalid = '0; + mem_rdata = '0; + mem_err = '0; + mem_exokay = '0; + + unique case (apb_state_q) + Setup: begin + if (!no_req) begin + bank_sel_d = bank_sel; + apb_sel_idx_d = apb_sel_idx; + dec_err_d = !apb_dec_valid; + apb_state_d = Access; + if (apb_dec_valid) begin + // SETUP phase: assert psel, keep penable low. + apb_req_o[apb_sel_idx] = '{ + paddr: apb_addr_t'(mem_addr[bank_sel]), + pprot: mem_prot[bank_sel], + psel: 1'b1, + penable: 1'b0, + pwrite: mem_we[bank_sel], + pwdata: mem_wdata[bank_sel], + pstrb: mem_strb[bank_sel] + }; + end + end + end + Access: begin + if (dec_err_q) begin + // Decode miss: no APB request, answer this lane with a slave error and move on. + mem_gnt[bank_sel_q] = 1'b1; + mem_rvalid[bank_sel_q] = 1'b1; + mem_err[bank_sel_q] = 1'b1; + apb_state_d = Setup; + end else begin + // ACCESS phase: assert psel and penable until the slave is ready. + apb_req_o[apb_sel_idx_q] = '{ + paddr: apb_addr_t'(mem_addr[bank_sel_q]), + pprot: mem_prot[bank_sel_q], + psel: 1'b1, + penable: 1'b1, + pwrite: mem_we[bank_sel_q], + pwdata: mem_wdata[bank_sel_q], + pstrb: mem_strb[bank_sel_q] + }; + if (apb_resp_i[apb_sel_idx_q].pready) begin + mem_gnt[bank_sel_q] = 1'b1; + mem_rvalid[bank_sel_q] = 1'b1; + mem_rdata[bank_sel_q] = apb_resp_i[apb_sel_idx_q].prdata; + mem_err[bank_sel_q] = apb_resp_i[apb_sel_idx_q].pslverr; + mem_exokay[bank_sel_q] = 1'b0; // APB has no exclusive access + apb_state_d = Setup; + end + end + end + default: /* do nothing */ ; + endcase + end + + `FF(apb_state_q, apb_state_d, Setup, clk_i, rst_ni) + `FF(bank_sel_q, bank_sel_d, '0, clk_i, rst_ni) + `FF(apb_sel_idx_q, apb_sel_idx_d, '0, clk_i, rst_ni) + `FF(dec_err_q, dec_err_d, 1'b0, clk_i, rst_ni) + + // parameter check + // pragma translate_off + `ifndef VERILATOR + initial begin : check_params + apb_data_le: assert (ApbDataWidth <= AxiDataWidth) else + $fatal(1, $sformatf("ApbDataWidth has to be <= AxiDataWidth")); + apb_addr_le: assert (ApbAddrWidth <= AxiAddrWidth) else + $fatal(1, $sformatf("ApbAddrWidth has to be <= AxiAddrWidth")); + apb_data_div: assert (AxiDataWidth % ApbDataWidth == 0) else + $fatal(1, $sformatf("AxiDataWidth has to be an integer multiple of ApbDataWidth")); + apb_no_decode: assert (UseAddrDecode || NoApbSlaves == 32'd1) else + $fatal(1, $sformatf("NoRules == 0 (no address decoder) is only allowed with a single APB slave")); + end + `endif + // pragma translate_on +endmodule + +module axi_to_apb_intf #( + /// Number of connected APB slaves. + parameter int unsigned NoApbSlaves = 32'd1, + /// Number of APB address-decode rules. Set to `0` to omit the address decoder (see `axi_to_apb`); + /// only legal with `NoApbSlaves == 1`, in which case `addr_map_i` may be left unconnected. + parameter int unsigned NoRules = 32'd1, + /// AXI4 address width. Decoding uses the full width; `paddr` is truncated to `ApbAddrWidth`. + parameter int unsigned AxiAddrWidth = 32'd0, + /// AXI4 data width. Must be an integer power-of-two multiple of `ApbDataWidth`. + parameter int unsigned AxiDataWidth = 32'd0, + /// AXI4 ID width. + parameter int unsigned AxiIdWidth = 32'd0, + /// AXI4 user width. + parameter int unsigned AxiUserWidth = 32'd0, + /// Maximum number of outstanding writes tracked by the `axi_atop_filter`. + parameter int unsigned AxiMaxWriteTxns = 32'd1, + /// Response buffer depth of the internal `axi_to_detailed_mem`. + parameter int unsigned BufDepth = 32'd1, + /// Output FIFO depth of the internal `axi_to_detailed_mem`. + parameter int unsigned OutFifoDepth = 32'd1, + /// APB4 address width. Must be `<= AxiAddrWidth`; the upper AXI address bits are discarded. + parameter int unsigned ApbAddrWidth = 32'd0, + /// APB4 data width. Must be a multiple of 8 and `<= 32` (`ApbDataWidth == 8` is supported). + parameter int unsigned ApbDataWidth = 32'd0, + /// Address-decode rule struct from `common_cells` (`addr_decode`). + parameter type rule_t = logic, + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter type apb_addr_t = logic [ApbAddrWidth-1:0], + parameter type apb_data_t = logic [ApbDataWidth-1:0], + parameter type apb_strb_t = logic [ApbDataWidth/8-1:0], + parameter type sel_t = logic [NoApbSlaves-1:0] +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // AXI4+ATOP slave port + AXI_BUS.Slave slv, + // APB master port + output apb_addr_t paddr_o, + output logic [2:0] pprot_o, + output sel_t pselx_o, + output logic penable_o, + output logic pwrite_o, + output apb_data_t pwdata_o, + output apb_strb_t pstrb_o, + input logic [NoApbSlaves-1:0] pready_i, + input apb_data_t [NoApbSlaves-1:0] prdata_i, + input [NoApbSlaves-1:0] pslverr_i, + // APB slave address map (unused when `NoRules == 0`; port width kept at >=1 to stay well-formed) + input rule_t [((NoRules > 0) ? NoRules : 1)-1:0] addr_map_i +); + localparam int unsigned SelIdxWidth = NoApbSlaves > 1 ? $clog2(NoApbSlaves) : 1; + + typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [AxiDataWidth-1:0] axi_data_t; + typedef logic [AxiIdWidth-1:0] axi_id_t; + typedef logic [AxiDataWidth/8-1:0] axi_strb_t; + typedef logic [AxiUserWidth-1:0] axi_user_t; + + typedef struct packed { + apb_addr_t paddr; + axi_pkg::prot_t pprot; + logic psel; + logic penable; + logic pwrite; + apb_data_t pwdata; + apb_strb_t pstrb; + } apb_req_t; + + typedef struct packed { + logic pready; + apb_data_t prdata; + logic pslverr; + } apb_resp_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, axi_addr_t, axi_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, axi_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, axi_addr_t, axi_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, axi_data_t, axi_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + + axi_req_t axi_req; + axi_resp_t axi_resp; + apb_req_t [NoApbSlaves-1:0] apb_req; + apb_resp_t [NoApbSlaves-1:0] apb_resp; + logic [SelIdxWidth-1:0] apb_sel; + + `AXI_ASSIGN_TO_REQ(axi_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, axi_resp) + + cc_onehot_to_bin #( + .OnehotWidth ( NoApbSlaves ) + ) i_onehot_to_bin ( + .onehot_i ( pselx_o ), + .bin_o ( apb_sel ) + ); + + assign paddr_o = apb_req[apb_sel].paddr; + assign pprot_o = apb_req[apb_sel].pprot; + assign penable_o = apb_req[apb_sel].penable; + assign pwrite_o = apb_req[apb_sel].pwrite; + assign pwdata_o = apb_req[apb_sel].pwdata; + assign pstrb_o = apb_req[apb_sel].pstrb; + for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_resp_assign + assign pselx_o[i] = apb_req[i].psel; + assign apb_resp[i].pready = pready_i[i]; + assign apb_resp[i].prdata = prdata_i[i]; + assign apb_resp[i].pslverr = pslverr_i[i]; + end + + axi_to_apb #( + .NoApbSlaves ( NoApbSlaves ), + .NoRules ( NoRules ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .AxiMaxWriteTxns ( AxiMaxWriteTxns ), + .BufDepth ( BufDepth ), + .OutFifoDepth ( OutFifoDepth ), + .ApbAddrWidth ( ApbAddrWidth ), + .ApbDataWidth ( ApbDataWidth ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .apb_req_t ( apb_req_t ), + .apb_resp_t ( apb_resp_t ), + .rule_t ( rule_t ) + ) i_axi_to_apb ( + .clk_i, + .rst_ni, + .axi_req_i ( axi_req ), + .axi_resp_o ( axi_resp ), + .apb_req_o ( apb_req ), + .apb_resp_i ( apb_resp ), + .addr_map_i + ); +endmodule diff --git a/src/axi_to_axi_lite.sv b/src/axi_to_axi_lite.sv index ad2e41414..c42120484 100644 --- a/src/axi_to_axi_lite.sv +++ b/src/axi_to_axi_lite.sv @@ -31,7 +31,6 @@ module axi_to_axi_lite #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave port full AXI4+ATOP input full_req_t slv_req_i, output full_resp_t slv_resp_o, @@ -91,7 +90,6 @@ module axi_to_axi_lite #( ) i_axi_to_axi_lite_id_reflect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_i ( test_i ), .slv_req_i ( splitted_req ), .slv_resp_o ( splitted_resp ), .mst_req_o ( mst_req_o ), @@ -127,7 +125,6 @@ module axi_to_axi_lite_id_reflect #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave port full AXI input full_req_t slv_req_i, output full_resp_t slv_resp_o, @@ -165,15 +162,15 @@ module axi_to_axi_lite_id_reflect #( // Write ID reflection assign aw_push = mst_req_o.aw_valid & slv_resp_o.aw_ready; assign aw_pop = slv_resp_o.b_valid & mst_req_o.b_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( AxiMaxWriteTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( AxiMaxWriteTxns ), + .data_t ( id_t ) ) i_aw_id_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( aw_full ), .empty_o ( aw_empty ), .usage_o ( /*not used*/ ), @@ -186,15 +183,15 @@ module axi_to_axi_lite_id_reflect #( // Read ID reflection assign ar_push = mst_req_o.ar_valid & slv_resp_o.ar_ready; assign ar_pop = slv_resp_o.r_valid & mst_req_o.r_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( AxiMaxReadTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( AxiMaxReadTxns ), + .data_t ( id_t ) ) i_ar_id_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( ar_full ), .empty_o ( ar_empty ), .usage_o ( /*not used*/ ), @@ -262,7 +259,6 @@ module axi_to_axi_lite_intf #( ) ( input logic clk_i, input logic rst_ni, - input logic testmode_i, AXI_BUS.Slave slv, AXI_LITE.Master mst ); @@ -315,7 +311,6 @@ module axi_to_axi_lite_intf #( ) i_axi_to_axi_lite ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_i ( testmode_i ), // slave port full AXI4+ATOP .slv_req_i ( full_req ), .slv_resp_o ( full_resp ), diff --git a/src/axi_to_detailed_mem.sv b/src/axi_to_detailed_mem.sv index 376a48f07..16a64cec9 100644 --- a/src/axi_to_detailed_mem.sv +++ b/src/axi_to_detailed_mem.sv @@ -264,9 +264,9 @@ module axi_to_detailed_mem #( end // Arbitrate between reads and writes. - stream_mux #( - .DATA_T ( meta_t ), - .N_INP ( 32'd2 ) + cc_stream_mux #( + .data_t ( meta_t ), + .NumInp ( 32'd2 ) ) i_ax_mux ( .inp_data_i ({wr_meta, rd_meta }), .inp_valid_i ({wr_valid, rd_valid}), @@ -321,11 +321,12 @@ module axi_to_detailed_mem #( end // Fork arbitrated stream to meta data, memory requests, and R/B channel selection. - stream_fork #( - .N_OUP ( 32'd3 ) + cc_stream_fork #( + .NumOup ( 32'd3 ) ) i_fork ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( arb_valid ), .ready_o ( arb_ready ), .valid_o ({sel_valid, meta_valid, m2s_req_valid}), @@ -335,15 +336,15 @@ module axi_to_detailed_mem #( assign sel_b = meta.write & meta.last; assign sel_r = ~meta.write | meta.atop[5]; - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( 32'd1 + BufDepth ), - .T ( logic[1:0] ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( 32'd1 + BufDepth ), + .data_t ( logic[1:0] ) ) i_sel_buf ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ({sel_b, sel_r }), .valid_i ( sel_valid ), .ready_o ( sel_ready ), @@ -353,15 +354,15 @@ module axi_to_detailed_mem #( .usage_o ( /* unused */ ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( 32'd1 + BufDepth ), - .T ( meta_t ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( 32'd1 + BufDepth ), + .data_t ( meta_t ) ) i_meta_buf ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( meta ), .valid_i ( meta_valid ), .ready_o ( meta_ready ), @@ -470,8 +471,8 @@ module axi_to_detailed_mem #( // Join memory read data and meta data stream. logic mem_join_valid, mem_join_ready; - stream_join #( - .N_INP ( 32'd2 ) + cc_stream_join #( + .NumInp ( 32'd2 ) ) i_join ( .inp_valid_i ({m2s_resp_valid, meta_buf_valid}), .inp_ready_o ({m2s_resp_ready, meta_buf_ready}), @@ -480,11 +481,12 @@ module axi_to_detailed_mem #( ); // Dynamically fork the joined stream to B and R channels. - stream_fork_dynamic #( - .N_OUP ( 32'd2 ) + cc_stream_fork_dynamic #( + .NumOup ( 32'd2 ) ) i_fork_dynamic ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( mem_join_valid ), .ready_o ( mem_join_ready ), .sel_i ({sel_buf_b, sel_buf_r }), @@ -555,19 +557,19 @@ module axi_to_detailed_mem #( }; // Registers - `FFARN(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni) - `FFARN(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni) - `FFARN(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FFARN(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FFARN(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni) - `FFARN(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni) - `FFARN(collect_b_err_q, collect_b_err_d, '0, clk_i, rst_ni) - `FFARN(collect_b_exokay_q, collect_b_exokay_d, 1'b1, clk_i, rst_ni) + `FF(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni) + `FF(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni) + `FF(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni) + `FF(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni) + `FF(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni) + `FF(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni) + `FF(collect_b_err_q, collect_b_err_d, '0, clk_i, rst_ni) + `FF(collect_b_exokay_q, collect_b_exokay_d, 1'b1, clk_i, rst_ni) // Assertions // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assume property (@(posedge clk_i) axi_req_i.ar_valid && !axi_resp_o.ar_ready |=> $stable(axi_req_i.ar)) @@ -864,7 +866,7 @@ module mem_stream_to_banks_detailed #( assign mem_req_valid = req_i & cnt_req_ready; // Register - `FFARN(cnt_q, cnt_d, '0, clk_i, rst_ni) + `FF(cnt_q, cnt_d, '0, clk_i, rst_ni) end // Handle requests. @@ -875,16 +877,16 @@ module mem_stream_to_banks_detailed #( assign bank_req[i].strb = strb_i[i*BytesPerBank+:BytesPerBank]; assign bank_req[i].wuser = wuser_i; assign bank_req[i].we = we_i; - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DATA_WIDTH ( $bits(req_t) ), - .DEPTH ( OutFifoDepth ), - .T ( req_t ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .DataWidth ( $bits(req_t) ), + .Depth ( OutFifoDepth ), + .data_t ( req_t ) ) i_ft_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .usage_o (), .data_i ( bank_req[i] ), .valid_i ( req_valid ), @@ -921,15 +923,15 @@ module mem_stream_to_banks_detailed #( for (genvar i = 0; unsigned'(i) < NumBanks; i++) begin assign zero_strobe_on_input[i] = (strb_i[i*BytesPerBank+:BytesPerBank] == '0); end - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MaxTrans+1 ), - .DATA_WIDTH ( NumBanks ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MaxTrans+1 ), + .DataWidth ( NumBanks ) ) i_dead_write_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( dead_write_fifo_full ), .empty_o ( dead_write_fifo_empty ), .usage_o ( ), @@ -948,15 +950,15 @@ module mem_stream_to_banks_detailed #( // Handle responses. for (genvar i = 0; unsigned'(i) < NumBanks; i++) begin : gen_resp_regs - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DATA_WIDTH ( $bits(oup_data_t) + $bits(oup_ruser_t) ), - .DEPTH ( MaxTrans ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .DataWidth ( $bits(oup_data_t) + $bits(oup_ruser_t) ), + .Depth ( MaxTrans ) ) i_ft_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .usage_o (), .data_i ( {bank_rdata_i[i], bank_ruser_i[i]} ), .valid_i ( bank_rvalid_i[i] ), diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv index 548339f37..5a8db0a40 100644 --- a/src/axi_to_mem_banked.sv +++ b/src/axi_to_mem_banked.sv @@ -69,7 +69,6 @@ module axi_to_mem_banked #( /// Asynchronous reset, active low input logic rst_ni, /// Testmode enable - input logic test_i, /// AXI4+ATOP slave port, request struct input axi_req_t axi_req_i, /// AXI4+ATOP slave port, response struct @@ -101,7 +100,7 @@ module axi_to_mem_banked #( localparam int unsigned BankSelOffset = $clog2(MemDataWidth / 32'd8); /// Selection signal width of the xbar. This is the reason for power of two banks, otherwise /// There are holes in the address mapping. - localparam int unsigned BankSelWidth = cf_math_pkg::idx_width(MemNumBanks); + localparam int unsigned BankSelWidth = cc_pkg::idx_width(MemNumBanks); typedef logic [BankSelWidth-1:0] xbar_sel_t; // Typedef for defining the channels @@ -159,7 +158,6 @@ module axi_to_mem_banked #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( axi_req_i ), .slv_aw_select_i ( WriteAccess ), .slv_ar_select_i ( ReadAccess ), @@ -240,12 +238,13 @@ module axi_to_mem_banked #( assign res_rdata[j] = mem_rdata_i[r_shift_oup.sel]; // Connect for the response data `MemLatency` cycles after a request was made to the xbar. - shift_reg #( - .dtype ( read_sel_t ), - .Depth ( MemLatency ) + cc_shift_register #( + .data_t ( read_sel_t ), + .Depth ( MemLatency ) ) i_shift_reg_rdata_mux ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .d_i ( r_shift_inp ), .d_o ( r_shift_oup ) ); @@ -255,7 +254,7 @@ module axi_to_mem_banked #( // Xbar to arbitrate data over the different memory banks xbar_payload_t [MemNumBanks-1:0] mem_payload; - stream_xbar #( + cc_stream_xbar #( .NumInp ( 32'd2 * BanksPerAxiChannel ), .NumOut ( MemNumBanks ), .payload_t ( xbar_payload_t ), @@ -266,7 +265,8 @@ module axi_to_mem_banked #( ) i_stream_xbar ( .clk_i, .rst_ni, - .flush_i ( 1'b0 ), + .clr_arb_i ( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .data_i ( inter_payload ), .sel_i ( inter_sel ), @@ -306,6 +306,7 @@ module axi_to_mem_banked #( // pragma translate_on endmodule + `include "axi/typedef.svh" `include "axi/assign.svh" /// AXI4+ATOP interface wrapper for `axi_to_mem` @@ -346,7 +347,6 @@ module axi_to_mem_banked_intf #( /// Asynchronous reset, active low input logic rst_ni, /// Testmode enable - input logic test_i, /// AXI4+ATOP slave port AXI_BUS.Slave slv, /// Memory bank request @@ -407,7 +407,6 @@ module axi_to_mem_banked_intf #( ) i_axi_to_mem_banked ( .clk_i, .rst_ni, - .test_i, .axi_to_mem_busy_o, .axi_req_i ( mem_axi_req ), .axi_resp_o ( mem_axi_resp ), @@ -432,4 +431,3 @@ module axi_to_mem_banked_intf #( `endif // pragma translate_on endmodule - diff --git a/src/axi_to_mem_interleaved.sv b/src/axi_to_mem_interleaved.sv index 94d2bbef0..b2cef75e9 100644 --- a/src/axi_to_mem_interleaved.sv +++ b/src/axi_to_mem_interleaved.sv @@ -48,7 +48,6 @@ module axi_to_mem_interleaved #( /// Asynchronous reset, active low. input logic rst_ni, /// Testmode enable - input logic test_i, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, /// AXI4+ATOP slave port, request input. @@ -113,7 +112,6 @@ module axi_to_mem_interleaved #( ) i_split_read_write ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( axi_req_i ), .slv_ar_select_i ( 1'b0 ), .slv_aw_select_i ( 1'b1 ), @@ -221,13 +219,13 @@ module axi_to_mem_interleaved #( assign r_axi_to_mem_gnt[i] = r_mem_gnt[i] & ~fifo_full[i]; // fine-grain arbitration - rr_arb_tree #( - .NumIn ( 2 ), - .DataType ( mem_req_payload_t ) + cc_rr_arb_tree #( + .NumIn ( 2 ), + .data_t ( mem_req_payload_t ) ) i_rr_arb_tree ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i ( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( { r_mem_req[i], w_mem_req[i] } ), .gnt_o ( { r_mem_gnt[i], w_mem_gnt[i] } ), @@ -239,14 +237,14 @@ module axi_to_mem_interleaved #( ); // back-routing store - fifo_v3 #( - .DATA_WIDTH ( 1 ), - .DEPTH ( BufDepth + 1 ) + cc_fifo #( + .DataWidth ( 1 ), + .Depth ( BufDepth + 1 ) ) i_fifo_v3_response_trgt_store ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( fifo_full[i] ), .empty_o ( ), .usage_o ( ), @@ -294,7 +292,6 @@ module axi_to_mem_interleaved_intf #( /// Asynchronous reset, active low input logic rst_ni, /// Testmode enable - input logic test_i, /// Status output, busy flag of `axi_to_mem` output logic busy_o, /// AXI4+ATOP slave port @@ -350,7 +347,6 @@ module axi_to_mem_interleaved_intf #( ) i_axi_to_mem_interleaved ( .clk_i, .rst_ni, - .test_i, .busy_o, .axi_req_i ( mem_axi_req ), .axi_resp_o ( mem_axi_resp ), diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv index 3e98bda2e..df52d3c2a 100644 --- a/src/axi_to_mem_split.sv +++ b/src/axi_to_mem_split.sv @@ -51,7 +51,6 @@ module axi_to_mem_split #( /// Asynchronous reset, active low. input logic rst_ni, /// Testmode enable - input logic test_i, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, /// AXI4+ATOP slave port, request input. @@ -97,7 +96,6 @@ module axi_to_mem_split #( ) i_split_read_write ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( axi_req_i ), .slv_ar_select_i ( 1'b0 ), .slv_aw_select_i ( 1'b1 ), @@ -197,7 +195,6 @@ module axi_to_mem_split_intf #( /// Asynchronous reset, active low. input logic rst_ni, /// Testmode enable - input logic test_i, /// See `axi_to_mem_split`, port `busy_o`. output logic busy_o, /// AXI4+ATOP slave interface port. @@ -246,7 +243,6 @@ module axi_to_mem_split_intf #( ) i_axi_to_mem_split ( .clk_i, .rst_ni, - .test_i, .busy_o, .axi_req_i (axi_req), .axi_resp_o (axi_resp), diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index 5baa854ba..e541392bd 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -16,7 +16,7 @@ /// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. /// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. module axi_xbar -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( /// Configuration struct for the crossbar see `axi_pkg` for fields and definitions. parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -68,8 +68,6 @@ import cf_math_pkg::idx_width; input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, - /// Testmode enable, active high. - input logic test_i, /// AXI4+ATOP requests to the slave ports. input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, /// AXI4+ATOP responses of the slave ports. @@ -109,7 +107,6 @@ import cf_math_pkg::idx_width; ) i_xbar_unmuxed ( .clk_i, .rst_ni, - .test_i, .slv_ports_req_i, .slv_ports_resp_o, .mst_ports_req_o (mst_reqs), @@ -146,7 +143,6 @@ import cf_math_pkg::idx_width; ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable .slv_reqs_i ( mst_reqs[i] ), .slv_resps_o ( mst_resps[i] ), .mst_req_o ( mst_ports_req_o[i] ), @@ -160,7 +156,7 @@ endmodule `include "axi/typedef.svh" module axi_xbar_intf -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter int unsigned AXI_USER_WIDTH = 0, parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -172,7 +168,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, @@ -239,7 +234,6 @@ import cf_math_pkg::idx_width; ) i_xbar ( .clk_i, .rst_ni, - .test_i, .slv_ports_req_i (slv_reqs ), .slv_ports_resp_o (slv_resps), .mst_ports_req_o (mst_reqs ), diff --git a/src/axi_xbar_unmuxed.sv b/src/axi_xbar_unmuxed.sv index 73e50975c..ef73bbb25 100644 --- a/src/axi_xbar_unmuxed.sv +++ b/src/axi_xbar_unmuxed.sv @@ -16,7 +16,7 @@ /// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. /// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. module axi_xbar_unmuxed -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( /// Configuration struct for the crossbar see `axi_pkg` for fields and definitions. parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -56,8 +56,6 @@ import cf_math_pkg::idx_width; input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, - /// Testmode enable, active high. - input logic test_i, /// AXI4+ATOP requests to the slave ports. input req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, /// AXI4+ATOP responses of the slave ports. @@ -98,7 +96,7 @@ import cf_math_pkg::idx_width; logic dec_aw_valid, dec_aw_error; logic dec_ar_valid, dec_ar_error; - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .NoRules ( Cfg.NoAddrRules ), .addr_t ( addr_t ), @@ -113,7 +111,7 @@ import cf_math_pkg::idx_width; .default_idx_i ( default_mst_port_i[i] ) ); - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NoAddrRules ), @@ -136,7 +134,7 @@ import cf_math_pkg::idx_width; // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -183,7 +181,6 @@ import cf_math_pkg::idx_width; ) i_axi_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable .slv_req_i ( slv_ports_req_i[i] ), .slv_aw_select_i ( slv_aw_select ), .slv_ar_select_i ( slv_ar_select ), @@ -204,7 +201,6 @@ import cf_math_pkg::idx_width; ) i_axi_err_slv ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable // slave port .slv_req_i ( slv_reqs[i][Cfg.NoMstPorts] ), .slv_resp_o ( slv_resps[i][cfg_NoMstPorts] ) @@ -245,7 +241,6 @@ import cf_math_pkg::idx_width; ) i_axi_err_slv ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( slv_reqs[i][j] ), .slv_resp_o ( slv_resps[i][j] ) ); @@ -255,7 +250,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin : check_params id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); @@ -266,89 +261,3 @@ import cf_math_pkg::idx_width; `endif // pragma translate_on endmodule - -`ifndef VCS -`ifndef TARGET_GENUS -// As of now, VCS and Genus does not support multi-dimensional array of interfaces. -`include "axi/assign.svh" -`include "axi/typedef.svh" - -module axi_xbar_unmuxed_intf -import cf_math_pkg::idx_width; -#( - parameter int unsigned AXI_USER_WIDTH = 0, - parameter axi_pkg::xbar_cfg_t Cfg = '0, - parameter bit ATOPS = 1'b1, - parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1, - parameter type rule_t = axi_pkg::xbar_rule_64_t -) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], - AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0], - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i -); - - typedef logic [Cfg.AxiIdWidthSlvPorts -1:0] id_t; - typedef logic [Cfg.AxiAddrWidth -1:0] addr_t; - typedef logic [Cfg.AxiDataWidth -1:0] data_t; - typedef logic [Cfg.AxiDataWidth/8 -1:0] strb_t; - typedef logic [AXI_USER_WIDTH -1:0] user_t; - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) - - req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; - req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - resp_t [Cfg.NoSlvPorts-1:0] slv_resps; - - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst - for (genvar j = 0; j < Cfg.NoSlvPorts; j++) begin : gen_assign_mst_inner - `AXI_ASSIGN_FROM_REQ(mst_ports[i][j], mst_reqs[i][j]) - `AXI_ASSIGN_TO_RESP(mst_resps[i][j], mst_ports[i][j]) - end - end - - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv - `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) - `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) - end - - axi_xbar_unmuxed #( - .Cfg ( Cfg ), - .ATOPs ( ATOPS ), - .Connectivity ( CONNECTIVITY ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ), - .rule_t ( rule_t ) - ) i_xbar ( - .clk_i, - .rst_ni, - .test_i, - .slv_ports_req_i (slv_reqs ), - .slv_ports_resp_o (slv_resps), - .mst_ports_req_o (mst_reqs ), - .mst_ports_resp_i (mst_resps), - .addr_map_i, - .en_default_mst_port_i, - .default_mst_port_i - ); - -endmodule - -`endif -`endif diff --git a/src/axi_xp.sv b/src/axi_xp.sv index 5ccbfb9ff..b0af8c4b0 100644 --- a/src/axi_xp.sv +++ b/src/axi_xp.sv @@ -84,8 +84,6 @@ module axi_xp #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Test mode enable - input logic test_en_i, /// Slave ports request input axi_req_t [NumSlvPorts-1:0] slv_req_i, /// Slave ports response @@ -135,7 +133,6 @@ module axi_xp #( ) i_xbar ( .clk_i, .rst_ni, - .test_i ( test_en_i ), .slv_ports_req_i ( slv_req_i ), .slv_ports_resp_o ( slv_resp_o ), .mst_ports_req_o ( xbar_req ), @@ -171,7 +168,7 @@ endmodule `include "axi/typedef.svh" module axi_xp_intf -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter bit ATOPs = 1'b1, parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -192,7 +189,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_en_i, AXI_BUS.Slave slv_ports [NumSlvPorts-1:0], AXI_BUS.Master mst_ports [NumMstPorts-1:0], input rule_t [NumAddrRules-1:0] addr_map_i @@ -245,7 +241,6 @@ import cf_math_pkg::idx_width; ) i_xp ( .clk_i, .rst_ni, - .test_en_i, .slv_req_i (slv_reqs ), .slv_resp_o (slv_resps), .mst_req_o (mst_reqs ), diff --git a/src_files.yml b/src_files.yml index 31575309e..5ee92a759 100644 --- a/src_files.yml +++ b/src_files.yml @@ -67,6 +67,7 @@ axi: - src/axi_interleaved_xbar.sv - src/axi_iw_converter.sv - src/axi_lite_xbar.sv + - src/axi_to_apb.sv - src/axi_xbar_unmuxed.sv - src/axi_to_mem_banked.sv - src/axi_to_mem_interleaved.sv diff --git a/test/axi_synth_bench.sv b/test/axi_synth_bench.sv index 334846abc..fcf15f447 100644 --- a/test/axi_synth_bench.sv +++ b/test/axi_synth_bench.sv @@ -90,6 +90,19 @@ module axi_synth_bench ( end end + // AXI4+ATOP to APB bridge (with data-width downsize and address truncation). + // `ApbDataWidth` is swept over {8, 16, 32} (banking-based downsizing supports 8-bit APB). + for (genvar i_data = 0; i_data < 3; i_data++) begin + localparam int unsigned ApbDataWidth = (2**i_data) * 8; + for (genvar i_slv = 0; i_slv < 3; i_slv++) begin + synth_axi_to_apb #( + .NoApbSlaves ( NUM_SLAVE_MASTER[i_slv] ), + .AxiDataWidth ( 32'd64 ), + .ApbDataWidth ( ApbDataWidth ) + ) i_axi_to_apb (.*); + end + end + // AXI4-Lite Mailbox for (genvar i_irq_mode = 0; i_irq_mode < 4; i_irq_mode++) begin localparam bit EDGE_TRIG = i_irq_mode[0]; @@ -241,7 +254,6 @@ module synth_slice #( ) a ( .clk_i (clk_i), .rst_ni (rst_ni), - .testmode_i (1'b0), .slv (a_full.Slave), .mst (a_lite.Master) ); @@ -360,6 +372,93 @@ module synth_axi_lite_to_apb #( endmodule +module synth_axi_to_apb #( + parameter int unsigned NoApbSlaves = 0, + parameter int unsigned AxiDataWidth = 0, + parameter int unsigned ApbDataWidth = 0 +) ( + input logic clk_i, // Clock + input logic rst_ni // Asynchronous reset active low +); + + localparam int unsigned AxiAddrWidth = 32'd48; + localparam int unsigned ApbAddrWidth = 32'd32; + localparam int unsigned AxiIdWidth = 32'd4; + localparam int unsigned AxiUserWidth = 32'd1; + + typedef logic [ApbAddrWidth-1:0] apb_addr_t; + typedef logic [ApbDataWidth-1:0] apb_data_t; + typedef logic [ApbDataWidth/8-1:0] apb_strb_t; + + typedef struct packed { + apb_addr_t paddr; + axi_pkg::prot_t pprot; + logic psel; + logic penable; + logic pwrite; + apb_data_t pwdata; + apb_strb_t pstrb; + } apb_req_t; + + typedef struct packed { + logic pready; + apb_data_t prdata; + logic pslverr; + } apb_resp_t; + + typedef logic [AxiAddrWidth-1:0] addr_t; + typedef logic [AxiDataWidth-1:0] data_t; + typedef logic [AxiIdWidth-1:0] id_t; + typedef logic [AxiDataWidth/8-1:0] strb_t; + typedef logic [AxiUserWidth-1:0] user_t; + + typedef struct packed { + int unsigned idx; + addr_t start_addr; + addr_t end_addr; + } rule_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + + axi_req_t axi_req; + axi_resp_t axi_resp; + apb_req_t [NoApbSlaves-1:0] apb_req; + apb_resp_t [NoApbSlaves-1:0] apb_resp; + + rule_t [NoApbSlaves-1:0] addr_map; + + axi_to_apb #( + .NoApbSlaves ( NoApbSlaves ), + .NoRules ( NoApbSlaves ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .ApbAddrWidth ( ApbAddrWidth ), + .ApbDataWidth ( ApbDataWidth ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .apb_req_t ( apb_req_t ), + .apb_resp_t ( apb_resp_t ), + .rule_t ( rule_t ) + ) i_axi_to_apb_dut ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .axi_req_i ( axi_req ), + .axi_resp_o ( axi_resp ), + .apb_req_o ( apb_req ), + .apb_resp_i ( apb_resp ), + .addr_map_i ( addr_map ) + ); + +endmodule + module synth_axi_cdc #( parameter int unsigned AXI_ADDR_WIDTH = 0, parameter int unsigned AXI_DATA_WIDTH = 0, @@ -434,7 +533,6 @@ module synth_axi_lite_xbar #( }; axi_pkg::xbar_rule_32_t [NoSlvMst-1:0] addr_map; - logic test; axi_req_t [NoSlvMst-1:0] mst_reqs, slv_reqs; axi_resp_t [NoSlvMst-1:0] mst_resps, slv_resps; @@ -451,7 +549,6 @@ module synth_axi_lite_xbar #( ) i_xbar_dut ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_i ( test ), .slv_ports_req_i ( mst_reqs ), .slv_ports_resp_o ( mst_resps ), .mst_ports_req_o ( slv_reqs ), @@ -477,7 +574,6 @@ module synth_axi_lite_mailbox #( .AXI_DATA_WIDTH (32'd32) ) slv [1:0] (); - logic test; logic [1:0] irq; addr_t [1:0] base_addr; @@ -490,7 +586,6 @@ module synth_axi_lite_mailbox #( ) i_axi_lite_mailbox ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low - .test_i ( test ), // Testmode enable // slave ports [1:0] .slv ( slv ), .irq_o ( irq ), // interrupt output for each port @@ -720,7 +815,6 @@ module synth_axi_to_mem_banked #( ) axi (); // Misc signals - logic test; logic [1:0] axi_to_mem_busy; // Signals for mem macros logic [BankNum-1:0] mem_req; @@ -745,7 +839,6 @@ module synth_axi_to_mem_banked #( ) i_axi_to_mem_banked_intf ( .clk_i, .rst_ni, - .test_i ( test ), .slv ( axi ), .mem_req_o ( mem_req ), .mem_gnt_i ( mem_gnt ), diff --git a/test/tb_axi_bus_compare.sv b/test/tb_axi_bus_compare.sv index c8cd1c91c..9283ae408 100644 --- a/test/tb_axi_bus_compare.sv +++ b/test/tb_axi_bus_compare.sv @@ -79,27 +79,30 @@ module tb_axi_bus_compare #( logic w_ready; logic ar_ready; - stream_fork #(.N_OUP(32'd2)) i_stream_fork_aw ( + cc_stream_fork #(.NumOup(32'd2)) i_stream_fork_aw ( .clk_i ( clk ), .rst_ni ( rst_n ), + .clr_i ( 1'b0 ), .valid_i ( axi_req.aw_valid ), .ready_o ( aw_ready ), .valid_o ( { aw_valid_a, aw_valid_b } ), .ready_i ( { aw_ready_a, aw_ready_b } ) ); - stream_fork #(.N_OUP(32'd2)) i_stream_fork_ar ( + cc_stream_fork #(.NumOup(32'd2)) i_stream_fork_ar ( .clk_i ( clk ), .rst_ni ( rst_n ), + .clr_i ( 1'b0 ), .valid_i ( axi_req.ar_valid ), .ready_o ( ar_ready ), .valid_o ( { ar_valid_a, ar_valid_b } ), .ready_i ( { ar_ready_a, ar_ready_b } ) ); - stream_fork #(.N_OUP(32'd2)) i_stream_fork_w ( + cc_stream_fork #(.NumOup(32'd2)) i_stream_fork_w ( .clk_i ( clk ), .rst_ni ( rst_n ), + .clr_i ( 1'b0 ), .valid_i ( axi_req.w_valid ), .ready_o ( w_ready ), .valid_o ( { w_valid_a, w_valid_b } ), @@ -149,7 +152,6 @@ module tb_axi_bus_compare #( ) i_axi_bus_compare ( .clk_i ( clk ), .rst_ni ( rst_n ), - .testmode_i ( 1'b0 ), .axi_a_req_i ( axi_req_a_in ), .axi_a_rsp_o ( axi_rsp_a_in ), .axi_a_req_o ( axi_req_a_out ), @@ -257,7 +259,7 @@ module tb_axi_bus_compare #( drv.reset_master(); wait (rst_n); // AW -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(aw_beat); assert (rand_success); @@ -272,7 +274,7 @@ module tb_axi_bus_compare #( drv.send_aw(aw_beat); // W beats for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); diff --git a/test/tb_axi_delayer.sv b/test/tb_axi_delayer.sv index 5b9c15dc4..186a10334 100644 --- a/test/tb_axi_delayer.sv +++ b/test/tb_axi_delayer.sv @@ -83,7 +83,7 @@ module tb_axi_delayer; @(posedge clk); repeat (200) begin @(posedge clk); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(ax_beat) may behave differently to ax_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(ax_beat); assert(rand_success); diff --git a/test/tb_axi_fifo.sv b/test/tb_axi_fifo.sv index 2e79044e0..b962fa952 100644 --- a/test/tb_axi_fifo.sv +++ b/test/tb_axi_fifo.sv @@ -111,7 +111,6 @@ module tb_axi_fifo #( ) i_dut ( .clk_i (clk), // clock .rst_ni(rst_n), // asynchronous reset active low - .test_i(1'b0), .slv (master), // slave port .mst (slave) // master port ); diff --git a/test/tb_axi_fifo.wave.do b/test/tb_axi_fifo.wave.do index bdf1d9e20..5e0fdf5a6 100644 --- a/test/tb_axi_fifo.wave.do +++ b/test/tb_axi_fifo.wave.do @@ -98,7 +98,6 @@ add wave -noupdate -divider Custom add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/clk_i add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/rst_ni add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/flush_i -add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/testmode_i add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/full_o add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/empty_o add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/usage_o @@ -109,7 +108,6 @@ add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_ax add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/clk_i add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/rst_ni add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/flush_i -add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/testmode_i add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/full_o add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/empty_o add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/usage_o @@ -120,7 +118,6 @@ add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/clk_i add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/rst_ni add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/flush_i -add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/testmode_i add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/full_o add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/empty_o add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/usage_o @@ -131,7 +128,6 @@ add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/clk_i add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/rst_ni add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/flush_i -add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/testmode_i add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/full_o add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/empty_o add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/usage_o @@ -142,7 +138,6 @@ add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_ax add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/clk_i add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/rst_ni add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/flush_i -add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/testmode_i add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/full_o add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/empty_o add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/usage_o diff --git a/test/tb_axi_lite_mailbox.sv b/test/tb_axi_lite_mailbox.sv index 255702922..14fab56fe 100644 --- a/test/tb_axi_lite_mailbox.sv +++ b/test/tb_axi_lite_mailbox.sv @@ -456,7 +456,6 @@ module tb_axi_lite_mailbox; ) i_mailbox_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .slv ( master ), .irq_o ( irq ), .base_addr_i ( '0 ) // set base address to '0 diff --git a/test/tb_axi_lite_mailbox.wave.do b/test/tb_axi_lite_mailbox.wave.do index c272b4fa2..3e1572ba3 100644 --- a/test/tb_axi_lite_mailbox.wave.do +++ b/test/tb_axi_lite_mailbox.wave.do @@ -3,7 +3,6 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/clk_i add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/rst_ni -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/test_i add wave -noupdate -divider Ports add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/slv_reqs_i add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/slv_resps_o diff --git a/test/tb_axi_lite_xbar.sv b/test/tb_axi_lite_xbar.sv index 54697344a..d4d460af1 100644 --- a/test/tb_axi_lite_xbar.sv +++ b/test/tb_axi_lite_xbar.sv @@ -175,7 +175,6 @@ module tb_axi_lite_xbar; ) i_xbar_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .slv_ports ( master ), .mst_ports ( slave ), .addr_map_i ( AddrMap ), diff --git a/test/tb_axi_lite_xbar.wave.do b/test/tb_axi_lite_xbar.wave.do index 604e70c80..1eb256870 100644 --- a/test/tb_axi_lite_xbar.wave.do +++ b/test/tb_axi_lite_xbar.wave.do @@ -3,7 +3,6 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_lite_xbar/i_xbar_dut/clk_i add wave -noupdate -label Reset /tb_axi_lite_xbar/i_xbar_dut/rst_ni -add wave -noupdate -label {Test Mode} /tb_axi_lite_xbar/i_xbar_dut/test_i add wave -noupdate -divider {Slave Ports} add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/slv_ports_req_i add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/slv_ports_resp_o diff --git a/test/tb_axi_sim_mem.sv b/test/tb_axi_sim_mem.sv index 76ddb03f8..018923ebe 100644 --- a/test/tb_axi_sim_mem.sv +++ b/test/tb_axi_sim_mem.sv @@ -100,7 +100,7 @@ module tb_axi_sim_mem #( wait (rst_n); // AW forever begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(aw_beat); assert (rand_success); @@ -121,7 +121,7 @@ module tb_axi_sim_mem #( drv.send_aw(aw_beat); // W beats for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); diff --git a/test/tb_axi_slave_compare.sv b/test/tb_axi_slave_compare.sv index 2fa47bdc7..407a63af4 100644 --- a/test/tb_axi_slave_compare.sv +++ b/test/tb_axi_slave_compare.sv @@ -82,7 +82,6 @@ module tb_axi_slave_compare #( ) i_axi_bus_compare ( .clk_i ( clk ), .rst_ni ( rst_n ), - .testmode_i ( 1'b0 ), .axi_mst_req_i ( axi_req ), .axi_mst_rsp_o ( axi_rsp ), .axi_ref_req_o ( axi_req_a_out ), @@ -188,7 +187,7 @@ module tb_axi_slave_compare #( drv.reset_master(); wait (rst_n); // AW -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(aw_beat); assert (rand_success); @@ -203,7 +202,7 @@ module tb_axi_slave_compare #( drv.send_aw(aw_beat); // W beats for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); diff --git a/test/tb_axi_to_apb.sv b/test/tb_axi_to_apb.sv new file mode 100644 index 000000000..4bc934ae1 --- /dev/null +++ b/test/tb_axi_to_apb.sv @@ -0,0 +1,404 @@ +// Copyright (c) 2024 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Tim Fischer + +// Description: Testbench for `axi_to_apb`. +// +// A full-AXI random master drives the DUT, whose APB master ports are attached to four behavioural +// APB slaves with different timing: an ideal (0-wait), a slow (fixed-wait), a random-wait, and an +// error slave. The first three are memory-backed, so `DUT + memory slaves` behaves as an AXI memory +// and an `axi_scoreboard` on the AXI port checks end-to-end data integrity (address mapping, bank +// placement, strobe masking, burst handling). The random master only targets the three memory +// slaves; the error slave and an unmapped address are exercised by a few directed transactions that +// check the error / decode-miss responses. APB-protocol legality is checked with assertions. + +`include "axi/typedef.svh" +`include "axi/assign.svh" + +module tb_axi_to_apb #( + // Swept externally over {32, 64} to cover NumBanks = 1 and 2 (with ApbDataWidth = 32). + parameter int unsigned TbAxiDataWidth = 32'd64 +); + + // Timing + localparam time CyclTime = 10ns; + localparam time ApplTime = 2ns; + localparam time TestTime = 8ns; + + // Random master transaction counts + localparam int unsigned NoWrites = 2000; + localparam int unsigned NoReads = 2000; + + // Widths. Keep AxiAddrWidth == ApbAddrWidth so the decode (full AXI address) and the APB memories + // (truncated `paddr`) stay consistent for the scoreboard, i.e. no truncation aliasing. + localparam int unsigned AxiAddrWidth = 32'd32; + localparam int unsigned ApbAddrWidth = 32'd32; + localparam int unsigned ApbDataWidth = 32'd32; + localparam int unsigned AxiIdWidth = 32'd4; + localparam int unsigned AxiUserWidth = 32'd2; + localparam int unsigned AxiStrbWidth = TbAxiDataWidth/8; + + localparam int unsigned NoApbSlaves = 32'd4; + localparam int unsigned NoRules = NoApbSlaves; + + // APB slave indices / behaviour + typedef enum int unsigned { + IdealSlv = 0, + SlowSlv = 1, + RandSlv = 2, + ErrSlv = 3 + } apb_slv_e; + + typedef axi_pkg::xbar_rule_32_t rule_t; // {idx, start_addr, end_addr}, 32-bit address + + // One 4 KiB page per slave; 4 KiB alignment guarantees a burst never crosses a slave boundary. + localparam rule_t [NoRules-1:0] AddrMap = '{ + '{idx: 32'd3, start_addr: 32'h0000_3000, end_addr: 32'h0000_4000}, // error + '{idx: 32'd2, start_addr: 32'h0000_2000, end_addr: 32'h0000_3000}, // random + '{idx: 32'd1, start_addr: 32'h0000_1000, end_addr: 32'h0000_2000}, // slow + '{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_1000} // ideal + }; + localparam logic [AxiAddrWidth-1:0] MemLo = 32'h0000_0000; // ideal+slow+random span + localparam logic [AxiAddrWidth-1:0] MemHi = 32'h0000_3000; + localparam logic [AxiAddrWidth-1:0] ErrAddr = 32'h0000_3040; // inside error slave + localparam logic [AxiAddrWidth-1:0] DecAddr = 32'h0000_8000; // unmapped + + // APB request/response structs (as expected by `axi_to_apb`) + typedef logic [ApbAddrWidth-1:0] apb_addr_t; + typedef logic [ApbDataWidth-1:0] apb_data_t; + typedef logic [ApbDataWidth/8-1:0] apb_strb_t; + + typedef struct packed { + apb_addr_t paddr; + axi_pkg::prot_t pprot; + logic psel; + logic penable; + logic pwrite; + apb_data_t pwdata; + apb_strb_t pstrb; + } apb_req_t; + + typedef struct packed { + logic pready; + apb_data_t prdata; + logic pslverr; + } apb_resp_t; + + // Full AXI types + typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [TbAxiDataWidth-1:0] axi_data_t; + typedef logic [AxiIdWidth-1:0] axi_id_t; + typedef logic [AxiStrbWidth-1:0] axi_strb_t; + typedef logic [AxiUserWidth-1:0] axi_user_t; + + `AXI_TYPEDEF_ALL(axi, axi_addr_t, axi_id_t, axi_data_t, axi_strb_t, axi_user_t) + + // ----------------------------------------------------------------------------------------------- + // Clock / reset + // ----------------------------------------------------------------------------------------------- + logic clk, rst_n; + logic end_of_sim; + + clk_rst_gen #( + .ClkPeriod ( CyclTime ), + .RstClkCycles ( 5 ) + ) i_clk_gen ( + .clk_o ( clk ), + .rst_no ( rst_n ) + ); + + // ----------------------------------------------------------------------------------------------- + // AXI master interface + driver + scoreboard monitor + // ----------------------------------------------------------------------------------------------- + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) master_dv (clk); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) master (); + `AXI_ASSIGN(master, master_dv) + + axi_req_t axi_req; + axi_resp_t axi_resp; + `AXI_ASSIGN_TO_REQ(axi_req, master) + `AXI_ASSIGN_FROM_RESP(master, axi_resp) + + apb_req_t [NoApbSlaves-1:0] apb_req; + apb_resp_t [NoApbSlaves-1:0] apb_resp; + + typedef axi_test::axi_rand_master #( + .AW ( AxiAddrWidth ), .DW ( TbAxiDataWidth ), .IW ( AxiIdWidth ), .UW ( AxiUserWidth ), + .TA ( ApplTime ), .TT ( TestTime ), + .MAX_READ_TXNS ( 4 ), .MAX_WRITE_TXNS ( 4 ), + .AXI_MAX_BURST_LEN ( 16 ), + // INCR only (`axi_to_detailed_mem` restriction); no atomics/exclusives. + .AXI_BURST_FIXED ( 1'b0 ), .AXI_BURST_INCR ( 1'b1 ), .AXI_BURST_WRAP ( 1'b0 ), + .AXI_ATOPS ( 1'b0 ), .AXI_EXCLS ( 1'b0 ), + // Master-side backpressure. + .AX_MIN_WAIT_CYCLES ( 0 ), .AX_MAX_WAIT_CYCLES ( 5 ), + .W_MIN_WAIT_CYCLES ( 0 ), .W_MAX_WAIT_CYCLES ( 3 ), + .RESP_MIN_WAIT_CYCLES ( 0 ), .RESP_MAX_WAIT_CYCLES ( 8 ) + ) axi_rand_master_t; + + typedef axi_test::axi_driver #( + .AW ( AxiAddrWidth ), .DW ( TbAxiDataWidth ), .IW ( AxiIdWidth ), .UW ( AxiUserWidth ), + .TA ( ApplTime ), .TT ( TestTime ) + ) axi_drv_t; + + axi_rand_master_t axi_rand_master = new (master_dv); + + // Directed single-beat write, checks the B response. + task automatic directed_write(input axi_addr_t addr, input axi_pkg::resp_t exp); + automatic axi_drv_t::ax_beat_t ax = new; + automatic axi_drv_t::w_beat_t w = new; + automatic axi_drv_t::b_beat_t b; + ax.ax_addr = addr; + ax.ax_id = '0; + ax.ax_len = '0; + ax.ax_size = axi_pkg::size_t'($clog2(AxiStrbWidth)); + ax.ax_burst = axi_pkg::BURST_INCR; + w.w_data = {(TbAxiDataWidth/32){32'hC0FF_EE00}}; + w.w_strb = '1; + w.w_last = 1'b1; + fork + axi_rand_master.drv.send_aw(ax); + axi_rand_master.drv.send_w(w); + join + axi_rand_master.drv.recv_b(b); + assert (b.b_resp == exp) else + $error("directed_write @%0h: expected B resp %0d, got %0d", addr, exp, b.b_resp); + endtask + + // Directed single-beat read, checks the R response. + task automatic directed_read(input axi_addr_t addr, input axi_pkg::resp_t exp); + automatic axi_drv_t::ax_beat_t ax = new; + automatic axi_drv_t::r_beat_t r; + ax.ax_addr = addr; + ax.ax_id = '0; + ax.ax_len = '0; + ax.ax_size = axi_pkg::size_t'($clog2(AxiStrbWidth)); + ax.ax_burst = axi_pkg::BURST_INCR; + axi_rand_master.drv.send_ar(ax); + axi_rand_master.drv.recv_r(r); + assert (r.r_resp == exp) else + $error("directed_read @%0h: expected R resp %0d, got %0d", addr, exp, r.r_resp); + endtask + + initial begin : proc_stimuli + end_of_sim <= 1'b0; + axi_rand_master.reset(); + // Random traffic only hits the three memory slaves. + axi_rand_master.add_memory_region(MemLo, MemHi, axi_pkg::WTHRU_NOALLOCATE); + @(posedge rst_n); + repeat (5) @(posedge clk); + + // Directed error / decode-miss checks (this DUT answers both with SLVERR). + directed_write(ErrAddr, axi_pkg::RESP_SLVERR); // error slave + directed_read (ErrAddr, axi_pkg::RESP_SLVERR); + directed_write(DecAddr, axi_pkg::RESP_SLVERR); // unmapped address + directed_read (DecAddr, axi_pkg::RESP_SLVERR); + + // Randomized data-integrity + backpressure run. + axi_rand_master.run(NoReads, NoWrites); + + end_of_sim <= 1'b1; + repeat (20) @(posedge clk); + $display("[tb_axi_to_apb] finished (AxiDataWidth=%0d, NumBanks=%0d).", + TbAxiDataWidth, TbAxiDataWidth/ApbDataWidth); + $stop(); + end + + // Watchdog: fail instead of hanging on a deadlock. + initial begin : proc_watchdog + repeat (32'd5_000_000) @(posedge clk); + if (!end_of_sim) $fatal(1, "[tb_axi_to_apb] timeout - possible deadlock."); + end + + // ----------------------------------------------------------------------------------------------- + // Scoreboard (end-to-end data integrity on the AXI side) + // ----------------------------------------------------------------------------------------------- + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) monitor_dv (clk); + `AXI_ASSIGN_MONITOR(monitor_dv, master) + + typedef axi_test::axi_scoreboard #( + .IW ( AxiIdWidth ), .AW ( AxiAddrWidth ), .DW ( TbAxiDataWidth ), + .UW ( AxiUserWidth ), .TT ( TestTime ) + ) axi_scoreboard_t; + axi_scoreboard_t axi_scoreboard = new(monitor_dv); + initial begin : proc_scoreboard + axi_scoreboard.enable_all_checks(); + @(posedge rst_n); + axi_scoreboard.monitor(); + end + + // ----------------------------------------------------------------------------------------------- + // DUT + // ----------------------------------------------------------------------------------------------- + axi_to_apb #( + .NoApbSlaves ( NoApbSlaves ), + .NoRules ( NoRules ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( TbAxiDataWidth ), + .AxiIdWidth ( AxiIdWidth ), + .AxiUserWidth ( AxiUserWidth ), + .ApbAddrWidth ( ApbAddrWidth ), + .ApbDataWidth ( ApbDataWidth ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .apb_req_t ( apb_req_t ), + .apb_resp_t ( apb_resp_t ), + .rule_t ( rule_t ) + ) i_dut ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( axi_req ), + .axi_resp_o ( axi_resp ), + .apb_req_o ( apb_req ), + .apb_resp_i ( apb_resp ), + .addr_map_i ( AddrMap ) + ); + + // ----------------------------------------------------------------------------------------------- + // APB slaves: ideal, slow, random (memory-backed) and error. + // ----------------------------------------------------------------------------------------------- + for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_slv + localparam bit IsErr = (i == ErrSlv); + localparam bit IsRand = (i == RandSlv); + localparam int unsigned FixedWait = (i == SlowSlv) ? 4 : 0; + tb_apb_mem_slave #( + .AddrWidth ( ApbAddrWidth ), + .DataWidth ( ApbDataWidth ), + .FixedWait ( FixedWait ), + .Random ( IsRand ), + .Error ( IsErr ), + .apb_req_t ( apb_req_t ), + .apb_resp_t ( apb_resp_t ) + ) i_apb_slv ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .apb_req_i ( apb_req[i] ), + .apb_resp_o ( apb_resp[i] ) + ); + end + + // ----------------------------------------------------------------------------------------------- + // APB protocol assertions (per slave) + // ----------------------------------------------------------------------------------------------- + // pragma translate_off + `ifndef VERILATOR + default disable iff (!rst_n); + for (genvar i = 0; i < NoApbSlaves; i++) begin : gen_apb_assertions + sequence APB_SETUP; apb_req[i].psel && !apb_req[i].penable; endsequence + sequence APB_ACCESS; apb_req[i].psel && apb_req[i].penable; endsequence + sequence APB_TRANSFER; APB_SETUP ##1 APB_ACCESS; endsequence + + apb_complete: assert property ( @(posedge clk) (APB_SETUP |-> APB_TRANSFER)); + apb_penable: assert property ( @(posedge clk) + (apb_req[i].penable && apb_req[i].psel && apb_resp[i].pready |=> (!apb_req[i].penable))); + control_stable: assert property ( @(posedge clk) + (APB_TRANSFER |-> $stable({apb_req[i].pwrite, apb_req[i].paddr}))); + write_stable: assert property ( @(posedge clk) + ((apb_req[i].penable && apb_req[i].pwrite) |-> $stable(apb_req[i].pwdata))); + strb_stable: assert property ( @(posedge clk) + ((apb_req[i].penable && apb_req[i].pwrite) |-> $stable(apb_req[i].pstrb))); + end + `endif + // pragma translate_on + +endmodule + +// ------------------------------------------------------------------------------------------------- +// Behavioural APB slave. +// - `Error` : always answers with `pslverr`, stores nothing (0-wait). +// - `Random` : asserts `pready` on a random cycle during the access phase. +// - else : asserts `pready` after `FixedWait` access cycles (0 = ideal). +// Memory-backed (except the error slave): stores `pwdata` under `pstrb`, returns it on reads. +// ------------------------------------------------------------------------------------------------- +module tb_apb_mem_slave #( + parameter int unsigned AddrWidth = 32, + parameter int unsigned DataWidth = 32, + parameter int unsigned FixedWait = 0, + parameter bit Random = 1'b0, + parameter bit Error = 1'b0, + parameter type apb_req_t = logic, + parameter type apb_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input apb_req_t apb_req_i, + output apb_resp_t apb_resp_o +); + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + + data_t mem [addr_t]; // word-addressed by `paddr` + logic in_access; + logic pready; + int unsigned wait_cnt; + logic rand_bit; + data_t rd_data; + + assign in_access = apb_req_i.psel & apb_req_i.penable; + + // Wait-state counter: counts access cycles until the transfer completes. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + wait_cnt <= 0; + rand_bit <= 1'b0; + end else begin + rand_bit <= $urandom_range(0, 1); + wait_cnt <= (in_access && !pready) ? wait_cnt + 1 : 0; + end + end + + always_comb begin + pready = 1'b0; + if (in_access) begin + if (Error) pready = 1'b1; // error slave completes immediately + else if (Random) pready = rand_bit; + else pready = (wait_cnt >= FixedWait); + end + end + + always_comb begin + rd_data = '0; + if (!Error && apb_req_i.psel && mem.exists(apb_req_i.paddr)) rd_data = mem[apb_req_i.paddr]; + end + + assign apb_resp_o.pready = pready; + assign apb_resp_o.prdata = rd_data; + assign apb_resp_o.pslverr = Error; + + // Commit writes (byte-strobed) on the completing access cycle. + always_ff @(posedge clk_i) begin + if (in_access && pready && apb_req_i.pwrite && !Error) begin + automatic data_t cur = mem.exists(apb_req_i.paddr) ? mem[apb_req_i.paddr] : '0; + for (int b = 0; b < DataWidth/8; b++) begin + if (apb_req_i.pstrb[b]) cur[8*b +: 8] = apb_req_i.pwdata[8*b +: 8]; + end + mem[apb_req_i.paddr] = cur; + end + end + +endmodule diff --git a/test/tb_axi_to_axi_lite.sv b/test/tb_axi_to_axi_lite.sv index 39589af19..09d41f0f1 100644 --- a/test/tb_axi_to_axi_lite.sv +++ b/test/tb_axi_to_axi_lite.sv @@ -74,7 +74,6 @@ module tb_axi_to_axi_lite; ) i_dut ( .clk_i ( clk ), .rst_ni ( rst ), - .testmode_i ( 1'b0 ), .slv ( axi ), .mst ( axi_lite ) ); diff --git a/test/tb_axi_to_mem_banked.sv b/test/tb_axi_to_mem_banked.sv index 64667998d..c5b31daaa 100644 --- a/test/tb_axi_to_mem_banked.sv +++ b/test/tb_axi_to_mem_banked.sv @@ -165,7 +165,7 @@ module tb_axi_to_mem_banked #( assign mem_rvalid[i] = mem_req[i]; end else begin : gen_mem_lat logic [TbMemLatency-1:0] mem_lat_q, mem_lat_d; - `FFARN(mem_lat_q, mem_lat_d, '0, clk, rst_n) + `FF(mem_lat_q, mem_lat_d, '0, clk, rst_n) assign mem_lat_d[TbMemLatency-1] = mem_req[i]; if (TbMemLatency > 1) begin for (genvar lat_i = 0; lat_i < TbMemLatency - 1; lat_i++) begin @@ -198,7 +198,6 @@ module tb_axi_to_mem_banked #( ) i_axi_to_mem_banked_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .axi_to_mem_busy_o ( dut_busy ), .slv ( mem_axi ), .mem_req_o ( mem_req ), diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index bb54e69a8..3f8b3ffba 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -316,7 +316,6 @@ module tb_axi_xbar #( ) i_xbar_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .slv_ports ( master ), .mst_ports ( slave ), .addr_map_i ( AddrMap ), diff --git a/test/tb_axi_xbar.wave.do b/test/tb_axi_xbar.wave.do index 23a9095a2..1f19f390c 100644 --- a/test/tb_axi_xbar.wave.do +++ b/test/tb_axi_xbar.wave.do @@ -3,7 +3,6 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_xbar/i_xbar_dut/clk_i add wave -noupdate -label Reset /tb_axi_xbar/i_xbar_dut/rst_ni -add wave -noupdate -label {Test Mode} /tb_axi_xbar/i_xbar_dut/test_i add wave -noupdate -divider {Slave Ports} add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_ports_req_i add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_ports_resp_o