diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml index b0fd13261..43bff9759 100644 --- a/.github/workflows/gitlab-ci.yml +++ b/.github/workflows/gitlab-ci.yml @@ -9,7 +9,7 @@ on: jobs: gitlab-ci: runs-on: ubuntu-latest - timeout-minutes: 310 + timeout-minutes: 360 steps: - name: Check Gitlab CI uses: pulp-platform/pulp-actions/gitlab-ci@v2.5.1 diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 146819335..e5e524a0a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -256,3 +256,20 @@ axi_xbar: - src/axi_mux.sv - src/axi_multicut.sv - src/axi_xbar_unmuxed.sv + timeout: 6h 00m + +axi_mcast_xbar: + extends: .run_vsim + variables: + TEST_MODULE: axi_mcast_xbar + rules: + - *run_vsim_common_change_rule + - *run_vsim_module_change_rule + - changes: + compare_to: 'refs/heads/master' + paths: + - src/axi_mcast_demux.sv + - src/axi_err_slv.sv + - src/axi_mcast_mux.sv + - src/axi_multicut.sv + timeout: 6h 00m diff --git a/Bender.lock b/Bender.lock index da9205fe2..ac28e3059 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,7 +1,7 @@ packages: common_cells: - revision: 9ca8a7655f741e7dd5736669a20a301325194c28 - version: 1.39.0 + revision: 03d98106aa19952a10360d2230def85144a0008b + version: null source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -14,8 +14,8 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] tech_cells_generic: - revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf - version: 0.2.13 + revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845 + version: 0.2.14 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: diff --git a/Bender.yml b/Bender.yml index 7105eca20..896b8f393 100644 --- a/Bender.yml +++ b/Bender.yml @@ -6,6 +6,7 @@ package: - "Niccolo Giuliani " # current maintainer - "Thomas Benz " - "Matheus Cavalcante " + - "Luca Colagrande " - "Tim Fischer " - "Noah Huetter " - "Cyril Koenig " @@ -20,10 +21,13 @@ package: - "Nils Wistoff " - "Florian Zaruba " +remotes: + pulp: https://github.com/pulp-platform + dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.39.0 } - common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.5 } - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: v2.0.0-beta.2 } + common_verification: 0.2.5 + tech_cells_generic: 0.2.14 export_include_dirs: - include @@ -39,22 +43,16 @@ sources: - src/axi_intf.sv # Level 2 - src/axi_atop_filter.sv - - src/axi_burst_splitter_gran.sv - - src/axi_burst_unwrap.sv - src/axi_bus_compare.sv - src/axi_cdc_dst.sv - src/axi_cdc_src.sv - src/axi_cut.sv - src/axi_delayer.sv - - src/axi_demux_simple.sv - - src/axi_dw_downsizer.sv - - src/axi_dw_upsizer.sv - src/axi_fifo.sv - src/axi_fifo_delay_dyn.sv - src/axi_id_remap.sv - src/axi_id_prepend.sv - src/axi_inval_filter.sv - - src/axi_isolate.sv - src/axi_join.sv - src/axi_lite_demux.sv - src/axi_lite_dw_converter.sv @@ -66,8 +64,9 @@ sources: - src/axi_lite_regs.sv - src/axi_lite_to_apb.sv - src/axi_lite_to_axi.sv + - src/axi_mcast_demux_simple.sv + - src/axi_mcast_mux.sv - src/axi_modify_address.sv - - src/axi_mux.sv - src/axi_rw_join.sv - src/axi_rw_split.sv - src/axi_serializer.sv @@ -75,29 +74,40 @@ sources: - src/axi_throttle.sv - src/axi_to_detailed_mem.sv # Level 3 - - src/axi_burst_splitter.sv - src/axi_cdc.sv - - src/axi_demux.sv + - src/axi_demux_simple.sv - src/axi_err_slv.sv - - src/axi_dw_converter.sv - src/axi_from_mem.sv - - src/axi_id_serialize.sv - - src/axi_lfsr.sv + - src/axi_mcast_demux_mapped.sv - src/axi_multicut.sv - - src/axi_to_axi_lite.sv + - src/axi_mux.sv - src/axi_to_mem.sv - src/axi_zero_mem.sv # Level 4 - - src/axi_interleaved_xbar.sv - - src/axi_iw_converter.sv + - src/axi_burst_splitter_gran.sv + - src/axi_demux.sv - src/axi_lite_xbar.sv - - src/axi_xbar_unmuxed.sv - - src/axi_to_mem_banked.sv + - src/axi_mcast_xbar_unmuxed.sv - src/axi_to_mem_interleaved.sv - src/axi_to_mem_split.sv # Level 5 - - src/axi_xbar.sv + - src/axi_burst_splitter.sv + - src/axi_burst_unwrap.sv + - src/axi_dw_downsizer.sv + - src/axi_dw_upsizer.sv + - src/axi_id_serialize.sv + - src/axi_interleaved_xbar.sv + - src/axi_isolate.sv + - src/axi_mcast_xbar.sv + - src/axi_to_mem_banked.sv + - src/axi_xbar_unmuxed.sv # Level 6 + - src/axi_dw_converter.sv + - src/axi_iw_converter.sv + - src/axi_to_axi_lite.sv + - src/axi_xbar.sv + # Level 7 + - src/axi_lfsr.sv - src/axi_xp.sv - target: synth_test @@ -133,6 +143,7 @@ sources: - test/tb_axi_lite_to_apb.sv - test/tb_axi_lite_to_axi.sv - test/tb_axi_lite_xbar.sv + - test/tb_axi_mcast_xbar.sv - test/tb_axi_modify_address.sv - test/tb_axi_serializer.sv - test/tb_axi_sim_mem.sv diff --git a/README.md b/README.md index 8408d861f..b46dd2749 100644 --- a/README.md +++ b/README.md @@ -143,3 +143,4 @@ All code in each release and on the default branch is tested on a recent version [doc.axi_id_serialize]: https://pulp-platform.github.io/axi/master/module.axi_id_serialize [doc.axi_iw_converter]: https://pulp-platform.github.io/axi/master/module.axi_iw_converter [doc.axi_lite_regs]: https://pulp-platform.github.io/axi/master/module.axi_lite_regs +[doc.axi_lite_dw_converter]: https://pulp-platform.github.io/axi/master/module.axi_lite_dw_converter \ No newline at end of file diff --git a/axi.core b/axi.core index 1c8b25040..5ed06d8dd 100644 --- a/axi.core +++ b/axi.core @@ -84,7 +84,7 @@ filesets: - src/axi_xp.sv file_type : systemVerilogSource depend : - - ">=pulp-platform.org::common_cells:1.31.1" + - ">=pulp-platform.org::common_cells:1.39.0" benchs: files: - test/tb_axi_dw_pkg.sv diff --git a/doc/axi_demux.md b/doc/axi_demux.md index 4b8b964ed..82a83375b 100644 --- a/doc/axi_demux.md +++ b/doc/axi_demux.md @@ -45,7 +45,6 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple |:----------------------------------|:------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. | | `slv_{aw,ar}_select_i` | Index of the master port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | | `mst_*` | Array of master ports of the demultiplexer. The array index of each port is the index of the master port. | @@ -71,7 +70,7 @@ Setting the `UniqueIds` parameter to `1'b1` reduces the area complexity of the d `2 * 2^AxiLookBits` counters track the number of [in-flight](../doc#in-flight) transactions. That is, for each ID in the (potentially) reduced set of IDs of `AxiLookBits` bits, there is one counter for write transactions and one for read transactions. Each counter can count up to (and including) `MaxTrans`, and there is a register that holds the index of the master port to which a counter is assigned. -When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID. If the indexed counter has a value greater than zero and its master port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another master port. The demultiplexer then stalls the AW or AR. In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the master port index of the counter. A counter is decremented upon a handshake a B respectively last R beat at a slave port. +When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID. If the indexed counter has a value greater than zero and its master port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another master port. The demultiplexer then stalls the AW or AR. In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the master port index of the counter. A counter associated with the AW or AR channel is decremented upon a handshake on the slave port respectively on the B channel or on the R channel in correspondence of the last beat. W beats are routed to the master port defined by the value of `slv_aw_select_i` for the corresponding AW. As the order of the W bursts is given by the order of the AWs, the select signals are stored in a FIFO queue. This FIFO is pushed upon a handshake on the AW slave channel and popped upon a handshake of the last W beat of a burst on a W master channel. diff --git a/doc/axi_lite_demux.md b/doc/axi_lite_demux.md index cafbf267a..b08bffc9f 100644 --- a/doc/axi_lite_demux.md +++ b/doc/axi_lite_demux.md @@ -38,7 +38,6 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple |:----------------------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. | | `slv_{aw,ar}_select_i` | Index of the master port to which a write or read, respectively, is demultiplexed. This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). | | `mst_*` | Array of master ports of the demultiplexer. The array index of each port is the index of the master port. | diff --git a/doc/axi_lite_mailbox.md b/doc/axi_lite_mailbox.md index 7d5e2de52..e636e052f 100644 --- a/doc/axi_lite_mailbox.md +++ b/doc/axi_lite_mailbox.md @@ -27,7 +27,6 @@ This table describes the ports of the module. |:---------------|:---------------------------|:-------------------------------------------------------| | `clk_i` | `input logic` | clock | | `rst_ni` | `input logic` | asynchronous reset active low | -| `test_i` | `input logic` | testmode enable | | `slv_reqs_i` | `input req_lite_t [1:0]` | requests of the two AXI4-Lite ports | | `slv_resps_o` | `output resp_lite_t [1:0]` | responses of the two AXI4-Lite ports | | `irq_o` | `output logic [1:0]` | interrupt output for each port | diff --git a/doc/axi_lite_xbar.md b/doc/axi_lite_xbar.md index 047b3966d..af515e32d 100644 --- a/doc/axi_lite_xbar.md +++ b/doc/axi_lite_xbar.md @@ -55,7 +55,6 @@ If two crossbars are connected in both directions, meaning both have one of thei |:------------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_ports_*` | Array of slave ports of the crossbar. The array index of each port is the index of the slave port. This index will be prepended to all requests at one of the master ports. | | `mst_ports_*` | Array of master ports of the crossbar. The array index of each port is the index of the master port. | | `addr_map_i` | Address map of the crossbar (see section *Address Map* above). | diff --git a/doc/axi_mux.md b/doc/axi_mux.md index fc257feb0..0c3641267 100644 --- a/doc/axi_mux.md +++ b/doc/axi_mux.md @@ -4,7 +4,7 @@ The opposite function to the AXI demultiplexer is performed by the AXI Multiplex ![Block-diagram of the AXI 4 Multiplexer Module.](axi_mux.png "Block-diagram of the AXI 4 Multiplexer Module.") -The Multiplexer module is has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which slave port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with: +The Multiplexer module has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which slave port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with: ```systemverilog $clog2(NoSlavePorts) diff --git a/doc/axi_xbar.md b/doc/axi_xbar.md index ca0c12108..98bdb23a7 100644 --- a/doc/axi_xbar.md +++ b/doc/axi_xbar.md @@ -5,7 +5,7 @@ ## Design Overview -`axi_xbar` is a fully-connected crossbar, which means that each master module that is connected to a *slave port* for of the crossbar has direct wires to all slave modules that are connected to the *master ports* of the crossbar. +`axi_xbar` is a fully-connected crossbar, which means that each master module that is connected to a *slave port* of the crossbar has direct wires to all slave modules that are connected to the *master ports* of the crossbar. A block-diagram of the crossbar is shown below: ![Block-diagram showing the design of the full AXI4 Crossbar.](axi_xbar.png "Block-diagram showing the design of the full AXI4 Crossbar.") @@ -49,7 +49,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg | `LatencyMode` | `enum logic [9:0]` | Latency on the individual channels, defined in detail in section *Pipelining and Latency* below. | | `AxiIdWidthSlvPorts` | `int unsigned` | The AXI ID width of the slave ports. | | `AxiIdUsedSlvPorts` | `int unsigned` | The number of slave port ID bits (starting at the least significant) the crossbar uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below). This value has to be less or equal than `AxiIdWidthSlvPorts`. | -| `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar. See the [`axi_demux` documentation](axi_demux#ordering-and-stalls) for details. | +| `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar. See the [`axi_demux` documentation](axi_demux.md#ordering-and-stalls) for details. | | `AxiAddrWidth` | `int unsigned` | The AXI address width. | | `AxiDataWidth` | `int unsigned` | The AXI data width. | | `NoAddrRules` | `int unsigned` | The number of address map rules. | @@ -71,7 +71,6 @@ If two crossbars are connected in both directions, meaning both have one of thei |:------------------------|:------------| | `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | | `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | | `slv_ports_*` | Array of slave ports of the crossbar. The array index of each port is the index of the slave port. This index will be prepended to all requests at one of the master ports. | | `mst_ports_*` | Array of master ports of the crossbar. The array index of each port is the index of the master port. | | `addr_map_i` | Address map of the crossbar (see section *Address Map* above). | diff --git a/ips_list.yml b/ips_list.yml index 81f9ef6b0..8c6cbae5f 100644 --- a/ips_list.yml +++ b/ips_list.yml @@ -1,5 +1,5 @@ common_cells: - commit: v1.39.0 + commit: v2.0.0-beta.2 group: pulp-platform common_verification: @@ -7,5 +7,5 @@ common_verification: group: pulp-platform tech_cells_generic: - commit: v0.2.2 + commit: v0.2.14 group: pulp-platform diff --git a/scripts/axi_intercon_gen.py b/scripts/axi_intercon_gen.py index 9e8e606d5..2880cf965 100644 --- a/scripts/axi_intercon_gen.py +++ b/scripts/axi_intercon_gen.py @@ -150,7 +150,6 @@ def assigns(w, max_idw, masters, slaves): def instance_ports(w, id_width, masters, slaves): ports = [Port('clk_i' , 'clk_i'), Port('rst_ni', 'rst_ni'), - Port('test_i', "1'b0"), Port('slv_ports_req_i' , 'masters_req'), Port('slv_ports_resp_o', 'masters_resp'), Port('mst_ports_req_o' , 'slaves_req'), diff --git a/scripts/compile_vsim.sh b/scripts/compile_vsim.sh index 7109858f9..4244e3a54 100755 --- a/scripts/compile_vsim.sh +++ b/scripts/compile_vsim.sh @@ -18,7 +18,7 @@ set -e [ ! -z "$VSIM" ] || VSIM=vsim -bender script vsim -t test -t rtl \ +bender script vsim -t test -t rtl -t cc_no_deprecated \ --vlog-arg="-svinputport=compat" \ --vlog-arg="-override_timescale 1ns/1ps" \ --vlog-arg="-suppress 2583" \ diff --git a/scripts/run_verilator.sh b/scripts/run_verilator.sh index c6681e6d0..df7c0aeab 100755 --- a/scripts/run_verilator.sh +++ b/scripts/run_verilator.sh @@ -21,7 +21,7 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) [ ! -z "$VERILATOR" ] || VERILATOR="verilator" -bender script verilator -t synthesis -t synth_test > ./verilator.f +bender script verilator -t synthesis -t synth_test -t cc_no_deprecated > ./verilator.f VERILATOR_FLAGS=() VERILATOR_FLAGS+=(-Wno-fatal) diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index aaf8c3f22..beeab0b34 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -219,7 +219,7 @@ exec_test() { MST_ID=5 for DATA_WIDTH in 64 256; do for PIPE in 0 1; do - call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \ + call_vsim tb_axi_xbar -t 1ns \ -gTbNumMasters=$NUM_MST \ -gTbNumSlaves=$NUM_SLV \ -gTbAxiIdWidthMasters=$MST_ID \ @@ -241,6 +241,32 @@ exec_test() { done done ;; + axi_mcast_xbar) + for GEN_ATOP in 0 1; do + for NUM_MST in 1 6; do + for NUM_SLV in 2 9; do + for MST_ID_USE in 3 5; do + MST_ID=5 + for DATA_WIDTH in 64 256; do + for PIPE in 0; do + for UNIQUE_IDS in 0; do + call_vsim tb_axi_mcast_xbar -t 1ns \ + -gTbNumMasters=$NUM_MST \ + -gTbNumMcastSlaves=$NUM_SLV \ + -gTbAxiIdWidthMasters=$MST_ID \ + -gTbAxiIdUsed=$MST_ID_USE \ + -gTbAxiDataWidth=$DATA_WIDTH \ + -gTbPipeline=$PIPE \ + -gTbEnAtop=$GEN_ATOP \ + -gTbUniqueIds=$UNIQUE_IDS + done + done + done + done + done + done + done + ;; *) call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx" ;; diff --git a/scripts/run_yosys_slang.sh b/scripts/run_yosys_slang.sh index 7876812c0..7f41e4027 100755 --- a/scripts/run_yosys_slang.sh +++ b/scripts/run_yosys_slang.sh @@ -18,6 +18,6 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) [ ! -z "$YOSYS" ] || YOSYS="yosys" -bender script flist-plus -t synthesis -t synth_test > ./slang.flist +bender script flist-plus -t synthesis -t synth_test -t cc_no_deprecated > ./slang.flist $YOSYS -m slang -p "read_slang -Werror -f slang.flist --allow-use-before-declare --ignore-unknown-modules --keep-hierarchy --top axi_synth_bench; hierarchy" diff --git a/scripts/synth.sh b/scripts/synth.sh index 70cb86a89..407ff9870 100755 --- a/scripts/synth.sh +++ b/scripts/synth.sh @@ -20,7 +20,7 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) [ ! -z "$SYNOPSYS_DC" ] || SYNOPSYS_DC="synopsys dc_shell -64" echo 'remove_design -all' > ./synth.tcl -bender script synopsys -t synth_test >> ./synth.tcl +bender script synopsys -t synth_test -t tech_cells_generic_exclude_tc_sram -t cc_no_deprecated >> ./synth.tcl echo 'elaborate axi_synth_bench' >> ./synth.tcl cat ./synth.tcl | $SYNOPSYS_DC | tee synth.log 2>&1 diff --git a/src/axi_atop_filter.sv b/src/axi_atop_filter.sv index 55ad491b2..d42549083 100644 --- a/src/axi_atop_filter.sv +++ b/src/axi_atop_filter.sv @@ -345,13 +345,12 @@ module axi_atop_filter #( end end - stream_register #( - .T(r_resp_cmd_t) + cc_stream_register #( + .data_t (r_resp_cmd_t) ) r_resp_cmd ( .clk_i (clk_i), .rst_ni (rst_ni), .clr_i (1'b0), - .testmode_i (1'b0), .valid_i (r_resp_cmd_push_valid), .ready_o (r_resp_cmd_push_ready), .data_i (r_resp_cmd_push), diff --git a/src/axi_burst_splitter_gran.sv b/src/axi_burst_splitter_gran.sv index 2ae847a4d..f58be9f1f 100644 --- a/src/axi_burst_splitter_gran.sv +++ b/src/axi_burst_splitter_gran.sv @@ -92,7 +92,6 @@ module axi_burst_splitter_gran #( ) i_demux_supported_vs_unsupported ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( slv_req ), .slv_aw_select_i ( sel_aw_unsupported ), .slv_ar_select_i ( sel_ar_unsupported ), @@ -148,7 +147,6 @@ module axi_burst_splitter_gran #( ) i_err_slv ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( unsupported_req ), .slv_resp_o ( unsupported_resp ) ); @@ -384,18 +382,18 @@ module axi_burst_splitter_gran #( // -------------------------------------------------- // Flip-Flops // -------------------------------------------------- - `FFARN(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) - `FFARN(b_state_q, b_state_d, BReady, clk_i, rst_ni) - `FFARN(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) - `FFARN(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) - `FFARN(w_len_q, w_len_d, 8'h00, clk_i, rst_ni) - `FFARN(w_len_vld_q, w_len_vld_d, 1'b0, clk_i, rst_ni) + `FF(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) + `FF(b_state_q, b_state_d, BReady, clk_i, rst_ni) + `FF(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) + `FF(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) + `FF(w_len_q, w_len_d, 8'h00, clk_i, rst_ni) + `FF(w_len_vld_q, w_len_vld_d, 1'b0, clk_i, rst_ni) // -------------------------------------------------- // Assumptions and assertions // -------------------------------------------------- `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR // pragma translate_off default disable iff (!rst_ni); // Inputs @@ -572,9 +570,9 @@ module axi_burst_splitter_gran_ax_chan #( end // registers - `FFARN(ax_q, ax_d, '0, clk_i, rst_ni) - `FFARN(state_q, state_d, Idle, clk_i, rst_ni) - `FFARN(num_beats_q, num_beats_d, 9'h000, clk_i, rst_ni) + `FF(ax_q, ax_d, '0, clk_i, rst_ni) + `FF(state_q, state_d, Idle, clk_i, rst_ni) + `FF(num_beats_q, num_beats_d, 9'h000, clk_i, rst_ni) endmodule @@ -621,12 +619,13 @@ module axi_burst_splitter_gran_counters #( assign alloc_pld_in.len = alloc_len_i; if (CutPath) begin : gen_spill - spill_register #( - .T ( alloc_pld_t ), + cc_spill_register #( + .data_t ( alloc_pld_t ), .Bypass ( 1'b0 ) ) i_spill_register_alloc ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( alloc_req_i ), .ready_o ( alloc_gnt_o ), .data_i ( alloc_pld_in ), @@ -647,12 +646,12 @@ module axi_burst_splitter_gran_counters #( cnt_t [MaxTxns-1:0] cnt_oup; cnt_idx_t cnt_free_idx, cnt_r_idx; for (genvar i = 0; i < MaxTxns; i++) begin : gen_cnt - delta_counter #( - .WIDTH ( $bits(cnt_t) ) + cc_delta_counter #( + .Width ( $bits(cnt_t) ) ) i_cnt ( .clk_i, .rst_ni, - .clear_i ( cnt_clr[i] ), + .clr_i ( cnt_clr[i] ), .en_i ( cnt_dec[i] ), .load_i ( cnt_set[i] ), .down_i ( 1'b1 ), @@ -665,9 +664,9 @@ module axi_burst_splitter_gran_counters #( end assign cnt_inp = {1'b0, alloc_pld_out.len} + 1; - lzc #( - .WIDTH ( MaxTxns ), - .MODE ( 1'b0 ) // start counting at index 0 + cc_lzc #( + .Width ( MaxTxns ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc ( .in_i ( cnt_free ), .cnt_o ( cnt_free_idx ), @@ -676,14 +675,15 @@ module axi_burst_splitter_gran_counters #( logic idq_inp_req, idq_inp_gnt, idq_oup_gnt, idq_oup_valid, idq_oup_pop; - id_queue #( - .ID_WIDTH ( $bits(id_t) ), - .CAPACITY ( MaxTxns ), - .FULL_BW ( FullBW ), + cc_id_queue #( + .IdWidth ( $bits(id_t) ), + .Capacity ( MaxTxns ), + .FullBw ( FullBW ), .data_t ( cnt_idx_t ) ) i_idq ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .inp_id_i ( alloc_pld_out.id ), .inp_data_i ( cnt_free_idx ), .inp_req_i ( idq_inp_req ), @@ -731,7 +731,7 @@ module axi_burst_splitter_gran_counters #( end // registers - `FFARN(err_q, err_d, '0, clk_i, rst_ni) + `FF(err_q, err_d, '0, clk_i, rst_ni) `ifndef VERILATOR // pragma translate_off diff --git a/src/axi_burst_unwrap.sv b/src/axi_burst_unwrap.sv index 70f8cc9eb..8ff4d9509 100644 --- a/src/axi_burst_unwrap.sv +++ b/src/axi_burst_unwrap.sv @@ -85,7 +85,6 @@ module axi_burst_unwrap #( ) i_demux_supported_vs_unsupported ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i, .slv_aw_select_i ( sel_aw_unsupported ), .slv_ar_select_i ( sel_ar_unsupported ), @@ -123,7 +122,6 @@ module axi_burst_unwrap #( ) i_err_slv ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( unsupported_req ), .slv_resp_o ( unsupported_resp ) ); @@ -135,11 +133,11 @@ module axi_burst_unwrap #( logic w_cnt_dec, w_cnt_req, w_cnt_gnt; axi_pkg::len_t b_cnt_len, w_cnt_len; axi_burst_unwrap_ax_chan #( - .AwChan ( 1'b1 ), - .chan_t ( aw_chan_t ), + .AwChan ( 1'b1 ), + .chan_t ( aw_chan_t ), .AddrWidth ( AddrWidth ), - .IdWidth ( IdWidth ), - .MaxTxns ( MaxWriteTxns ) + .IdWidth ( IdWidth ), + .MaxTxns ( MaxWriteTxns ) ) i_axi_burst_unwrap_aw_chan ( .clk_i, .rst_ni, @@ -353,18 +351,18 @@ module axi_burst_unwrap #( // -------------------------------------------------- // Flip-Flops // -------------------------------------------------- - `FFARN(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) - `FFARN(b_state_q, b_state_d, BReady, clk_i, rst_ni) - `FFARN(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) - `FFARN(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) - `FFARN(w_last_q, w_last_d, 1'b0, clk_i, rst_ni) - `FFARN(w_state_q, w_state_d, WReady, clk_i, rst_ni) + `FF(b_err_q, b_err_d, 1'b0, clk_i, rst_ni) + `FF(b_state_q, b_state_d, BReady, clk_i, rst_ni) + `FF(r_last_q, r_last_d, 1'b0, clk_i, rst_ni) + `FF(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni) + `FF(w_last_q, w_last_d, 1'b0, clk_i, rst_ni) + `FF(w_state_q, w_state_d, WReady, clk_i, rst_ni) // -------------------------------------------------- // Assumptions and assertions // -------------------------------------------------- `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR // pragma translate_off default disable iff (!rst_ni); // Inputs @@ -533,8 +531,8 @@ module axi_burst_unwrap_ax_chan #( end // registers - `FFARN(ax_q, ax_d, '0, clk_i, rst_ni) - `FFARN(state_q, state_d, Idle, clk_i, rst_ni) + `FF(ax_q, ax_d, '0, clk_i, rst_ni) + `FF(state_q, state_d, Idle, clk_i, rst_ni) endmodule /// Internal module of [`axi_burst_splitter`](module.axi_burst_splitter) to order transactions. @@ -567,12 +565,12 @@ module axi_burst_counters #( cnt_t [MaxTxns-1:0] cnt_oup; cnt_idx_t cnt_free_idx, cnt_r_idx; for (genvar i = 0; i < MaxTxns; i++) begin : gen_cnt - counter #( - .WIDTH ( $bits(cnt_t) ) + cc_counter #( + .Width ( $bits(cnt_t) ) ) i_cnt ( .clk_i, .rst_ni, - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( cnt_dec[i] ), .load_i ( cnt_set[i] ), .down_i ( 1'b1 ), @@ -584,9 +582,9 @@ module axi_burst_counters #( end assign cnt_inp = {1'b0, alloc_len_i} + 1; - lzc #( - .WIDTH ( MaxTxns ), - .MODE ( 1'b0 ) // start counting at index 0 + cc_lzc #( + .Width ( MaxTxns ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) // start counting at index 0 ) i_lzc ( .in_i ( cnt_free ), .cnt_o ( cnt_free_idx ), @@ -595,13 +593,14 @@ module axi_burst_counters #( logic idq_inp_req, idq_inp_gnt, idq_oup_gnt, idq_oup_valid, idq_oup_pop; - id_queue #( - .ID_WIDTH ( $bits(id_t) ), - .CAPACITY ( MaxTxns ), + cc_id_queue #( + .IdWidth ( $bits(id_t) ), + .Capacity ( MaxTxns ), .data_t ( cnt_idx_t ) ) i_idq ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .inp_id_i ( alloc_id_i ), .inp_data_i ( cnt_free_idx ), .inp_req_i ( idq_inp_req ), @@ -649,6 +648,6 @@ module axi_burst_counters #( end // registers - `FFARN(err_q, err_d, '0, clk_i, rst_ni) + `FF(err_q, err_d, '0, clk_i, rst_ni) endmodule diff --git a/src/axi_bus_compare.sv b/src/axi_bus_compare.sv index e1a3426ee..5f14677b6 100644 --- a/src/axi_bus_compare.sv +++ b/src/axi_bus_compare.sv @@ -45,8 +45,6 @@ module axi_bus_compare #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4+ATOP A channel request in input axi_req_t axi_a_req_i, /// AXI4+ATOP A channel response out @@ -164,55 +162,60 @@ module axi_bus_compare #( //----------------------------------- // Channel A stream forks //----------------------------------- - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_aw_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_req_i.aw_valid ), .ready_o ( axi_a_rsp_o.aw_ready ), .valid_o ( {fifo_sel_valid_aw_a, axi_a_req_o.aw_valid} ), .ready_i ( {fifo_sel_ready_aw_a, axi_a_rsp_i.aw_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_w_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_req_i.w_valid ), .ready_o ( axi_a_rsp_o.w_ready ), .valid_o ( {fifo_sel_valid_w_a, axi_a_req_o.w_valid} ), .ready_i ( {fifo_sel_ready_w_a, axi_a_rsp_i.w_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_b_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_rsp_i.b_valid ), .ready_o ( axi_a_req_o.b_ready ), .valid_o ( {fifo_sel_valid_b_a, axi_a_rsp_o.b_valid} ), .ready_i ( {fifo_sel_ready_b_a, axi_a_req_i.b_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_ar_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_req_i.ar_valid ), .ready_o ( axi_a_rsp_o.ar_ready ), .valid_o ( {fifo_sel_valid_ar_a, axi_a_req_o.ar_valid} ), .ready_i ( {fifo_sel_ready_ar_a, axi_a_rsp_i.ar_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_r_a ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_a_rsp_i.r_valid ), .ready_o ( axi_a_req_o.r_ready ), .valid_o ( {fifo_sel_valid_r_a, axi_a_rsp_o.r_valid} ), @@ -225,15 +228,15 @@ module axi_bus_compare #( //----------------------------------- for (genvar id = 0; id < 2**AxiIdWidth; id++) begin : gen_fifos_a - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_aw_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_aw_chan_t ) ) i_stream_fifo_aw_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_req_i.aw ), @@ -244,15 +247,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_aw_a [id] & fifo_cmp_valid_aw_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_b_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_b_chan_t ) ) i_stream_fifo_b_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_rsp_i.b ), @@ -263,15 +266,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_b_a [id] & fifo_cmp_valid_b_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_ar_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_ar_chan_t ) ) i_stream_fifo_ar_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_req_i.ar ), @@ -283,15 +286,14 @@ module axi_bus_compare #( ); if (UseSize) begin : gen_r_size - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( $clog2(DataWidth/8)+3 ), - // .DATA_WIDTH ( 7+3 ), - .DEPTH ( 2*FifoDepth ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( $clog2(DataWidth/8)+3 ), + .Depth ( 2*FifoDepth ) ) i_stream_fifo_w_size ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o (), .data_i ( {axi_a_req_i.ar.addr[$clog2(DataWidth/8)-1:0], axi_a_req_i.ar.size} ), @@ -322,15 +324,15 @@ module axi_bus_compare #( end - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_r_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_r_chan_t ) ) i_stream_fifo_r_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_rsp_i.r ), @@ -343,15 +345,14 @@ module axi_bus_compare #( end if (UseSize) begin : gen_w_size - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( $clog2(DataWidth/8)+3 ), - // .DATA_WIDTH ( 7+3 ), - .DEPTH ( FifoDepth ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( $clog2(DataWidth/8)+3 ), + .Depth ( FifoDepth ) ) i_stream_fifo_w_size ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o (), .data_i ( {axi_a_req_i.aw.addr[$clog2(DataWidth/8)-1:0], axi_a_req_i.aw.size} ), @@ -381,15 +382,15 @@ module axi_bus_compare #( assign w_lower = '0; end - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_w_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_w_chan_t ) ) i_stream_fifo_w_a ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_a_req_i.w ), @@ -443,55 +444,60 @@ module axi_bus_compare #( //----------------------------------- // Channel B stream forks //----------------------------------- - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_aw_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_req_i.aw_valid ), .ready_o ( axi_b_rsp_o.aw_ready ), .valid_o ( {fifo_sel_valid_aw_b, axi_b_req_o.aw_valid} ), .ready_i ( {fifo_sel_ready_aw_b, axi_b_rsp_i.aw_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_w_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_req_i.w_valid ), .ready_o ( axi_b_rsp_o.w_ready ), .valid_o ( {fifo_sel_valid_w_b, axi_b_req_o.w_valid} ), .ready_i ( {fifo_sel_ready_w_b, axi_b_rsp_i.w_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_b_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_rsp_i.b_valid ), .ready_o ( axi_b_req_o.b_ready ), .valid_o ( {fifo_sel_valid_b_b, axi_b_rsp_o.b_valid} ), .ready_i ( {fifo_sel_ready_b_b, axi_b_req_i.b_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_ar_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_req_i.ar_valid ), .ready_o ( axi_b_rsp_o.ar_ready ), .valid_o ( {fifo_sel_valid_ar_b, axi_b_req_o.ar_valid} ), .ready_i ( {fifo_sel_ready_ar_b, axi_b_rsp_i.ar_ready} ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_r_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_b_rsp_i.r_valid ), .ready_o ( axi_b_req_o.r_ready ), .valid_o ( {fifo_sel_valid_r_b, axi_b_rsp_o.r_valid} ), @@ -504,15 +510,15 @@ module axi_bus_compare #( //----------------------------------- for (genvar id = 0; id < 2**AxiIdWidth; id++) begin : gen_fifos_b - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_aw_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_aw_chan_t ) ) i_stream_fifo_aw_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_req_i.aw ), @@ -523,15 +529,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_aw_a [id] & fifo_cmp_valid_aw_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_b_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_b_chan_t ) ) i_stream_fifo_b_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_rsp_i.b ), @@ -542,15 +548,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_b_a [id] & fifo_cmp_valid_b_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_ar_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_ar_chan_t ) ) i_stream_fifo_ar_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_req_i.ar ), @@ -561,15 +567,15 @@ module axi_bus_compare #( .ready_i ( fifo_cmp_valid_ar_a [id] & fifo_cmp_valid_ar_b [id] ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_r_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_r_chan_t ) ) i_stream_fifo_r_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_rsp_i.r ), @@ -581,15 +587,15 @@ module axi_bus_compare #( ); end - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 1'b0 ), - .DEPTH ( FifoDepth ), - .T ( axi_w_chan_t ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 1'b0 ), + .Depth ( FifoDepth ), + .data_t ( axi_w_chan_t ) ) i_stream_fifo_w_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( axi_b_req_i.w ), diff --git a/src/axi_cdc_dst.sv b/src/axi_cdc_dst.sv index c3e76bfc1..cb831869f 100644 --- a/src/axi_cdc_dst.sv +++ b/src/axi_cdc_dst.sv @@ -57,16 +57,16 @@ module axi_cdc_dst #( input axi_resp_t dst_resp_i ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA // Workaround for a bug in Questa: Pass flat logic vector instead of struct to type parameter. - .T ( logic [$bits(aw_chan_t)-1:0] ), + .data_t ( logic [$bits(aw_chan_t)-1:0] ), `else // Other tools, such as VCS, have problems with type parameters constructed through `$bits()`. - .T ( aw_chan_t ), + .data_t ( aw_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_aw ( .async_data_i ( async_data_slave_aw_data_i ), .async_wptr_i ( async_data_slave_aw_wptr_i ), @@ -78,14 +78,14 @@ module axi_cdc_dst #( .dst_ready_i ( dst_resp_i.aw_ready ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(w_chan_t)-1:0] ), + .data_t ( logic [$bits(w_chan_t)-1:0] ), `else - .T ( w_chan_t ), + .data_t ( w_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_w ( .async_data_i ( async_data_slave_w_data_i ), .async_wptr_i ( async_data_slave_w_wptr_i ), @@ -97,14 +97,14 @@ module axi_cdc_dst #( .dst_ready_i ( dst_resp_i.w_ready ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(b_chan_t)-1:0] ), + .data_t ( logic [$bits(b_chan_t)-1:0] ), `else - .T ( b_chan_t ), + .data_t ( b_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_b ( .src_clk_i ( dst_clk_i ), .src_rst_ni ( dst_rst_ni ), @@ -116,14 +116,14 @@ module axi_cdc_dst #( .async_rptr_i ( async_data_slave_b_rptr_i ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(ar_chan_t)-1:0] ), + .data_t ( logic [$bits(ar_chan_t)-1:0] ), `else - .T ( ar_chan_t ), + .data_t ( ar_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_ar ( .dst_clk_i, .dst_rst_ni, @@ -135,14 +135,14 @@ module axi_cdc_dst #( .async_rptr_o ( async_data_slave_ar_rptr_o ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(r_chan_t)-1:0] ), + .data_t ( logic [$bits(r_chan_t)-1:0] ), `else - .T ( r_chan_t ), + .data_t ( r_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_r ( .src_clk_i ( dst_clk_i ), .src_rst_ni ( dst_rst_ni ), diff --git a/src/axi_cdc_src.sv b/src/axi_cdc_src.sv index 36e4e6119..902f5136e 100644 --- a/src/axi_cdc_src.sv +++ b/src/axi_cdc_src.sv @@ -57,15 +57,15 @@ module axi_cdc_src #( output logic [LogDepth:0] async_data_master_r_rptr_o ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( // Workaround for a bug in Questa (see comment in `axi_cdc_dst` for details). `ifdef QUESTA - .T ( logic [$bits(aw_chan_t)-1:0] ), + .data_t ( logic [$bits(aw_chan_t)-1:0] ), `else - .T ( aw_chan_t ), + .data_t ( aw_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_aw ( .src_clk_i, .src_rst_ni, @@ -77,14 +77,14 @@ module axi_cdc_src #( .async_rptr_i ( async_data_master_aw_rptr_i ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(w_chan_t)-1:0] ), + .data_t ( logic [$bits(w_chan_t)-1:0] ), `else - .T ( w_chan_t ), + .data_t ( w_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_w ( .src_clk_i, .src_rst_ni, @@ -96,14 +96,14 @@ module axi_cdc_src #( .async_rptr_i ( async_data_master_w_rptr_i ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(b_chan_t)-1:0] ), + .data_t ( logic [$bits(b_chan_t)-1:0] ), `else - .T ( b_chan_t ), + .data_t ( b_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_b ( .dst_clk_i ( src_clk_i ), .dst_rst_ni ( src_rst_ni ), @@ -115,14 +115,14 @@ module axi_cdc_src #( .async_rptr_o ( async_data_master_b_rptr_o ) ); - cdc_fifo_gray_src #( + cc_cdc_fifo_gray_src #( `ifdef QUESTA - .T ( logic [$bits(ar_chan_t)-1:0] ), + .data_t ( logic [$bits(ar_chan_t)-1:0] ), `else - .T ( ar_chan_t ), + .data_t ( ar_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_src_ar ( .src_clk_i, .src_rst_ni, @@ -134,14 +134,14 @@ module axi_cdc_src #( .async_rptr_i ( async_data_master_ar_rptr_i ) ); - cdc_fifo_gray_dst #( + cc_cdc_fifo_gray_dst #( `ifdef QUESTA - .T ( logic [$bits(r_chan_t)-1:0] ), + .data_t ( logic [$bits(r_chan_t)-1:0] ), `else - .T ( r_chan_t ), + .data_t ( r_chan_t ), `endif - .LOG_DEPTH ( LogDepth ), - .SYNC_STAGES ( SyncStages ) + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ) ) i_cdc_fifo_gray_dst_r ( .dst_clk_i ( src_clk_i ), .dst_rst_ni ( src_rst_ni ), diff --git a/src/axi_cut.sv b/src/axi_cut.sv index ace6d7497..17309198d 100644 --- a/src/axi_cut.sv +++ b/src/axi_cut.sv @@ -46,12 +46,13 @@ module axi_cut #( ); // a spill register for each channel - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( BypassAw ) ) i_reg_aw ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_resp_o.aw_ready ), .data_i ( slv_req_i.aw ), @@ -60,12 +61,13 @@ module axi_cut #( .data_o ( mst_req_o.aw ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( BypassW ) ) i_reg_w ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -74,12 +76,13 @@ module axi_cut #( .data_o ( mst_req_o.w ) ); - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( BypassB ) ) i_reg_b ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -88,12 +91,13 @@ module axi_cut #( .data_o ( slv_resp_o.b ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( BypassAr ) ) i_reg_ar ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_resp_o.ar_ready ), .data_i ( slv_req_i.ar ), @@ -102,12 +106,13 @@ module axi_cut #( .data_o ( mst_req_o.ar ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( BypassR ) ) i_reg_r ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv index 8d217d14e..3b34ed259 100644 --- a/src/axi_delayer.sv +++ b/src/axi_delayer.sv @@ -40,13 +40,14 @@ module axi_delayer #( input axi_resp_t mst_resp_i ); // AW - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomInput ), .FixedDelay ( FixedDelayInput ), .payload_t ( aw_chan_t ) ) i_stream_delay_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( slv_req_i.aw ), .ready_o ( slv_resp_o.aw_ready ), .valid_i ( slv_req_i.aw_valid ), @@ -56,13 +57,14 @@ module axi_delayer #( ); // AR - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomInput ), .FixedDelay ( FixedDelayInput ), .payload_t ( ar_chan_t ) ) i_stream_delay_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( slv_req_i.ar ), .ready_o ( slv_resp_o.ar_ready ), .valid_i ( slv_req_i.ar_valid ), @@ -72,13 +74,14 @@ module axi_delayer #( ); // W - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomInput ), .FixedDelay ( FixedDelayInput ), .payload_t ( w_chan_t ) ) i_stream_delay_w ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( slv_req_i.w ), .ready_o ( slv_resp_o.w_ready ), .valid_i ( slv_req_i.w_valid ), @@ -88,13 +91,14 @@ module axi_delayer #( ); // B - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomOutput ), .FixedDelay ( FixedDelayOutput ), .payload_t ( b_chan_t ) ) i_stream_delay_b ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( mst_resp_i.b ), .ready_o ( mst_req_o.b_ready ), .valid_i ( mst_resp_i.b_valid ), @@ -104,13 +108,14 @@ module axi_delayer #( ); // R - stream_delay #( + cc_stream_delay #( .StallRandom ( StallRandomOutput ), .FixedDelay ( FixedDelayOutput ), .payload_t ( r_chan_t ) ) i_stream_delay_r ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .payload_i ( mst_resp_i.r ), .ready_o ( mst_req_o.r_ready ), .valid_i ( mst_resp_i.r_valid ), diff --git a/src/axi_demux.sv b/src/axi_demux.sv index 899d83521..c32efca10 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -64,7 +64,6 @@ module axi_demux #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, // Slave Port input axi_req_t slv_req_i, input select_t slv_aw_select_i, @@ -86,12 +85,13 @@ module axi_demux #( select_t slv_aw_select, slv_ar_select; - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_aw_ready_chan ), .data_i ( slv_req_i.aw ), @@ -99,12 +99,13 @@ module axi_demux #( .ready_i ( slv_resp_cut.aw_ready ), .data_o ( slv_req_cut.aw ) ); - spill_register #( - .T ( select_t ), + cc_spill_register #( + .data_t ( select_t ), .Bypass ( ~SpillAw ) ) i_aw_select_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_aw_ready_sel ), .data_i ( slv_aw_select_i ), @@ -116,12 +117,13 @@ module axi_demux #( assign slv_resp_o.aw_ready = slv_aw_ready_chan & slv_aw_ready_sel; assign slv_req_cut.aw_valid = slv_aw_valid_chan & slv_aw_valid_sel; - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -129,12 +131,13 @@ module axi_demux #( .ready_i ( slv_resp_cut.w_ready ), .data_o ( slv_req_cut.w ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_ar_ready_chan ), .data_i ( slv_req_i.ar ), @@ -142,12 +145,13 @@ module axi_demux #( .ready_i ( slv_resp_cut.ar_ready ), .data_o ( slv_req_cut.ar ) ); - spill_register #( - .T ( select_t ), + cc_spill_register #( + .data_t ( select_t ), .Bypass ( ~SpillAr ) ) i_ar_sel_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_ar_ready_sel ), .data_i ( slv_ar_select_i ), @@ -159,12 +163,13 @@ module axi_demux #( assign slv_resp_o.ar_ready = slv_ar_ready_chan & slv_ar_ready_sel; assign slv_req_cut.ar_valid = slv_ar_valid_chan & slv_ar_valid_sel; - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_resp_cut.b_valid ), .ready_o ( slv_req_cut.b_ready ), .data_i ( slv_resp_cut.b ), @@ -172,12 +177,13 @@ module axi_demux #( .ready_i ( slv_req_i.b_ready ), .data_o ( slv_resp_o.b ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_resp_cut.r_valid ), .ready_o ( slv_req_cut.r_ready ), .data_i ( slv_resp_cut.r ), @@ -198,7 +204,6 @@ module axi_demux #( ) i_demux_simple ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( slv_req_cut ), .slv_aw_select_i ( slv_aw_select ), @@ -234,7 +239,6 @@ module axi_demux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable input select_t slv_aw_select_i, // has to be stable, when aw_valid input select_t slv_ar_select_i, // has to be stable, when ar_valid AXI_BUS.Slave slv, // slave port @@ -289,7 +293,6 @@ module axi_demux_intf #( ) i_axi_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable // slave port .slv_req_i ( slv_req ), .slv_aw_select_i ( slv_aw_select_i ), diff --git a/src/axi_demux_id_counters.sv b/src/axi_demux_id_counters.sv index 7e8c88da5..776bfe8b2 100644 --- a/src/axi_demux_id_counters.sv +++ b/src/axi_demux_id_counters.sv @@ -109,13 +109,13 @@ module axi_demux_id_counters #( endcase end - delta_counter #( - .WIDTH ( CounterWidth ), - .STICKY_OVERFLOW ( 1'b0 ) + cc_delta_counter #( + .Width ( CounterWidth ), + .StickyOverflow ( 1'b0 ) ) i_in_flight_cnt ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( cnt_en ), .load_i ( 1'b0 ), .down_i ( cnt_down ), @@ -128,11 +128,11 @@ module axi_demux_id_counters #( assign cnt_full[i] = overflow | (&in_flight); // holds the selection signal for this id - `FFLARN(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni) + `FFL(mst_select_q[i], push_mst_select_i, push_en[i], '0, clk_i, rst_ni) // pragma translate_off `ifndef VERILATOR -`ifndef XSIM +`ifndef XILINX_SIMULATOR // Validate parameters. cnt_underflow: assert property( @(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else diff --git a/src/axi_demux_simple.sv b/src/axi_demux_simple.sv index 3f854c14f..357b643c2 100644 --- a/src/axi_demux_simple.sv +++ b/src/axi_demux_simple.sv @@ -55,7 +55,6 @@ module axi_demux_simple #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, // Slave Port input axi_req_t slv_req_i, input select_t slv_aw_select_i, @@ -66,447 +65,38 @@ module axi_demux_simple #( input axi_resp_t [NoMstPorts-1:0] mst_resps_i ); - localparam int unsigned IdCounterWidth = cf_math_pkg::idx_width(MaxTrans); - typedef logic [IdCounterWidth-1:0] id_cnt_t; + logic [NoMstPorts-1:0] aw_select_mask; + + assign aw_select_mask = 1'b1 << slv_aw_select_i; + + axi_mcast_demux_simple #( + .AxiIdWidth (AxiIdWidth), + .AtopSupport (AtopSupport), + .axi_req_t (axi_req_t), + .axi_resp_t (axi_resp_t), + .NoMstPorts (NoMstPorts), + .MaxTrans (MaxTrans), + .AxiLookBits (AxiLookBits), + .UniqueIds (UniqueIds), + .NoMulticastPorts (0), + .MaxMcastTrans (1) + ) i_axi_mcast_demux_simple ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_req_i (slv_req_i), + .slv_aw_select_i (aw_select_mask), + .slv_aw_addr_i ('0), + .slv_aw_mask_i ('0), + .slv_ar_select_i (slv_ar_select_i), + .slv_resp_o (slv_resp_o), + .mst_reqs_o (mst_reqs_o), + .mst_resps_i (mst_resps_i), + .mst_is_mcast_o (), + .mst_aw_commit_o () + ); + + `ASSUME(aw_select, slv_req_i.aw_valid |-> (slv_aw_select_i < NoMstPorts), clk_i, rst_ni, + $sformatf("slv_aw_select_i is %d: AW has selected a slave that is not defined.\ + NoMstPorts: %d", slv_aw_select_i, NoMstPorts)) - // pass through if only one master port - if (NoMstPorts == 32'h1) begin : gen_no_demux - `AXI_ASSIGN_REQ_STRUCT(mst_reqs_o[0], slv_req_i) - `AXI_ASSIGN_RESP_STRUCT(slv_resp_o, mst_resps_i[0]) - end else begin - - //-------------------------------------- - //-------------------------------------- - // Signal Declarations - //-------------------------------------- - //-------------------------------------- - - //-------------------------------------- - // Write Transaction - //-------------------------------------- - - // Register which locks the AW valid signal - logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; - logic aw_valid, aw_ready; - - // AW ID counter - select_t lookup_aw_select; - logic aw_select_occupied, aw_id_cnt_full; - // Upon an ATOP load, inject IDs from the AW into the AR channel - logic atop_inject; - - // W select counter: stores the decision to which master W beats should go - select_t w_select, w_select_q; - logic w_select_valid; - id_cnt_t w_open; - logic w_cnt_up, w_cnt_down; - - // B channles input into the arbitration - logic [NoMstPorts-1:0] mst_b_valids, mst_b_readies; - - //-------------------------------------- - // Read Transaction - //-------------------------------------- - - // AR ID counter - select_t lookup_ar_select; - logic ar_select_occupied, ar_id_cnt_full; - logic ar_push; - - // Register which locks the AR valid signel - logic lock_ar_valid_d, lock_ar_valid_q, load_ar_lock; - logic ar_valid, ar_ready; - - logic [NoMstPorts-1:0] mst_r_valids, mst_r_readies; - - - - - - - - //-------------------------------------- - // Channel Control - //-------------------------------------- - //-------------------------------------- - - //-------------------------------------- - // AW Channel - //-------------------------------------- - - // Control of the AW handshake - always_comb begin - // AXI Handshakes - slv_resp_o.aw_ready = 1'b0; - aw_valid = 1'b0; - // `lock_aw_valid`, used to be protocol conform as it is not allowed to deassert - // a valid if there was no corresponding ready. As this process has to be able to inject - // an AXI ID into the counter of the AR channel on an ATOP, there could be a case where - // this process waits on `aw_ready` but in the mean time on the AR channel the counter gets - // full. - lock_aw_valid_d = lock_aw_valid_q; - load_aw_lock = 1'b0; - // AW ID counter and W FIFO - w_cnt_up = 1'b0; - // ATOP injection into ar counter - atop_inject = 1'b0; - // we had an arbitration decision, the valid is locked, wait for the transaction - if (lock_aw_valid_q) begin - aw_valid = 1'b1; - // transaction - if (aw_ready) begin - slv_resp_o.aw_ready = 1'b1; - lock_aw_valid_d = 1'b0; - load_aw_lock = 1'b1; - // inject the ATOP if necessary - atop_inject = slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; - end - end else begin - // An AW can be handled if `i_aw_id_counter` and `i_counter_open_w` are not full. An ATOP that - // requires an R response can be handled if additionally `i_ar_id_counter` is not full (this - // only applies if ATOPs are supported at all). - if (!aw_id_cnt_full && (w_open != {IdCounterWidth{1'b1}}) && - (!(ar_id_cnt_full && slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) || - !AtopSupport)) begin - // There is a valid AW vector make the id lookup and go further, if it passes. - // Also stall if previous transmitted AWs still have active W's in flight. - // This prevents deadlocking of the W channel. The counters are there for the - // Handling of the B responses. - if (slv_req_i.aw_valid && - ((w_open == '0) || (w_select == slv_aw_select_i)) && - (!aw_select_occupied || (slv_aw_select_i == lookup_aw_select))) begin - // connect the handshake - aw_valid = 1'b1; - // push arbitration to the W FIFO regardless, do not wait for the AW transaction - w_cnt_up = 1'b1; - // on AW transaction - if (aw_ready) begin - slv_resp_o.aw_ready = 1'b1; - atop_inject = slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; - // no AW transaction this cycle, lock the decision - end else begin - lock_aw_valid_d = 1'b1; - load_aw_lock = 1'b1; - end - end - end - end - end - - // lock the valid signal, as the selection gets pushed into the W FIFO on first assertion, - // prevent further pushing - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) - - if (UniqueIds) begin : gen_unique_ids_aw - // If the `UniqueIds` parameter is set, each write transaction has an ID that is unique among - // all in-flight write transactions, or all write transactions with a given ID target the same - // master port as all write transactions with the same ID, or both. This means that the - // signals that are driven by the ID counters if this parameter is not set can instead be - // derived from existing signals. The ID counters can therefore be omitted. - assign lookup_aw_select = slv_aw_select_i; - assign aw_select_occupied = 1'b0; - assign aw_id_cnt_full = 1'b0; - end else begin : gen_aw_id_counter - axi_demux_id_counters #( - .AxiIdBits ( AxiLookBits ), - .CounterWidth ( IdCounterWidth ), - .mst_port_select_t ( select_t ) - ) i_aw_id_counter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .lookup_axi_id_i ( slv_req_i.aw.id[0+:AxiLookBits] ), - .lookup_mst_select_o ( lookup_aw_select ), - .lookup_mst_select_occupied_o ( aw_select_occupied ), - .full_o ( aw_id_cnt_full ), - .inject_axi_id_i ( '0 ), - .inject_i ( 1'b0 ), - .push_axi_id_i ( slv_req_i.aw.id[0+:AxiLookBits] ), - .push_mst_select_i ( slv_aw_select_i ), - .push_i ( w_cnt_up ), - .pop_axi_id_i ( slv_resp_o.b.id[0+:AxiLookBits] ), - .pop_i ( slv_resp_o.b_valid & slv_req_i.b_ready ), - .any_outstanding_trx_o ( ) - ); - // pop from ID counter on outward transaction - end - - // This counter steers the demultiplexer of the W channel. - // `w_select` determines, which handshaking is connected. - // AWs are only forwarded, if the counter is empty, or `w_select_q` is the same as - // `slv_aw_select_i`. - counter #( - .WIDTH ( IdCounterWidth ), - .STICKY_OVERFLOW ( 1'b0 ) - ) i_counter_open_w ( - .clk_i, - .rst_ni, - .clear_i ( 1'b0 ), - .en_i ( w_cnt_up ^ w_cnt_down ), - .load_i ( 1'b0 ), - .down_i ( w_cnt_down ), - .d_i ( '0 ), - .q_o ( w_open ), - .overflow_o ( /*not used*/ ) - ); - - `FFLARN(w_select_q, slv_aw_select_i, w_cnt_up, select_t'(0), clk_i, rst_ni) - assign w_select = (|w_open) ? w_select_q : slv_aw_select_i; - assign w_select_valid = w_cnt_up | (|w_open); - - //-------------------------------------- - // W Channel - //-------------------------------------- - - //-------------------------------------- - // B Channel - //-------------------------------------- - logic [cf_math_pkg::idx_width(NoMstPorts)-1:0] b_idx; - - // Arbitration of the different B responses - rr_arb_tree #( - .NumIn ( NoMstPorts ), - .DataType ( logic ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) - ) i_b_mux ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), - .rr_i ( '0 ), - .req_i ( mst_b_valids ), - .gnt_o ( mst_b_readies ), - .data_i ( '0 ), - .gnt_i ( slv_req_i.b_ready ), - .req_o ( slv_resp_o.b_valid ), - .data_o ( ), - .idx_o ( b_idx ) - ); - - always_comb begin - if (slv_resp_o.b_valid) begin - `AXI_SET_B_STRUCT(slv_resp_o.b, mst_resps_i[b_idx].b) - end else begin - slv_resp_o.b = '0; - end - end - - //-------------------------------------- - // AR Channel - //-------------------------------------- - - // control of the AR handshake - always_comb begin - // AXI Handshakes - slv_resp_o.ar_ready = 1'b0; - ar_valid = 1'b0; - // `lock_ar_valid`: Used to be protocol conform as it is not allowed to deassert `ar_valid` - // if there was no corresponding `ar_ready`. There is the possibility that an injection - // of a R response from an `atop` from the AW channel can change the occupied flag of the - // `i_ar_id_counter`, even if it was previously empty. This FF prevents the deassertion. - lock_ar_valid_d = lock_ar_valid_q; - load_ar_lock = 1'b0; - // AR id counter - ar_push = 1'b0; - // The process had an arbitration decision in a previous cycle, the valid is locked, - // wait for the AR transaction. - if (lock_ar_valid_q) begin - ar_valid = 1'b1; - // transaction - if (ar_ready) begin - slv_resp_o.ar_ready = 1'b1; - ar_push = 1'b1; - lock_ar_valid_d = 1'b0; - load_ar_lock = 1'b1; - end - end else begin - // The process can start handling AR transaction if `i_ar_id_counter` has space. - if (!ar_id_cnt_full) begin - // There is a valid AR, so look the ID up. - if (slv_req_i.ar_valid && (!ar_select_occupied || - (slv_ar_select_i == lookup_ar_select))) begin - // connect the AR handshake - ar_valid = 1'b1; - // on transaction - if (ar_ready) begin - slv_resp_o.ar_ready = 1'b1; - ar_push = 1'b1; - // no transaction this cycle, lock the valid decision! - end else begin - lock_ar_valid_d = 1'b1; - load_ar_lock = 1'b1; - end - end - end - end - end - - // this ff is needed so that ar does not get de-asserted if an atop gets injected - `FFLARN(lock_ar_valid_q, lock_ar_valid_d, load_ar_lock, '0, clk_i, rst_ni) - - if (UniqueIds) begin : gen_unique_ids_ar - // If the `UniqueIds` parameter is set, each read transaction has an ID that is unique among - // all in-flight read transactions, or all read transactions with a given ID target the same - // master port as all read transactions with the same ID, or both. This means that the - // signals that are driven by the ID counters if this parameter is not set can instead be - // derived from existing signals. The ID counters can therefore be omitted. - assign lookup_ar_select = slv_ar_select_i; - assign ar_select_occupied = 1'b0; - assign ar_id_cnt_full = 1'b0; - end else begin : gen_ar_id_counter - axi_demux_id_counters #( - .AxiIdBits ( AxiLookBits ), - .CounterWidth ( IdCounterWidth ), - .mst_port_select_t ( select_t ) - ) i_ar_id_counter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .lookup_axi_id_i ( slv_req_i.ar.id[0+:AxiLookBits] ), - .lookup_mst_select_o ( lookup_ar_select ), - .lookup_mst_select_occupied_o ( ar_select_occupied ), - .full_o ( ar_id_cnt_full ), - .inject_axi_id_i ( slv_req_i.aw.id[0+:AxiLookBits] ), - .inject_i ( atop_inject ), - .push_axi_id_i ( slv_req_i.ar.id[0+:AxiLookBits] ), - .push_mst_select_i ( slv_ar_select_i ), - .push_i ( ar_push ), - .pop_axi_id_i ( slv_resp_o.r.id[0+:AxiLookBits] ), - .pop_i ( slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last ), - .any_outstanding_trx_o ( ) - ); - end - - //-------------------------------------- - // R Channel - //-------------------------------------- - - logic [cf_math_pkg::idx_width(NoMstPorts)-1:0] r_idx; - - // Arbitration of the different r responses - rr_arb_tree #( - .NumIn ( NoMstPorts ), - .DataType ( logic ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) - ) i_r_mux ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), - .rr_i ( '0 ), - .req_i ( mst_r_valids ), - .gnt_o ( mst_r_readies ), - .data_i ( '0 ), - .gnt_i ( slv_req_i.r_ready ), - .req_o ( slv_resp_o.r_valid ), - .data_o (), - .idx_o ( r_idx ) - ); - - always_comb begin - if (slv_resp_o.r_valid) begin - `AXI_SET_R_STRUCT(slv_resp_o.r, mst_resps_i[r_idx].r) - end else begin - slv_resp_o.r = '0; - end - end - - assign ar_ready = ar_valid & mst_resps_i[slv_ar_select_i].ar_ready; - assign aw_ready = aw_valid & mst_resps_i[slv_aw_select_i].aw_ready; - - // process that defines the individual demuxes and assignments for the arbitration - // as mst_reqs_o has to be drivem from the same always comb block! - always_comb begin - // default assignments - mst_reqs_o = '0; - slv_resp_o.w_ready = 1'b0; - w_cnt_down = 1'b0; - - for (int unsigned i = 0; i < NoMstPorts; i++) begin - // AW channel - mst_reqs_o[i].aw = slv_req_i.aw; - mst_reqs_o[i].aw_valid = 1'b0; - if (aw_valid && (slv_aw_select_i == i)) begin - mst_reqs_o[i].aw_valid = 1'b1; - end - - // W channel - mst_reqs_o[i].w = slv_req_i.w; - mst_reqs_o[i].w_valid = 1'b0; - if (w_select_valid && (w_select == i)) begin - mst_reqs_o[i].w_valid = slv_req_i.w_valid; - slv_resp_o.w_ready = mst_resps_i[i].w_ready; - w_cnt_down = slv_req_i.w_valid & mst_resps_i[i].w_ready & slv_req_i.w.last; - end - - // B channel - mst_reqs_o[i].b_ready = mst_b_readies[i]; - - // AR channel - mst_reqs_o[i].ar = slv_req_i.ar; - mst_reqs_o[i].ar_valid = 1'b0; - if (ar_valid && (slv_ar_select_i == i)) begin - mst_reqs_o[i].ar_valid = 1'b1; - end - - // R channel - mst_reqs_o[i].r_ready = mst_r_readies[i]; - end - end - // unpack the response B and R channels for the arbitration - for (genvar i = 0; i < NoMstPorts; i++) begin : gen_b_channels - // assign mst_b_chans[i] = mst_resps_i[i].b; - assign mst_b_valids[i] = mst_resps_i[i].b_valid; - // assign mst_r_chans[i] = mst_resps_i[i].r; - assign mst_r_valids[i] = mst_resps_i[i].r_valid; - end - -// Validate parameters. -// pragma translate_off -`ifndef VERILATOR - initial begin: validate_params - no_mst_ports: assume (NoMstPorts > 0) else - $fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1"); - AXI_ID_BITS: assume (AxiIdWidth >= AxiLookBits) else - $fatal(1, "AxiIdBits has to be equal or smaller than AxiIdWidth."); - end -`ifndef XSIM - default disable iff (!rst_ni); - aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> - (slv_aw_select_i < NoMstPorts))) else - $fatal(1, "slv_aw_select_i is %d: AW has selected a slave that is not defined.\ - NoMstPorts: %d", slv_aw_select_i, NoMstPorts); - ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |-> - (slv_ar_select_i < NoMstPorts))) else - $fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\ - NoMstPorts: %d", slv_ar_select_i, NoMstPorts); - aw_valid_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) |=> aw_valid) else - $fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle."); - ar_valid_stable: assert property( @(posedge clk_i) - (ar_valid && !ar_ready) |=> ar_valid) else - $fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle."); - slv_aw_chan_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) - |=> $stable(slv_req_i.aw)) else - $fatal(1, "slv_aw_chan unstable with valid set."); - slv_aw_select_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) - |=> $stable(slv_aw_select_i)) else - $fatal(1, "slv_aw_select_i unstable with valid set."); - slv_ar_chan_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) - |=> $stable(slv_req_i.ar)) else - $fatal(1, "slv_ar_chan unstable with valid set."); - slv_ar_select_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) - |=> $stable(slv_ar_select_i)) else - $fatal(1, "slv_ar_select_i unstable with valid set."); - internal_ar_select: assert property( @(posedge clk_i) - (ar_valid |-> slv_ar_select_i < NoMstPorts)) - else $fatal(1, "slv_ar_select_i illegal while ar_valid."); - internal_aw_select: assert property( @(posedge clk_i) - (aw_valid |-> slv_aw_select_i < NoMstPorts)) - else $fatal(1, "slv_aw_select_i illegal while aw_valid."); - w_underflow: assert property( @(posedge clk_i) - ((w_open == '0) && (w_cnt_up ^ w_cnt_down) |-> !w_cnt_down)) else - $fatal(1, "W counter underflowed!"); - `ASSUME(NoAtopAllowed, !AtopSupport && slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0) -`endif -`endif -// pragma translate_on - end endmodule diff --git a/src/axi_dw_converter.sv b/src/axi_dw_converter.sv index 7e6f6dad3..3f1dff199 100644 --- a/src/axi_dw_converter.sv +++ b/src/axi_dw_converter.sv @@ -11,9 +11,9 @@ // Authors: // - Matheus Cavalcante -// NOTE: The upsizer does not support WRAP bursts, and will answer with SLVERR -// upon receiving a burst of such type. In addition to that, the downsizer also -// does not support FIXED bursts with incoming axlen != 0. +// Burst support: INCR fully supported. FIXED passed through when upsizing, +// single-beat only when downsizing (multi-beat answers with SLVERR). WRAP not +// supported, answers with SLVERR (single-beat WRAP tolerated when upsizing). module axi_dw_converter #( parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv index b508e31ca..aaee12d20 100644 --- a/src/axi_dw_downsizer.sv +++ b/src/axi_dw_downsizer.sv @@ -15,10 +15,8 @@ // Data width downsize conversion. // Connects a wide master to a narrower slave. -// NOTE: The downsizer does not support WRAP bursts, and will answer with SLVERR -// upon receiving a burst of such type. The downsizer does support FIXED -// bursts, but only if they consist of a single beat; it will answer with SLVERR -// on multi-beat FIXED bursts. +// Burst support: INCR fully supported. FIXED single-beat only, multi-beat +// answers with SLVERR. WRAP not supported, answers with SLVERR. module axi_dw_downsizer #( parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads parameter int unsigned AxiSlvPortDataWidth = 8 , // Data width of the slv port @@ -53,7 +51,7 @@ module axi_dw_downsizer #( import axi_pkg::aligned_addr; import axi_pkg::modifiable ; - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // Type used to index which adapter is handling each outstanding transaction. localparam TranIdWidth = AxiMaxReads > 1 ? $clog2(AxiMaxReads) : 1; @@ -96,16 +94,16 @@ module axi_dw_downsizer #( logic [AxiMaxReads-1:0] slv_r_valid_tran; logic [AxiMaxReads-1:0] slv_r_ready_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads ), - .DataType (slv_r_chan_t), + .data_t ( slv_r_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_slv_r_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (slv_r_valid_tran ), .gnt_o (slv_r_ready_tran ), @@ -132,7 +130,7 @@ module axi_dw_downsizer #( assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (2 ), .DataWidth (AxiIdWidth), .ExtPrio (1'b0 ), @@ -141,7 +139,7 @@ module axi_dw_downsizer #( ) i_slv_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i (1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid} ), .gnt_o ({inject_aw_into_ar_gnt, slv_resp_o.ar_ready}), @@ -158,16 +156,16 @@ module axi_dw_downsizer #( logic [AxiMaxReads-1:0] mst_ar_ready_tran; tran_id_t mst_req_idx; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads), - .DataType (ar_chan_t ), + .data_t ( ar_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_mst_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (mst_ar_valid_tran), .gnt_o (mst_ar_ready_tran), @@ -193,7 +191,6 @@ module axi_dw_downsizer #( ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .slv_req_i (axi_err_req ), .slv_resp_o(axi_err_resp) ); @@ -224,7 +221,6 @@ module axi_dw_downsizer #( ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .mst_reqs_o ({axi_err_req, mst_req_o} ), .mst_resps_i ({axi_err_resp, mst_resp_i} ), .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), @@ -276,8 +272,9 @@ module axi_dw_downsizer #( // Find an idle downsizer to handle this transaction tran_id_t idx_idle_downsizer; - lzc #( - .WIDTH(AxiMaxReads) + cc_lzc #( + .Width (AxiMaxReads), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_idle_lzc ( .in_i (idle_read_downsizer), .cnt_o (idx_idle_downsizer ), @@ -291,11 +288,11 @@ module axi_dw_downsizer #( assign id_clash_downsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_downsizer[t]; end - onehot_to_bin #( - .ONEHOT_WIDTH(AxiMaxReads) + cc_onehot_to_bin #( + .OnehotWidth (AxiMaxReads) ) i_id_clash_onehot_to_bin ( - .onehot(id_clash_downsizer ), - .bin (idx_id_clash_downsizer) + .onehot_i (id_clash_downsizer ), + .bin_o (idx_id_clash_downsizer) ); // Choose an idle downsizer, unless there is an id clash @@ -309,13 +306,14 @@ module axi_dw_downsizer #( tran_id_t idqueue_id; logic idqueue_valid; - id_queue #( - .ID_WIDTH(AxiIdWidth ), - .CAPACITY(AxiMaxReads), + cc_id_queue #( + .IdWidth ( AxiIdWidth ), + .Capacity ( AxiMaxReads ), .data_t (tran_id_t ) ) i_read_id_queue ( .clk_i (clk_i ), .rst_ni (rst_ni ), + .clr_i ( 1'b0 ), .inp_id_i (arb_slv_ar_id ), .inp_data_i (idx_ar_downsizer), .inp_req_i (|idqueue_push ), @@ -679,15 +677,15 @@ module axi_dw_downsizer #( logic forward_b_beat_pop; logic forward_b_beat_full; - fifo_v3 #( - .DATA_WIDTH (1 ), - .DEPTH (AxiMaxReads), - .FALL_THROUGH(1'b1 ) + cc_fifo #( + .DataWidth (1 ), + .Depth (AxiMaxReads), + .FallThrough (1'b1 ) ) i_forward_b_beats_queue ( .clk_i (clk_i ), .rst_ni (rst_ni ), + .clr_i ( 1'b0 ), .flush_i (1'b0 ), - .testmode_i(1'b0 ), .data_i (forward_b_beat_i ), .push_i (forward_b_beat_push ), .full_o (forward_b_beat_full ), diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv index 623df8235..1d2e3fe79 100644 --- a/src/axi_dw_upsizer.sv +++ b/src/axi_dw_upsizer.sv @@ -15,8 +15,8 @@ // Data width upsize conversion. // Connects a narrow master to a wider slave. -// NOTE: The upsizer does not support WRAP bursts, and will answer with SLVERR -// upon receiving a burst of such type. +// Burst support: INCR fully supported. FIXED passed through unmodified. +// WRAP not supported, answers with SLVERR (single-beat WRAP is tolerated). module axi_dw_upsizer #( parameter int unsigned AxiMaxReads = 1 , // Number of outstanding reads @@ -53,7 +53,7 @@ module axi_dw_upsizer #( import axi_pkg::beat_addr ; import axi_pkg::modifiable ; - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // Type used to index which adapter is handling each outstanding transaction. localparam TranIdWidth = AxiMaxReads > 1 ? $clog2(AxiMaxReads) : 1; @@ -93,16 +93,16 @@ module axi_dw_upsizer #( logic [AxiMaxReads-1:0] slv_r_valid_tran; logic [AxiMaxReads-1:0] slv_r_ready_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads ), - .DataType (slv_r_chan_t), + .data_t ( slv_r_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_slv_r_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (slv_r_valid_tran ), .gnt_o (slv_r_ready_tran ), @@ -129,7 +129,7 @@ module axi_dw_upsizer #( assign arb_slv_ar_gnt = |arb_slv_ar_gnt_tran; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (2 ), .DataWidth (AxiIdWidth), .ExtPrio (1'b0 ), @@ -138,7 +138,7 @@ module axi_dw_upsizer #( ) i_slv_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i ({inject_aw_into_ar_req, slv_req_i.ar_valid} ), .gnt_o ({inject_aw_into_ar_gnt, slv_resp_o.ar_ready}), @@ -155,16 +155,16 @@ module axi_dw_upsizer #( logic [AxiMaxReads-1:0] mst_ar_ready_tran; tran_id_t mst_req_idx; - rr_arb_tree #( + cc_rr_arb_tree #( .NumIn (AxiMaxReads), - .DataType (ar_chan_t ), + .data_t ( ar_chan_t ), .AxiVldRdy(1'b1 ), .ExtPrio (1'b0 ), .LockIn (1'b1 ) ) i_mst_ar_arb ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .flush_i(1'b0 ), + .clr_i ( 1'b0 ), .rr_i ('0 ), .req_i (mst_ar_valid_tran), .gnt_o (mst_ar_ready_tran), @@ -190,7 +190,6 @@ module axi_dw_upsizer #( ) i_axi_err_slv ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .slv_req_i (axi_err_req ), .slv_resp_o(axi_err_resp) ); @@ -221,7 +220,6 @@ module axi_dw_upsizer #( ) i_axi_demux ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .test_i (1'b0 ), .mst_reqs_o ({axi_err_req, mst_req_o} ), .mst_resps_i ({axi_err_resp, mst_resp_i} ), .slv_ar_select_i(mst_req_ar_err[mst_req_idx]), @@ -260,8 +258,9 @@ module axi_dw_upsizer #( // Find an idle upsizer to handle this transaction tran_id_t idx_idle_upsizer; - lzc #( - .WIDTH(AxiMaxReads) + cc_lzc #( + .Width (AxiMaxReads), + .Mode (cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_idle_lzc ( .in_i (idle_read_upsizer), .cnt_o (idx_idle_upsizer ), @@ -275,11 +274,11 @@ module axi_dw_upsizer #( assign id_clash_upsizer[t] = arb_slv_ar_id == mst_ar_id[t] && !idle_read_upsizer[t]; end - onehot_to_bin #( - .ONEHOT_WIDTH(AxiMaxReads) + cc_onehot_to_bin #( + .OnehotWidth (AxiMaxReads) ) i_id_clash_onehot_to_bin ( - .onehot(id_clash_upsizer ), - .bin (idx_id_clash_upsizer) + .onehot_i (id_clash_upsizer ), + .bin_o (idx_id_clash_upsizer) ); // Choose an idle upsizer, unless there is an id clash @@ -300,11 +299,11 @@ module axi_dw_upsizer #( assign rid_upsizer_match[t] = (mst_resp.r.id == mst_ar_id[t]) && !idle_read_upsizer[t]; end - onehot_to_bin #( - .ONEHOT_WIDTH(AxiMaxReads) + cc_onehot_to_bin #( + .OnehotWidth (AxiMaxReads) ) i_rid_upsizer_lzc ( - .onehot(rid_upsizer_match), - .bin (idx_r_upsizer ) + .onehot_i (rid_upsizer_match), + .bin_o (idx_r_upsizer ) ); typedef struct packed { diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index 9035d9a80..f0be32914 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -28,7 +28,6 @@ module axi_err_slv #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave port input axi_req_t slv_req_i, output axi_resp_t slv_resp_o @@ -87,15 +86,15 @@ module axi_err_slv #( assign w_fifo_push = err_req.aw_valid & ~w_fifo_full; assign err_resp.aw_ready = ~w_fifo_full; - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( MaxTrans ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( MaxTrans ), + .data_t ( id_t ) ) i_w_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( test_i ), .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( ), @@ -120,15 +119,15 @@ module axi_err_slv #( end end - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( unsigned'(2) ), // two placed so that w can eat beats if b is not sent - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( unsigned'(2) ), // two placed so that w can eat beats if b is not sent + .data_t ( id_t ) ) i_b_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( test_i ), .full_o ( b_fifo_full ), .empty_o ( b_fifo_empty ), .usage_o ( ), @@ -162,15 +161,15 @@ module axi_err_slv #( assign r_fifo_inp.id = err_req.ar.id; assign r_fifo_inp.len = err_req.ar.len; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MaxTrans ), - .dtype ( r_data_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MaxTrans ), + .data_t ( r_data_t ) ) i_r_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( r_fifo_full ), .empty_o ( r_fifo_empty ), .usage_o ( ), @@ -228,12 +227,12 @@ module axi_err_slv #( end end - counter #( - .WIDTH ($bits(axi_pkg::len_t)) + cc_counter #( + .Width ($bits(axi_pkg::len_t)) ) i_r_counter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( r_cnt_clear ), + .clr_i ( r_cnt_clear ), .en_i ( r_cnt_en ), .load_i ( r_cnt_load ), .down_i ( 1'b1 ), @@ -248,7 +247,7 @@ module axi_err_slv #( assert (Resp == axi_pkg::RESP_DECERR || Resp == axi_pkg::RESP_SLVERR) else $fatal(1, "This module may only generate RESP_DECERR or RESP_SLVERR responses!"); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); if (!ATOPs) begin : gen_assert_atops_unsupported assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0)) else diff --git a/src/axi_fifo.sv b/src/axi_fifo.sv index 8e4cbdfb1..0b854b82a 100644 --- a/src/axi_fifo.sv +++ b/src/axi_fifo.sv @@ -33,7 +33,6 @@ module axi_fifo #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // slave port input axi_req_t slv_req_i, output axi_resp_t slv_resp_o, @@ -63,15 +62,15 @@ module axi_fifo #( assign mst_req_o.b_ready = ~b_fifo_full; // A FiFo for each channel - fifo_v3 #( - .dtype(aw_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (aw_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_aw_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (aw_fifo_full), .empty_o (aw_fifo_empty), .usage_o (), @@ -80,15 +79,15 @@ module axi_fifo #( .data_o (mst_req_o.aw), .pop_i (mst_req_o.aw_valid && mst_resp_i.aw_ready) ); - fifo_v3 #( - .dtype(ar_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (ar_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_ar_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (ar_fifo_full), .empty_o (ar_fifo_empty), .usage_o (), @@ -97,15 +96,15 @@ module axi_fifo #( .data_o (mst_req_o.ar), .pop_i (mst_req_o.ar_valid && mst_resp_i.ar_ready) ); - fifo_v3 #( - .dtype(w_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (w_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_w_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (w_fifo_full), .empty_o (w_fifo_empty), .usage_o (), @@ -114,15 +113,15 @@ module axi_fifo #( .data_o (mst_req_o.w), .pop_i (mst_req_o.w_valid && mst_resp_i.w_ready) ); - fifo_v3 #( - .dtype(r_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (r_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_r_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (r_fifo_full), .empty_o (r_fifo_empty), .usage_o (), @@ -131,15 +130,15 @@ module axi_fifo #( .data_o (slv_resp_o.r), .pop_i (slv_resp_o.r_valid && slv_req_i.r_ready) ); - fifo_v3 #( - .dtype(b_chan_t), - .DEPTH(Depth), - .FALL_THROUGH(FallThrough) + cc_fifo #( + .data_t (b_chan_t), + .Depth (Depth), + .FallThrough (FallThrough) ) i_b_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i (1'b0), - .testmode_i(test_i), .full_o (b_fifo_full), .empty_o (b_fifo_empty), .usage_o (), @@ -174,7 +173,6 @@ module axi_fifo_intf #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_BUS.Slave slv, AXI_BUS.Master mst ); @@ -215,7 +213,6 @@ module axi_fifo_intf #( ) i_axi_fifo ( .clk_i, .rst_ni, - .test_i, .slv_req_i (slv_req), .slv_resp_o(slv_resp), .mst_req_o (mst_req), diff --git a/src/axi_fifo_delay_dyn.sv b/src/axi_fifo_delay_dyn.sv index c06db637d..870efb5a6 100644 --- a/src/axi_fifo_delay_dyn.sv +++ b/src/axi_fifo_delay_dyn.sv @@ -283,7 +283,7 @@ module stream_fifo_delay_dyn #( `endif `endif - if (Depth & (Depth - 1) == 0) + if (Depth == 0 || (Depth & (Depth - 1)) != 0) $fatal(1, "Depth must be a power of two"); localparam int unsigned BookeepingBits = $clog2(Depth) + 1; @@ -327,12 +327,12 @@ module stream_fifo_delay_dyn #( assign payload_o = head_data; - counter #( - .WIDTH ( CounterWidth ) + cc_counter #( + .Width ( CounterWidth ) ) i_counter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .clear_i ( 1'b0 ), + .clr_i ( 1'b0 ), .en_i ( 1'b1 ), .load_i ( 1'b0 ), .down_i ( 1'b0 ), @@ -374,15 +374,15 @@ module stream_fifo_delay_dyn #( .dout ( head_data ) ); `else - fifo_v3 #( - .DATA_WIDTH ( $bits(payload_t) ), - .DEPTH ( Depth ), - .FALL_THROUGH ( 1'b0 ) + cc_fifo #( + .DataWidth ( $bits(payload_t) ), + .Depth ( Depth ), + .FallThrough ( 1'b0 ) ) data_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( payload_i ), .push_i ( fifo_data_push ), .full_o ( fifo_data_full ), @@ -426,15 +426,15 @@ module stream_fifo_delay_dyn #( .dout ( head_deadline ) ); `else - fifo_v3 #( - .DATA_WIDTH ( CounterWidth ), - .DEPTH ( Depth ), - .FALL_THROUGH ( 1'b0 ) + cc_fifo #( + .DataWidth ( CounterWidth ), + .Depth ( Depth ), + .FallThrough ( 1'b0 ) ) deadline_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( tail_deadline ), .push_i ( fifo_dead_push ), .full_o ( fifo_dead_full ), diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv index f97c52fd1..00782f630 100644 --- a/src/axi_id_remap.sv +++ b/src/axi_id_remap.sv @@ -128,7 +128,7 @@ module axi_id_remap #( // Remap tables keep track of in-flight bursts and their input and output IDs. - localparam int unsigned IdxWidth = cf_math_pkg::idx_width(AxiSlvPortMaxUniqIds); + localparam int unsigned IdxWidth = cc_pkg::idx_width(AxiSlvPortMaxUniqIds); typedef logic [AxiSlvPortMaxUniqIds-1:0] field_t; typedef logic [AxiSlvPortIdWidth-1:0] id_inp_t; typedef logic [IdxWidth-1:0] idx_t; @@ -185,9 +185,9 @@ module axi_id_remap #( .pop_inp_id_o ( slv_resp_o.r.id ) ); assign both_free = wr_free & rd_free; - lzc #( - .WIDTH ( AxiSlvPortMaxUniqIds ), - .MODE ( 1'b0 ) + cc_lzc #( + .Width ( AxiSlvPortMaxUniqIds ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc ( .in_i ( both_free ), .cnt_o ( both_free_oup_id ), @@ -415,10 +415,10 @@ module axi_id_remap #( end // Registers - `FFARN(ar_id_q, ar_id_d, '0, clk_i, rst_ni) - `FFARN(ar_prio_q, ar_prio_d, 1'b0, clk_i, rst_ni) - `FFARN(aw_id_q, aw_id_d, '0, clk_i, rst_ni) - `FFARN(state_q, state_d, Ready, clk_i, rst_ni) + `FF(ar_id_q, ar_id_d, '0, clk_i, rst_ni) + `FF(ar_prio_q, ar_prio_d, 1'b0, clk_i, rst_ni) + `FF(aw_id_q, aw_id_d, '0, clk_i, rst_ni) + `FF(state_q, state_d, Ready, clk_i, rst_ni) // pragma translate_off `ifndef VERILATOR @@ -452,7 +452,7 @@ module axi_id_remap #( assert ($bits(mst_req_o.ar.id) == AxiMstPortIdWidth); assert ($bits(mst_resp_i.r.id) == AxiMstPortIdWidth); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assert property (@(posedge clk_i) slv_req_i.aw_valid && slv_resp_o.aw_ready |-> mst_req_o.aw_valid && mst_resp_i.aw_ready); @@ -505,7 +505,7 @@ module axi_id_remap_table #( localparam type id_inp_t = logic [InpIdWidth-1:0], /// Derived (**=do not override**) width of table index (ceiled binary logarithm of /// `MaxUniqInpIds`). - localparam int unsigned IdxWidth = cf_math_pkg::idx_width(MaxUniqInpIds), + localparam int unsigned IdxWidth = cc_pkg::idx_width(MaxUniqInpIds), /// Derived (**=do not override**) type of table index (width = `IdxWidth`). localparam type idx_t = logic [IdxWidth-1:0], /// Derived (**=do not override**) type with one bit per table entry (thus also output ID). @@ -569,9 +569,9 @@ module axi_id_remap_table #( for (genvar i = 0; i < MaxUniqInpIds; i++) begin : gen_free_o assign free_o[i] = table_q[i].cnt == '0; end - lzc #( - .WIDTH ( MaxUniqInpIds ), - .MODE ( 1'b0 ) + cc_lzc #( + .Width ( MaxUniqInpIds ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc_free ( .in_i ( free_o ), .cnt_o ( free_oup_id_o ), @@ -591,9 +591,9 @@ module axi_id_remap_table #( assign match[i] = table_q[i].cnt > 0 && table_q[i].inp_id == exists_inp_id_i; end logic no_match; - lzc #( - .WIDTH ( MaxUniqInpIds ), - .MODE ( 1'b0 ) + cc_lzc #( + .Width ( MaxUniqInpIds ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) ) i_lzc_match ( .in_i ( match ), .cnt_o ( exists_oup_id_o ), @@ -619,12 +619,12 @@ module axi_id_remap_table #( end // Registers - `FFARN(table_q, table_d, '0, clk_i, rst_ni) + `FF(table_q, table_d, '0, clk_i, rst_ni) // Assertions // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assume property (@(posedge clk_i) push_i |-> table_q[push_oup_id_i].cnt == '0 || table_q[push_oup_id_i].inp_id == push_inp_id_i) diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index 94051786c..9cfc82651 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -83,7 +83,7 @@ module axi_id_serialize #( ); /// Number of bits of the slave port ID that determine the mapping to the master port ID - localparam int unsigned SelectWidth = cf_math_pkg::idx_width(AxiMstPortMaxUniqIds); + localparam int unsigned SelectWidth = cc_pkg::idx_width(AxiMstPortMaxUniqIds); /// Slice of slave port IDs that determines the master port ID typedef logic [SelectWidth-1:0] select_t; @@ -200,7 +200,6 @@ module axi_id_serialize #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( slv_req_i ), .slv_aw_select_i ( slv_aw_select ), .slv_ar_select_i ( slv_ar_select ), @@ -270,7 +269,6 @@ module axi_id_serialize #( ) i_axi_mux ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_reqs_i ( from_serializer_reqs ), .slv_resps_o ( from_serializer_resps ), .mst_req_o ( axi_mux_req ), diff --git a/src/axi_interleaved_xbar.sv b/src/axi_interleaved_xbar.sv index 83d215df7..2d04680a7 100644 --- a/src/axi_interleaved_xbar.sv +++ b/src/axi_interleaved_xbar.sv @@ -17,7 +17,7 @@ /// Interleaved version of the crossbar. This module is experimental; use at your own risk. module axi_interleaved_xbar -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter bit ATOPs = 1'b1, @@ -42,7 +42,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_i, input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, output mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, @@ -118,7 +117,7 @@ import cf_math_pkg::idx_width; end end - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .NoRules ( Cfg.NoAddrRules ), .addr_t ( addr_t ), @@ -133,7 +132,7 @@ import cf_math_pkg::idx_width; .default_idx_i ( default_mst_port_i[i] ) ); - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NoAddrRules ), @@ -163,7 +162,7 @@ import cf_math_pkg::idx_width; // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -210,7 +209,6 @@ import cf_math_pkg::idx_width; ) i_axi_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable .slv_req_i ( slv_reqs_mod[i] ), .slv_aw_select_i ( slv_aw_select ), .slv_ar_select_i ( slv_ar_select ), @@ -231,7 +229,6 @@ import cf_math_pkg::idx_width; ) i_axi_err_slv ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable // slave port .slv_req_i ( slv_reqs[i][Cfg.NoMstPorts] ), .slv_resp_o ( slv_resps[i][cfg_NoMstPorts] ) @@ -257,7 +254,6 @@ import cf_math_pkg::idx_width; ) i_axi_err_slv ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( slv_reqs[i][j] ), .slv_resp_o ( slv_resps[i][j] ) ); @@ -292,7 +288,6 @@ import cf_math_pkg::idx_width; ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable .slv_reqs_i ( mst_reqs[i] ), .slv_resps_o ( mst_resps[i] ), .mst_req_o ( mst_ports_req_o[i] ), @@ -302,7 +297,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin : check_params id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); @@ -318,7 +313,7 @@ endmodule : axi_interleaved_xbar `include "axi/typedef.svh" module axi_interleaved_xbar_intf -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter int unsigned AXI_USER_WIDTH = 0, @@ -332,7 +327,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, @@ -404,7 +398,6 @@ import cf_math_pkg::idx_width; ) i_interleaved_xbar ( .clk_i, .rst_ni, - .test_i, .slv_ports_req_i (slv_reqs ), .slv_ports_resp_o (slv_resps), .mst_ports_req_o (mst_reqs ), diff --git a/src/axi_inval_filter.sv b/src/axi_inval_filter.sv index 272f9043f..fc651ae67 100644 --- a/src/axi_inval_filter.sv +++ b/src/axi_inval_filter.sv @@ -35,7 +35,7 @@ module axi_inval_filter #( input logic inval_ready_i ); - import cf_math_pkg::idx_width; + import cc_pkg::idx_width; // Includes `include "axi/typedef.svh" @@ -127,15 +127,15 @@ module axi_inval_filter #( end end - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( MaxTxns ), - .dtype ( aw_chan_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( MaxTxns ), + .data_t ( aw_chan_t ) ) i_aw_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( aw_fifo_full ), .empty_o ( aw_fifo_empty ), .usage_o ( ), diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index cb9a14852..6891b8527 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -115,7 +115,6 @@ module axi_isolate #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i, .slv_aw_select_i ( isolated_o ), .slv_ar_select_i ( isolated_o ), @@ -135,7 +134,6 @@ module axi_isolate #( ) i_axi_err_slv ( .clk_i, .rst_ni, - .test_i ( 1'b0 ), .slv_req_i ( demux_req[1] ), .slv_resp_o ( demux_rsp[1] ) ); @@ -200,11 +198,11 @@ module axi_isolate_inner #( cnt_t pending_ar_d, pending_ar_q; logic update_ar_cnt; - `FFLARN(pending_aw_q, pending_aw_d, update_aw_cnt, '0, clk_i, rst_ni) - `FFLARN(pending_w_q, pending_w_d, update_w_cnt, '0, clk_i, rst_ni) - `FFLARN(pending_ar_q, pending_ar_d, update_ar_cnt, '0, clk_i, rst_ni) - `FFLARN(state_aw_q, state_aw_d, update_aw_state, Isolate, clk_i, rst_ni) - `FFLARN(state_ar_q, state_ar_d, update_ar_state, Isolate, clk_i, rst_ni) + `FFL(pending_aw_q, pending_aw_d, update_aw_cnt, '0, clk_i, rst_ni) + `FFL(pending_w_q, pending_w_d, update_w_cnt, '0, clk_i, rst_ni) + `FFL(pending_ar_q, pending_ar_d, update_ar_cnt, '0, clk_i, rst_ni) + `FFL(state_aw_q, state_aw_d, update_aw_state, Isolate, clk_i, rst_ni) + `FFL(state_ar_q, state_ar_d, update_ar_state, Isolate, clk_i, rst_ni) // Update counters. always_comb begin @@ -392,7 +390,7 @@ module axi_isolate_inner #( initial begin assume (NumPending > 0) else $fatal(1, "At least one pending transaction required."); end -`ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_overflow: assert property (@(posedge clk_i) (pending_aw_q == '1) |=> (pending_aw_q != '0)) else diff --git a/src/axi_lfsr.sv b/src/axi_lfsr.sv index 2085a76fe..530d581d3 100644 --- a/src/axi_lfsr.sv +++ b/src/axi_lfsr.sv @@ -33,8 +33,6 @@ module axi_lfsr #( input logic clk_i, /// Active-low reset input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4 request struct input axi_req_t req_i, /// AXI4 response struct @@ -93,7 +91,6 @@ module axi_lfsr #( ) i_axi_to_axi_lite ( .clk_i, .rst_ni, - .test_i ( testmode_i ), .slv_req_i ( req_i ), .slv_resp_o ( rsp_o ), .mst_req_o ( axi_lite_req ), @@ -107,7 +104,6 @@ module axi_lfsr #( ) i_axi_lite_lfsr ( .clk_i, .rst_ni, - .testmode_i, .w_ser_data_i, .w_ser_data_o, .w_ser_en_i, diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv index 1b979d874..edc5a3d2a 100644 --- a/src/axi_lite_demux.sv +++ b/src/axi_lite_demux.sv @@ -45,7 +45,6 @@ module axi_lite_demux #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, // slave port (AXI4-Lite input), connect master module here input axi_req_t slv_req_i, input select_t slv_aw_select_i, @@ -70,12 +69,13 @@ module axi_lite_demux #( if (NoMstPorts == 32'd1) begin : gen_no_demux // degenerate case, connect slave to master port - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_resp_o.aw_ready ), .data_i ( slv_req_i.aw ), @@ -83,12 +83,13 @@ module axi_lite_demux #( .ready_i ( mst_resps_i[0].aw_ready ), .data_o ( mst_reqs_o[0].aw ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -96,12 +97,13 @@ module axi_lite_demux #( .ready_i ( mst_resps_i[0].w_ready ), .data_o ( mst_reqs_o[0].w ) ); - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resps_i[0].b_valid ), .ready_o ( mst_reqs_o[0].b_ready ), .data_i ( mst_resps_i[0].b ), @@ -109,12 +111,13 @@ module axi_lite_demux #( .ready_i ( slv_req_i.b_ready ), .data_o ( slv_resp_o.b ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_resp_o.ar_ready ), .data_i ( slv_req_i.ar ), @@ -122,12 +125,13 @@ module axi_lite_demux #( .ready_i ( mst_resps_i[0].ar_ready ), .data_o ( mst_reqs_o[0].ar ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resps_i[0].r_valid ), .ready_o ( mst_reqs_o[0].r_ready ), .data_i ( mst_resps_i[0].r ), @@ -194,7 +198,7 @@ module axi_lite_demux #( //-------------------------------------- `ifdef TARGET_VSIM // Workaround for bug in Questa 2020.2 and 2021.1: Flatten the struct into a logic vector before - // instantiating `spill_register`. + // instantiating `cc_spill_register`. typedef logic [$bits(aw_chan_select_t)-1:0] aw_chan_select_flat_t; `else // Other tools, such as VCS, have problems with `$bits()`, so the workaround cannot be used @@ -204,12 +208,13 @@ module axi_lite_demux #( aw_chan_select_flat_t slv_aw_chan_select_in_flat, slv_aw_chan_select_out_flat; assign slv_aw_chan_select_in_flat = {slv_req_i.aw, slv_aw_select_i}; - spill_register #( - .T ( aw_chan_select_flat_t ), + cc_spill_register #( + .data_t ( aw_chan_select_flat_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_resp_o.aw_ready ), .data_i ( slv_aw_chan_select_in_flat ), @@ -265,17 +270,17 @@ module axi_lite_demux #( // lock the valid signal, as the selection gets pushed into the W FIFO on first assertion, // prevent further pushing - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) - fifo_v3 #( - .FALL_THROUGH( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_w_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemtion rule - .testmode_i ( test_i ), .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( /*not used*/ ), @@ -288,12 +293,13 @@ module axi_lite_demux #( //-------------------------------------- // W Channel //-------------------------------------- - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_resp_o.w_ready ), .data_i ( slv_req_i.w ), @@ -311,15 +317,15 @@ module axi_lite_demux #( assign slv_w_ready = ~w_fifo_empty & ~b_fifo_full & mst_resps_i[w_select].w_ready; assign w_fifo_pop = slv_w_valid & slv_w_ready; - fifo_v3 #( - .FALL_THROUGH( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_b_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption - .testmode_i ( test_i ), .full_o ( b_fifo_full ), .empty_o ( b_fifo_empty ), .usage_o ( /*not used*/ ), @@ -332,12 +338,13 @@ module axi_lite_demux #( //-------------------------------------- // B Channel //-------------------------------------- - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_b_valid ), .ready_o ( slv_b_ready ), .data_i ( slv_b_chan ), @@ -366,12 +373,13 @@ module axi_lite_demux #( ar_chan_select_flat_t slv_ar_chan_select_in_flat, slv_ar_chan_select_out_flat; assign slv_ar_chan_select_in_flat = {slv_req_i.ar, slv_ar_select_i}; - spill_register #( - .T ( ar_chan_select_flat_t ), + cc_spill_register #( + .data_t ( ar_chan_select_flat_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_resp_o.ar_ready ), .data_i ( slv_ar_chan_select_in_flat ), @@ -390,15 +398,15 @@ module axi_lite_demux #( assign slv_ar_ready = ~r_fifo_full & mst_resps_i[slv_ar_chan.select].ar_ready; assign r_fifo_push = slv_ar_valid & slv_ar_ready; - fifo_v3 #( - .FALL_THROUGH( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_r_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), // not used, because AXI4-Lite no preemption rule - .testmode_i ( test_i ), .full_o ( r_fifo_full ), .empty_o ( r_fifo_empty ), .usage_o ( /*not used*/ ), @@ -411,12 +419,13 @@ module axi_lite_demux #( //-------------------------------------- // R Channel //-------------------------------------- - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_r_valid ), .ready_o ( slv_r_ready ), .data_i ( slv_r_chan ), @@ -442,7 +451,7 @@ module axi_lite_demux #( // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> (slv_aw_select_i < NoMstPorts))) else @@ -498,7 +507,6 @@ module axi_lite_demux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable input select_t slv_aw_select_i, // has to be stable, when aw_valid input select_t slv_ar_select_i, // has to be stable, when ar_valid AXI_LITE.Slave slv, // slave port @@ -547,7 +555,6 @@ module axi_lite_demux_intf #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i, // slave Port .slv_req_i ( slv_req ), .slv_aw_select_i ( slv_aw_select_i ), // must be stable while slv_aw_valid_i diff --git a/src/axi_lite_dw_converter.sv b/src/axi_lite_dw_converter.sv index 139c2d313..daf20fd23 100644 --- a/src/axi_lite_dw_converter.sv +++ b/src/axi_lite_dw_converter.sv @@ -133,12 +133,13 @@ module axi_lite_dw_converter #( axi_lite_aw_t aw_chan_spill; logic aw_chan_spill_valid, aw_chan_spill_ready; - spill_register #( - .T ( axi_lite_aw_t ), + cc_spill_register #( + .data_t ( axi_lite_aw_t ), .Bypass ( 1'b0 ) ) i_spill_register_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.aw_valid ), .ready_o ( slv_res_o.aw_ready ), .data_i ( slv_req_i.aw ), @@ -160,17 +161,18 @@ module axi_lite_dw_converter #( assign aw_sel_load = mst_req_o.aw_valid & mst_res_i.aw_ready; assign aw_sel_d = sel_t'(aw_sel_q + 1'b1); - `FFLARN(aw_sel_q, aw_sel_d, aw_sel_load, '0, clk_i, rst_ni) + `FFL(aw_sel_q, aw_sel_d, aw_sel_load, '0, clk_i, rst_ni) // Input spill register of the W channel. axi_lite_slv_w_t w_chan_spill; logic w_chan_spill_valid, w_chan_spill_ready; - spill_register #( - .T ( axi_lite_slv_w_t ), + cc_spill_register #( + .data_t ( axi_lite_slv_w_t ), .Bypass ( 1'b0 ) ) i_spill_register_w ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.w_valid ), .ready_o ( slv_res_o.w_ready ), .data_i ( slv_req_i.w ), @@ -193,7 +195,7 @@ module axi_lite_dw_converter #( assign w_sel_load = mst_req_o.w_valid & mst_res_i.w_ready; assign w_sel_d = sel_t'(w_sel_q + 1'b1); - `FFLARN(w_sel_q, w_sel_d, w_sel_load, '0, clk_i, rst_ni) + `FFL(w_sel_q, w_sel_d, w_sel_load, '0, clk_i, rst_ni) // B response aggregation // Slave port B output is the aggregated error of the last few B responses. @@ -216,20 +218,21 @@ module axi_lite_dw_converter #( assign b_sel_d = sel_t'(b_sel_q + 1'b1); assign b_resp_d = (&b_sel_q) ? axi_pkg::RESP_OKAY : (b_resp_q | mst_res_i.b.resp); assign b_resp_load = mst_res_i.b_valid & mst_req_o.b_ready; - `FFLARN(b_sel_q, b_sel_d, b_resp_load, '0, clk_i, rst_ni) - `FFLARN(b_resp_q, b_resp_d, b_resp_load, axi_pkg::RESP_OKAY, clk_i, rst_ni) + `FFL(b_sel_q, b_sel_d, b_resp_load, '0, clk_i, rst_ni) + `FFL(b_resp_q, b_resp_d, b_resp_load, axi_pkg::RESP_OKAY, clk_i, rst_ni) // Read channels. // Input spill register of the AW channel. axi_lite_ar_t ar_chan_spill; logic ar_chan_spill_valid, ar_chan_spill_ready; - spill_register #( - .T ( axi_lite_ar_t ), + cc_spill_register #( + .data_t ( axi_lite_ar_t ), .Bypass ( 1'b0 ) ) i_spill_register_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( slv_req_i.ar_valid ), .ready_o ( slv_res_o.ar_ready ), .data_i ( slv_req_i.ar ), @@ -251,7 +254,7 @@ module axi_lite_dw_converter #( assign ar_sel_load = mst_req_o.ar_valid & mst_res_i.ar_ready; assign ar_sel_d = sel_t'(ar_sel_q + 1'b1); - `FFLARN(ar_sel_q, ar_sel_d, ar_sel_load, '0, clk_i, rst_ni) + `FFL(ar_sel_q, ar_sel_d, ar_sel_load, '0, clk_i, rst_ni) // Responses have to be aggregated, one FF less, as the last data is feed directly through. sel_t r_sel_q, r_sel_d; @@ -260,11 +263,11 @@ module axi_lite_dw_converter #( logic [DownsizeFactor-2:0] r_chan_mst_load; for (genvar i = 0; unsigned'(i) < (DownsizeFactor-1); i++) begin : gen_r_chan_ff assign r_chan_mst_load[i] = (sel_t'(i) == r_sel_q) & mst_res_i.r_valid & mst_req_o.r_ready; - `FFLARN(r_chan_mst_q[i], mst_res_i.r, r_chan_mst_load[i], axi_lite_mst_r_t'{default: '0}, clk_i, rst_ni) + `FFL(r_chan_mst_q[i], mst_res_i.r, r_chan_mst_load[i], axi_lite_mst_r_t'{default: '0}, clk_i, rst_ni) end assign r_sel_load = mst_res_i.r_valid & mst_req_o.r_ready; assign r_sel_d = sel_t'(r_sel_q + 1'b1); - `FFLARN(r_sel_q, r_sel_d, r_sel_load, '0, clk_i, rst_ni) + `FFL(r_sel_q, r_sel_d, r_sel_load, '0, clk_i, rst_ni) always_comb begin : proc_r_chan_oup slv_res_o.r = axi_lite_slv_r_t'{ @@ -332,20 +335,20 @@ module axi_lite_dw_converter #( end end assign lock_aw_d = ~lock_aw_q; - `FFLARN(lock_aw_q, lock_aw_d, load_aw_lock, 1'b0, clk_i, rst_ni) + `FFL(lock_aw_q, lock_aw_d, load_aw_lock, 1'b0, clk_i, rst_ni) // The selection comes from part of the AW address. assign aw_sel = sel_t'(slv_req_i.aw.addr >> SelOffset); - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( UpsizeFactor ), - .dtype ( sel_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( UpsizeFactor ), + .data_t ( sel_t ) ) i_fifo_w_sel ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( w_full ), .empty_o ( w_empty ), .usage_o ( /*not used*/ ), @@ -414,20 +417,20 @@ module axi_lite_dw_converter #( end end assign lock_ar_d = ~lock_ar_q; - `FFLARN(lock_ar_q, lock_ar_d, load_ar_lock, 1'b0, clk_i, rst_ni) + `FFL(lock_ar_q, lock_ar_d, load_ar_lock, 1'b0, clk_i, rst_ni) // The selection comes from part of the AW address. assign ar_sel = sel_t'(slv_req_i.ar.addr >> SelOffset); - fifo_v3 #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( UpsizeFactor ), - .dtype ( sel_t ) + cc_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( UpsizeFactor ), + .data_t ( sel_t ) ) i_fifo_r_sel ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( r_full ), .empty_o ( r_empty ), .usage_o ( /*not used*/ ), @@ -464,7 +467,7 @@ module axi_lite_dw_converter #( assume ($onehot(AxiSlvPortDataWidth)) else $fatal(1, "AxiSlvPortDataWidth must be power of 2"); assume ($onehot(AxiMstPortDataWidth)) else $fatal(1, "AxiMstPortDataWidth must be power of 2"); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); stable_aw: assert property (@(posedge clk_i) (mst_req_o.aw_valid && !mst_res_i.aw_ready) |=> $stable(mst_req_o.aw)) else diff --git a/src/axi_lite_from_mem.sv b/src/axi_lite_from_mem.sv index 2b7e9e38c..1d2d76619 100644 --- a/src/axi_lite_from_mem.sv +++ b/src/axi_lite_from_mem.sv @@ -170,21 +170,21 @@ module axi_lite_from_mem #( end end - `FFARN(aw_sent_q, aw_sent_d, 1'b0, clk_i, rst_ni) - `FFARN(w_sent_q, w_sent_d, 1'b0, clk_i, rst_ni) + `FF(aw_sent_q, aw_sent_d, 1'b0, clk_i, rst_ni) + `FF(w_sent_q, w_sent_d, 1'b0, clk_i, rst_ni) // Select which response should be forwarded. `1` write response, `0` read response. logic rsp_sel; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), // No fallthrough for one cycle delay before ready on AXI. - .DEPTH ( MaxRequests ), - .dtype ( logic ) + cc_fifo #( + .FallThrough ( 1'b0 ), // No fallthrough for one cycle delay before ready on AXI. + .Depth ( MaxRequests ), + .data_t ( logic ) ) i_fifo_rsp_mux ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( fifo_full ), .empty_o ( fifo_empty ), .usage_o ( /*not used*/ ), @@ -235,7 +235,7 @@ module axi_lite_from_mem #( assert (DataWidth == $bits(axi_rsp_i.r.data)) else $fatal(1, "DataWidth has to match axi_rsp_i.r.data!"); end - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); assert property (@(posedge clk_i) (mem_req_i && !mem_gnt_o) |=> mem_req_i) else $fatal(1, "It is not allowed to deassert the request if it was not granted!"); diff --git a/src/axi_lite_lfsr.sv b/src/axi_lite_lfsr.sv index 7d4710d5f..e557257e2 100644 --- a/src/axi_lite_lfsr.sv +++ b/src/axi_lite_lfsr.sv @@ -27,8 +27,6 @@ module axi_lite_lfsr #( input logic clk_i, /// Active-low reset input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4 Lite request struct input axi_lite_req_t req_i, /// AXI4 Lite response struct @@ -93,14 +91,14 @@ module axi_lite_lfsr #( end // B - stream_fifo #( - .FALL_THROUGH ( 1'b0 ), - .DATA_WIDTH ( 'd1 ), - .DEPTH ( 'd2 ) + cc_stream_fifo #( + .FallThrough ( 1'b0 ), + .DataWidth ( 'd1 ), + .Depth ( 'd2 ) ) i_stream_fifo_w_b ( .clk_i, .rst_ni, - .testmode_i, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), .usage_o ( /* NOT CONNECTED */ ), .data_i ( 1'b0 ), @@ -156,7 +154,7 @@ module axi_opt_lfsr #( ); /// Number of bits required to hold the LFSR tab configuration - localparam int unsigned LfsrIdxWidth = cf_math_pkg::idx_width(Width); + localparam int unsigned LfsrIdxWidth = cc_pkg::idx_width(Width); /// Maximum number of tabs localparam int unsigned MaxNumTabs = 4; diff --git a/src/axi_lite_mailbox.sv b/src/axi_lite_mailbox.sv index 13d0785c6..4877e601d 100644 --- a/src/axi_lite_mailbox.sv +++ b/src/axi_lite_mailbox.sv @@ -31,7 +31,6 @@ module axi_lite_mailbox #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave ports [1:0] input req_lite_t [1:0] slv_reqs_i, output resp_lite_t [1:0] slv_resps_o, @@ -120,46 +119,41 @@ module axi_lite_mailbox #( .clear_irq_o ( clear_irq[1] ) ); - // the usage gets concatinated with the full flag to have consistent threshold detection - logic [FifoUsageWidth-1:0] mbox_0_to_1_usage, mbox_1_to_0_usage; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MailboxDepth ), - .dtype ( data_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MailboxDepth ), + .data_t ( data_t ) ) i_mbox_0_to_1 ( .clk_i, .rst_ni, - .testmode_i( test_i ), + .clr_i ( 1'b0 ), .flush_i ( w_mbox_flush[0] | r_mbox_flush[1] ), .full_o ( mbox_full[0] ), .empty_o ( mbox_empty[0] ), - .usage_o ( mbox_0_to_1_usage ), + .usage_o ( mbox_usage[0] ), .data_i ( mbox_w_data[0] ), .push_i ( mbox_push[0] ), .data_o ( mbox_r_data[1] ), .pop_i ( mbox_pop[1] ) ); - // assign the MSB of the FIFO to the correct usage signal - assign mbox_usage[0] = {mbox_full[0], mbox_0_to_1_usage}; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MailboxDepth ), - .dtype ( data_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MailboxDepth ), + .data_t ( data_t ) ) i_mbox_1_to_0 ( .clk_i, .rst_ni, - .testmode_i( test_i ), + .clr_i ( 1'b0 ), .flush_i ( w_mbox_flush[1] | r_mbox_flush[0] ), .full_o ( mbox_full[1] ), .empty_o ( mbox_empty[1] ), - .usage_o ( mbox_1_to_0_usage ), + .usage_o ( mbox_usage[1] ), .data_i ( mbox_w_data[1] ), .push_i ( mbox_push[1] ), .data_o ( mbox_r_data[0] ), .pop_i ( mbox_pop[0] ) ); - assign mbox_usage[1] = {mbox_full[1], mbox_1_to_0_usage}; for (genvar i = 0; i < 2; i++) begin : gen_irq_conversion if (IrqEdgeTrig) begin : gen_irq_edge @@ -181,7 +175,7 @@ module axi_lite_mailbox #( end end - `FFLARN(irq_q, irq_d, update_irq, '0, clk_i, rst_ni) + `FFL(irq_q, irq_d, update_irq, '0, clk_i, rst_ni) end else begin : gen_irq_level assign irq_o[i] = (IrqActHigh) ? slv_irq[i] : ~slv_irq[i]; end @@ -191,6 +185,8 @@ module axi_lite_mailbox #( `ifndef VERILATOR initial begin : proc_check_params mailbox_depth: assert (MailboxDepth > 1) else $fatal(1, "MailboxDepth has to be at least 2"); + mailbox_depth_pow2: assert ((MailboxDepth & (MailboxDepth - 1)) == 0) + else $fatal(1, "MailboxDepth has to be a power of two (usage_t sizing relies on it)."); axi_addr_width: assert (AxiAddrWidth > 0) else $fatal(1, "AxiAddrWidth has to be > 0"); axi_data_width: assert (AxiDataWidth > 0) else $fatal(1, "AxiDataWidth has to be > 0"); end @@ -292,11 +288,11 @@ module axi_lite_mailbox_slave #( logic update_regs; // register enable signal // register instantiation - `FFLARN(error_q, error_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(wirqt_q, wirqt_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(rirqt_q, rirqt_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(irqs_q, irqs_d, update_regs, '0, clk_i, rst_ni) - `FFLARN(irqen_q, irqen_d, update_regs, '0, clk_i, rst_ni) + `FFL(error_q, error_d, update_regs, '0, clk_i, rst_ni) + `FFL(wirqt_q, wirqt_d, update_regs, '0, clk_i, rst_ni) + `FFL(rirqt_q, rirqt_d, update_regs, '0, clk_i, rst_ni) + `FFL(irqs_q, irqs_d, update_regs, '0, clk_i, rst_ni) + `FFL(irqen_q, irqen_d, update_regs, '0, clk_i, rst_ni) // Mailbox FIFO data assignments for (genvar i = 0; i < (AxiDataWidth/8); i++) begin : gen_w_mbox_data @@ -489,7 +485,7 @@ module axi_lite_mailbox_slave #( // address decoder and response FIFOs for the LITE channel, the port can take a new transaction if // these FIFOs are not full, not fall through to prevent combinational paths to the return path - addr_decode #( + cc_addr_decode #( .NoIndices( NoRegs ), .NoRules ( NoRegs ), .addr_t ( addr_t ), @@ -503,11 +499,12 @@ module axi_lite_mailbox_slave #( .en_default_idx_i ( 1'b0 ), .default_idx_i ( '0 ) ); - spill_register #( - .T ( b_chan_lite_t ) + cc_spill_register #( + .data_t ( b_chan_lite_t ) ) i_b_chan_outp ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( b_valid ), .ready_o ( b_ready ), .data_i ( b_chan ), @@ -515,7 +512,7 @@ module axi_lite_mailbox_slave #( .ready_i ( slv_req_i.b_ready ), .data_o ( slv_resp_o.b ) ); - addr_decode #( + cc_addr_decode #( .NoIndices( NoRegs ), .NoRules ( NoRegs ), .addr_t ( addr_t ), @@ -529,11 +526,12 @@ module axi_lite_mailbox_slave #( .en_default_idx_i ( 1'b0 ), .default_idx_i ( '0 ) ); - spill_register #( - .T ( r_chan_lite_t ) + cc_spill_register #( + .data_t ( r_chan_lite_t ) ) i_r_chan_outp ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( r_valid ), .ready_o ( r_ready ), .data_i ( r_chan ), @@ -566,7 +564,6 @@ module axi_lite_mailbox_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable AXI_LITE.Slave slv [1:0], // slave ports [1:0] output logic [1:0] irq_o, // interrupt output for each port input addr_t [1:0] base_addr_i // base address for each port @@ -600,7 +597,6 @@ module axi_lite_mailbox_intf #( ) i_axi_lite_mailbox ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable // slave ports [1:0] .slv_reqs_i ( slv_reqs ), .slv_resps_o ( slv_resps ), diff --git a/src/axi_lite_mux.sv b/src/axi_lite_mux.sv index 26f97b589..a6820555f 100644 --- a/src/axi_lite_mux.sv +++ b/src/axi_lite_mux.sv @@ -44,7 +44,6 @@ module axi_lite_mux #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable // slave ports (AXI4-Lite inputs), connect master modules here input axi_req_t [NoSlvPorts-1:0] slv_reqs_i, output axi_resp_t [NoSlvPorts-1:0] slv_resps_o, @@ -54,12 +53,13 @@ module axi_lite_mux #( ); // pass through if only one slave port if (NoSlvPorts == 32'h1) begin : gen_no_mux - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].aw_valid ), .ready_o ( slv_resps_o[0].aw_ready ), .data_i ( slv_reqs_i[0].aw ), @@ -67,12 +67,13 @@ module axi_lite_mux #( .ready_i ( mst_resp_i.aw_ready ), .data_o ( mst_req_o.aw ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].w_valid ), .ready_o ( slv_resps_o[0].w_ready ), .data_i ( slv_reqs_i[0].w ), @@ -80,12 +81,13 @@ module axi_lite_mux #( .ready_i ( mst_resp_i.w_ready ), .data_o ( mst_req_o.w ) ); - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -93,12 +95,13 @@ module axi_lite_mux #( .ready_i ( slv_reqs_i[0].b_ready ), .data_o ( slv_resps_o[0].b ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( slv_reqs_i[0].ar_valid ), .ready_o ( slv_resps_o[0].ar_ready ), .data_i ( slv_reqs_i[0].ar ), @@ -106,12 +109,13 @@ module axi_lite_mux #( .ready_i ( mst_resp_i.ar_ready ), .data_o ( mst_req_o.ar ) ); - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), @@ -196,15 +200,15 @@ module axi_lite_mux #( assign slv_aw_valids[i] = slv_reqs_i[i].aw_valid; assign slv_resps_o[i].aw_ready = slv_aw_readies[i]; end - rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( aw_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + cc_rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .data_t ( aw_chan_t ), + .AxiVldRdy ( 1'b1 ), + .LockIn ( 1'b1 ) ) i_aw_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( slv_aw_valids ), .gnt_o ( slv_aw_readies ), @@ -247,17 +251,17 @@ module axi_lite_mux #( end end - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_w_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( w_fifo_full ), .empty_o ( w_fifo_empty ), .usage_o ( ), @@ -267,12 +271,13 @@ module axi_lite_mux #( .pop_i ( w_fifo_pop ) ); - spill_register #( - .T ( aw_chan_t ), + cc_spill_register #( + .data_t ( aw_chan_t ), .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg ) i_aw_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_aw_valid ), .ready_o ( mst_aw_ready ), .data_i ( mst_aw_chan ), @@ -293,15 +298,15 @@ module axi_lite_mux #( end assign w_fifo_pop = mst_w_valid & mst_w_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_b_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( b_fifo_full ), .empty_o ( b_fifo_empty ), .usage_o ( ), @@ -311,12 +316,13 @@ module axi_lite_mux #( .pop_i ( b_fifo_pop ) ); - spill_register #( - .T ( w_chan_t ), + cc_spill_register #( + .data_t ( w_chan_t ), .Bypass ( ~SpillW ) ) i_w_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_w_valid ), .ready_o ( mst_w_ready ), .data_i ( mst_w_chan ), @@ -336,12 +342,13 @@ module axi_lite_mux #( assign mst_b_ready = ~b_fifo_empty & slv_reqs_i[b_select].b_ready; assign b_fifo_pop = mst_b_valid & mst_b_ready; - spill_register #( - .T ( b_chan_t ), + cc_spill_register #( + .data_t ( b_chan_t ), .Bypass ( ~SpillB ) ) i_b_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.b_valid ), .ready_o ( mst_req_o.b_ready ), .data_i ( mst_resp_i.b ), @@ -359,15 +366,15 @@ module axi_lite_mux #( assign slv_ar_valids[i] = slv_reqs_i[i].ar_valid; assign slv_resps_o[i].ar_ready = slv_ar_readies[i]; end - rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( ar_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + cc_rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .data_t ( ar_chan_t ), + .AxiVldRdy ( 1'b1 ), + .LockIn ( 1'b1 ) ) i_ar_arbiter ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( slv_ar_valids ), .gnt_o ( slv_ar_readies ), @@ -384,15 +391,15 @@ module axi_lite_mux #( assign ar_ready = (!r_fifo_full) ? mst_ar_ready : 1'b0; assign r_fifo_push = mst_ar_valid & mst_ar_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxTrans ), - .dtype ( select_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxTrans ), + .data_t ( select_t ) ) i_r_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( r_fifo_full ), .empty_o ( r_fifo_empty ), .usage_o ( ), @@ -402,12 +409,13 @@ module axi_lite_mux #( .pop_i ( r_fifo_pop ) ); - spill_register #( - .T ( ar_chan_t ), + cc_spill_register #( + .data_t ( ar_chan_t ), .Bypass ( ~SpillAr ) ) i_ar_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_ar_valid ), .ready_o ( mst_ar_ready ), .data_i ( mst_ar_chan ), @@ -427,12 +435,13 @@ module axi_lite_mux #( assign mst_r_ready = ~r_fifo_empty & slv_reqs_i[r_select].r_ready; assign r_fifo_pop = mst_r_valid & mst_r_ready; - spill_register #( - .T ( r_chan_t ), + cc_spill_register #( + .data_t ( r_chan_t ), .Bypass ( ~SpillR ) ) i_r_spill_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .valid_i ( mst_resp_i.r_valid ), .ready_o ( mst_req_o.r_ready ), .data_i ( mst_resp_i.r ), @@ -474,7 +483,6 @@ module axi_lite_mux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable AXI_LITE.Slave slv [NoSlvPorts-1:0], // slave ports AXI_LITE.Master mst // master port ); @@ -523,7 +531,6 @@ module axi_lite_mux_intf #( ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable .slv_reqs_i ( slv_reqs ), .slv_resps_o ( slv_resps ), .mst_req_o ( mst_req ), diff --git a/src/axi_lite_regs.sv b/src/axi_lite_regs.sv index 392bd17f1..a6d294f73 100644 --- a/src/axi_lite_regs.sv +++ b/src/axi_lite_regs.sv @@ -141,7 +141,7 @@ module axi_lite_regs #( // Reg byte: B A 9 8 7 6 5 4 3 2 1 0 // | chunk_2 | chunk_1 | chunk_0 | localparam int unsigned AxiStrbWidth = AxiDataWidth / 32'd8; - localparam int unsigned NumChunks = cf_math_pkg::ceil_div(RegNumBytes, AxiStrbWidth); + localparam int unsigned NumChunks = cc_pkg::ceil_div(RegNumBytes, AxiStrbWidth); localparam int unsigned ChunkIdxWidth = (NumChunks > 32'd1) ? $clog2(NumChunks) : 32'd1; // Type of the index to identify a specific register chunk. typedef logic [ChunkIdxWidth-1:0] chunk_idx_t; @@ -313,11 +313,11 @@ module axi_lite_regs #( // Register array mapping, even read only register can be loaded over `reg_load_i`. for (genvar i = 0; i < RegNumBytes; i++) begin : gen_rw_regs - `FFLARN(reg_q[i], reg_d[i], reg_update[i], RegRstVal[i], clk_i, rst_ni) + `FFL(reg_q[i], reg_d[i], reg_update[i], RegRstVal[i], clk_i, rst_ni) assign reg_q_o[i] = reg_q[i]; end - addr_decode #( + cc_addr_decode #( .NoIndices ( NumChunks ), .NoRules ( NumChunks ), .addr_t ( addr_t ), @@ -332,7 +332,7 @@ module axi_lite_regs #( .default_idx_i ( '0 ) ); - addr_decode #( + cc_addr_decode #( .NoIndices ( NumChunks ), .NoRules ( NumChunks ), .addr_t ( addr_t ), @@ -348,12 +348,13 @@ module axi_lite_regs #( ); // Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs. - spill_register #( - .T ( b_chan_lite_t ), + cc_spill_register #( + .data_t ( b_chan_lite_t ), .Bypass ( 1'b0 ) ) i_b_spill_register ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( b_valid ), .ready_o ( b_ready ), .data_i ( b_chan ), @@ -363,12 +364,13 @@ module axi_lite_regs #( ); // Add a cycle delay on AXI response, cut all comb paths between slave port inputs and outputs. - spill_register #( - .T ( r_chan_lite_t ), + cc_spill_register #( + .data_t ( r_chan_lite_t ), .Bypass ( 1'b0 ) ) i_r_spill_register ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( r_valid ), .ready_o ( r_ready ), .data_i ( r_chan ), @@ -380,7 +382,7 @@ module axi_lite_regs #( // Validate parameters. // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin: p_assertions assert (RegNumBytes > 32'd0) else $fatal(1, "The number of bytes must be at least 1!"); diff --git a/src/axi_lite_to_apb.sv b/src/axi_lite_to_apb.sv index 4d58d0c4a..b35d5e0fe 100644 --- a/src/axi_lite_to_apb.sv +++ b/src/axi_lite_to_apb.sv @@ -146,16 +146,16 @@ module axi_lite_to_apb #( int_resp_t apb_rresp; logic apb_rresp_valid, apb_rresp_ready; - rr_arb_tree #( - .NumIn ( 32'd2 ), - .DataType ( int_req_t ), - .ExtPrio ( 1'b0 ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) + cc_rr_arb_tree #( + .NumIn ( 32'd2 ), + .data_t ( int_req_t ), + .ExtPrio ( 1'b0 ), + .AxiVldRdy ( 1'b1 ), + .LockIn ( 1'b1 ) ) i_req_arb ( .clk_i, .rst_ni, - .flush_i ( '0 ), + .clr_i ( '0 ), .rr_i ( '0 ), .req_i ( axi_req_valid ), .gnt_o ( axi_req_ready ), @@ -167,12 +167,13 @@ module axi_lite_to_apb #( ); if (PipelineRequest) begin : gen_req_spill - spill_register #( - .T ( int_req_t ), + cc_spill_register #( + .data_t ( int_req_t ), .Bypass ( 1'b0 ) ) i_req_spill ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( arb_req_valid ), .ready_o ( arb_req_ready ), .data_i ( arb_req ), @@ -181,13 +182,12 @@ module axi_lite_to_apb #( .data_o ( apb_req ) ); end else begin : gen_req_ft_reg - fall_through_register #( - .T ( int_req_t ) + cc_fall_through_register #( + .data_t ( int_req_t ) ) i_req_ft_reg ( .clk_i, .rst_ni, .clr_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .valid_i ( arb_req_valid ), .ready_o ( arb_req_ready ), .data_i ( arb_req ), @@ -198,12 +198,13 @@ module axi_lite_to_apb #( end if (PipelineResponse) begin : gen_resp_spill - spill_register #( - .T ( axi_pkg::resp_t ), + cc_spill_register #( + .data_t ( axi_pkg::resp_t ), .Bypass ( 1'b0 ) ) i_write_resp_spill ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( apb_wresp_valid ), .ready_o ( apb_wresp_ready ), .data_i ( apb_wresp ), @@ -211,12 +212,13 @@ module axi_lite_to_apb #( .ready_i ( axi_lite_req_i.b_ready ), .data_o ( axi_bresp ) ); - spill_register #( - .T ( int_resp_t ), + cc_spill_register #( + .data_t ( int_resp_t ), .Bypass ( 1'b0 ) ) i_read_resp_spill ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( apb_rresp_valid ), .ready_o ( apb_rresp_ready ), .data_i ( apb_rresp ), @@ -225,13 +227,12 @@ module axi_lite_to_apb #( .data_o ( axi_rresp ) ); end else begin : gen_resp_ft_reg - fall_through_register #( - .T ( axi_pkg::resp_t ) + cc_fall_through_register #( + .data_t ( axi_pkg::resp_t ) ) i_write_resp_ft_reg ( .clk_i, .rst_ni, .clr_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .valid_i ( apb_wresp_valid ), .ready_o ( apb_wresp_ready ), .data_i ( apb_wresp ), @@ -239,13 +240,12 @@ module axi_lite_to_apb #( .ready_i ( axi_lite_req_i.b_ready ), .data_o ( axi_bresp ) ); - fall_through_register #( - .T ( int_resp_t ) + cc_fall_through_register #( + .data_t ( int_resp_t ) ) i_read_resp_ft_reg ( .clk_i, .rst_ni, .clr_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .valid_i ( apb_rresp_valid ), .ready_o ( apb_rresp_ready ), .data_i ( apb_rresp ), @@ -264,7 +264,7 @@ module axi_lite_to_apb #( // output of address decoder to determine PSELx signal logic apb_dec_valid; sel_idx_t apb_sel_idx; - addr_decode #( + cc_addr_decode #( .NoIndices( NoApbSlaves ), .NoRules ( NoRules ), .addr_t ( addr_t ), @@ -360,7 +360,7 @@ module axi_lite_to_apb #( endcase end - `FFLARN(apb_state_q, apb_state_d, apb_update, Setup, clk_i, rst_ni) + `FFL(apb_state_q, apb_state_d, apb_update, Setup, clk_i, rst_ni) // parameter check // pragma translate_off @@ -451,11 +451,11 @@ module axi_lite_to_apb_intf #( `AXI_LITE_ASSIGN_TO_REQ(axi_req, slv) `AXI_LITE_ASSIGN_FROM_RESP(slv, axi_resp) - onehot_to_bin #( - .ONEHOT_WIDTH ( NoApbSlaves ) + cc_onehot_to_bin #( + .OnehotWidth ( NoApbSlaves ) ) i_onehot_to_bin ( - .onehot ( pselx_o ), - .bin ( apb_sel ) + .onehot_i ( pselx_o ), + .bin_o ( apb_sel ) ); assign paddr_o = apb_req[apb_sel].paddr; diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv index 72d1e0356..7ce9d5bfa 100644 --- a/src/axi_lite_xbar.sv +++ b/src/axi_lite_xbar.sv @@ -34,7 +34,6 @@ module axi_lite_xbar #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, input axi_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, output axi_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, output axi_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, @@ -76,7 +75,7 @@ module axi_lite_xbar #( full_req_t decerr_req; full_resp_t decerr_resp; - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .NoRules ( Cfg.NoAddrRules ), .addr_t ( addr_t ), @@ -91,7 +90,7 @@ module axi_lite_xbar #( .default_idx_i ( default_mst_port_i[i] ) ); - addr_decode #( + cc_addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NoAddrRules ), @@ -114,7 +113,7 @@ module axi_lite_xbar #( // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -158,7 +157,6 @@ module axi_lite_xbar #( ) i_axi_lite_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable .slv_req_i ( slv_ports_req_i[i] ), .slv_aw_select_i ( slv_aw_select ), .slv_ar_select_i ( slv_ar_select ), @@ -195,7 +193,6 @@ module axi_lite_xbar #( ) i_axi_err_slv ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low - .test_i ( test_i ), // Testmode enable // slave port .slv_req_i ( decerr_req ), .slv_resp_o ( decerr_resp ) @@ -230,7 +227,6 @@ module axi_lite_xbar #( ) i_axi_lite_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable .slv_reqs_i ( mst_reqs[i] ), .slv_resps_o ( mst_resps[i] ), .mst_req_o ( mst_ports_req_o[i] ), @@ -247,7 +243,6 @@ module axi_lite_xbar_intf #( ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_LITE.Slave slv_ports [Cfg.NoSlvPorts-1:0], AXI_LITE.Master mst_ports [Cfg.NoMstPorts-1:0], input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, @@ -294,7 +289,6 @@ module axi_lite_xbar_intf #( ) i_xbar ( .clk_i, .rst_ni, - .test_i, .slv_ports_req_i (slv_reqs ), .slv_ports_resp_o (slv_resps), .mst_ports_req_o (mst_reqs ), diff --git a/src/axi_mcast_demux_mapped.sv b/src/axi_mcast_demux_mapped.sv new file mode 100644 index 000000000..718c9e1a5 --- /dev/null +++ b/src/axi_mcast_demux_mapped.sv @@ -0,0 +1,547 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Michael Rogenmoser +// - Wolfgang Roenninger +// - Thomas Benz +// - Andreas Kurth +// - Luca Colagrande + +`include "common_cells/assertions.svh" +`include "common_cells/registers.svh" + +`ifdef QUESTA +// Derive `TARGET_VSIM`, which is used for tool-specific workarounds in this file, from `QUESTA`, +// which is automatically set in Questa. +`define TARGET_VSIM +`endif + +/// Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports. +/// +/// The module internally decodes Ax requests, determining the master port route based on the +/// address of the request. To this end an address map, and additional inputs required by the +/// address decoding modules, are provided. +/// +/// ## Design overview +/// +/// ![Block diagram](module.axi_demux.png "Block diagram") +/// +/// Beats on the W channel are routed by demultiplexer according to the selection for the +/// corresponding AW beat. This relies on the AXI property that W bursts must be sent in the same +/// order as AW beats and beats from different W bursts may not be interleaved. +/// +/// Beats on the B and R channel are multiplexed from the master ports to the slave port with +/// a round-robin arbitration tree. +module axi_mcast_demux_mapped #( + parameter int unsigned AxiIdWidth = 32'd0, + parameter int unsigned AxiAddrWidth = 32'd0, + parameter bit AtopSupport = 1'b1, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned MaxTrans = 32'd8, + parameter int unsigned AxiLookBits = 32'd3, + parameter bit UniqueIds = 1'b0, + parameter bit SpillAw = 1'b1, + parameter bit SpillW = 1'b0, + parameter bit SpillB = 1'b0, + parameter bit SpillAr = 1'b1, + parameter bit SpillR = 1'b0, + parameter bit [NoMstPorts-1:0] Connectivity = '1, + parameter bit [NoMstPorts-1:0] MulticastConnectivity = '1, + parameter type rule_t = logic, + parameter int unsigned NoAddrRules = 32'd0, + parameter int unsigned NoMulticastRules = 32'd0, + parameter int unsigned NoMulticastPorts = 32'd0, + parameter int unsigned MaxMcastTrans = 32'd7 +) ( + input logic clk_i, + input logic rst_ni, + // Addressing rules + input rule_t [NoAddrRules-1:0] addr_map_i, + input logic en_default_mst_port_i, + input rule_t default_mst_port_i, + // Slave Port + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + // Master Ports + output axi_req_t [NoMstPorts-1:0] mst_reqs_o, + input axi_resp_t [NoMstPorts-1:0] mst_resps_i, + output logic [NoMstPorts-1:0] mst_is_mcast_o, + output logic [NoMstPorts-1:0] mst_aw_commit_o +); + + // Account for additional error slave + localparam int unsigned NoMstPortsExt = NoMstPorts + 1; + + localparam int unsigned IdxSelectWidth = cc_pkg::idx_width(NoMstPorts); + localparam int unsigned IdxSelectWidthExt = cc_pkg::idx_width(NoMstPortsExt); + typedef logic [IdxSelectWidth-1:0] idx_select_t; + typedef logic [IdxSelectWidthExt-1:0] idx_select_ext_t; + + typedef logic [NoMstPortsExt-1:0] mask_select_t; + + typedef logic [AxiAddrWidth-1:0] addr_t; + + typedef struct packed { + int unsigned idx; + addr_t addr; + addr_t mask; + } mask_rule_t; + + // ---------------- + // Spill registers + // ---------------- + + axi_req_t slv_req_cut; + axi_resp_t slv_resp_cut; + + cc_spill_register #( + .data_t ( aw_chan_t ), + .Bypass ( ~SpillAw ) + ) i_aw_spill_reg ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .valid_i ( slv_req_i.aw_valid ), + .ready_o ( slv_resp_o.aw_ready ), + .data_i ( slv_req_i.aw ), + .valid_o ( slv_req_cut.aw_valid ), + .ready_i ( slv_resp_cut.aw_ready ), + .data_o ( slv_req_cut.aw ) + ); + cc_spill_register #( + .data_t ( w_chan_t ), + .Bypass ( ~SpillW ) + ) i_w_spill_reg ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .valid_i ( slv_req_i.w_valid ), + .ready_o ( slv_resp_o.w_ready ), + .data_i ( slv_req_i.w ), + .valid_o ( slv_req_cut.w_valid ), + .ready_i ( slv_resp_cut.w_ready ), + .data_o ( slv_req_cut.w ) + ); + cc_spill_register #( + .data_t ( ar_chan_t ), + .Bypass ( ~SpillAr ) + ) i_ar_spill_reg ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .valid_i ( slv_req_i.ar_valid ), + .ready_o ( slv_resp_o.ar_ready ), + .data_i ( slv_req_i.ar ), + .valid_o ( slv_req_cut.ar_valid ), + .ready_i ( slv_resp_cut.ar_ready ), + .data_o ( slv_req_cut.ar ) + ); + cc_spill_register #( + .data_t ( b_chan_t ), + .Bypass ( ~SpillB ) + ) i_b_spill_reg ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .valid_i ( slv_resp_cut.b_valid ), + .ready_o ( slv_req_cut.b_ready ), + .data_i ( slv_resp_cut.b ), + .valid_o ( slv_resp_o.b_valid ), + .ready_i ( slv_req_i.b_ready ), + .data_o ( slv_resp_o.b ) + ); + cc_spill_register #( + .data_t ( r_chan_t ), + .Bypass ( ~SpillR ) + ) i_r_spill_reg ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .valid_i ( slv_resp_cut.r_valid ), + .ready_o ( slv_req_cut.r_ready ), + .data_i ( slv_resp_cut.r ), + .valid_o ( slv_resp_o.r_valid ), + .ready_i ( slv_req_i.r_ready ), + .data_o ( slv_resp_o.r ) + ); + + // ----------------- + // AR address decoding + // ----------------- + + idx_select_t dec_ar_select_idx; + logic dec_ar_error; + idx_select_ext_t ar_select_idx; + + // Address decoding for unicast requests + cc_addr_decode #( + .NoIndices (NoMstPorts), + .NoRules (NoAddrRules), + .addr_t (addr_t), + .rule_t (rule_t) + ) i_axi_ar_decode ( + .addr_i (slv_req_cut.ar.addr), + .addr_map_i (addr_map_i), + .idx_o (dec_ar_select_idx), + .dec_valid_o (), + .dec_error_o (dec_ar_error), + .en_default_idx_i (en_default_mst_port_i), + .default_idx_i (idx_select_t'(default_mst_port_i.idx)) + ); + + assign ar_select_idx = dec_ar_error ? NoMstPorts : idx_select_ext_t'(dec_ar_select_idx); + + // ----------------- + // AW address decoding + // ----------------- + + // AW decoder inputs + mask_rule_t [axi_pkg::iomsb(NoMulticastRules):0] multicast_rules; + mask_rule_t default_rule; + + // AW unicast decoder outputs + idx_select_t dec_aw_unicast_select_idx; + logic [NoMstPorts-1:0] dec_aw_unicast_select_mask; + logic dec_aw_unicast_valid; + logic dec_aw_unicast_error; + + // AW multicast decoder outputs + logic [axi_pkg::iomsb(NoMulticastPorts):0] dec_aw_multicast_select_mask; + addr_t [axi_pkg::iomsb(NoMulticastPorts):0] dec_aw_multicast_addr; + addr_t [axi_pkg::iomsb(NoMulticastPorts):0] dec_aw_multicast_mask; + logic dec_aw_multicast_valid; + logic dec_aw_multicast_error; + + // Decoding outputs (merged from unicast and multicast paths) + mask_select_t dec_aw_select_mask; + addr_t [NoMstPortsExt-1:0] dec_aw_addr; + addr_t [NoMstPortsExt-1:0] dec_aw_mask; + + // Address decoding for unicast requests + cc_addr_decode #( + .NoIndices (NoMstPorts), + .NoRules (NoAddrRules), + .addr_t (addr_t), + .rule_t (rule_t) + ) i_axi_aw_unicast_decode ( + .addr_i (slv_req_cut.aw.addr), + .addr_map_i (addr_map_i), + .idx_o (dec_aw_unicast_select_idx), + .dec_valid_o (dec_aw_unicast_valid), + .dec_error_o (dec_aw_unicast_error), + .en_default_idx_i (en_default_mst_port_i), + .default_idx_i (idx_select_t'(default_mst_port_i.idx)) + ); + + // Generate the output mask from the index + assign dec_aw_unicast_select_mask = 1'b1 << dec_aw_unicast_select_idx; + + // If the address decoding doesn't produce any match, the request + // is routed to the error slave, which lies at the highest index. + mask_select_t select_error_slave; + assign select_error_slave = 1'b1 << NoMstPorts; + + // Disable multicast only if NoMulticastPorts == 0. In some instances you may want to + // match the multicast decoder's default port, even if NoMulticastRules == 0. + if (NoMulticastPorts > 0) begin : gen_multicast + + // Convert multicast rules to mask (NAPOT) form, see https://arxiv.org/pdf/2502.19215 + for (genvar i = 0; i < NoMulticastRules; i++) begin : gen_multicast_rules + assign multicast_rules[i].idx = addr_map_i[i].idx; + assign multicast_rules[i].mask = addr_map_i[i].end_addr - addr_map_i[i].start_addr - 1; + assign multicast_rules[i].addr = addr_map_i[i].start_addr; + end + assign default_rule.idx = default_mst_port_i.idx; + assign default_rule.mask = default_mst_port_i.end_addr - default_mst_port_i.start_addr - 1; + assign default_rule.addr = default_mst_port_i.start_addr; + + if (NoMulticastRules > 0) begin : gen_multiaddr_decode + // Address decoding for multicast requests. + cc_multiaddr_decode #( + .NoIndices (NoMulticastPorts), + .NoRules (NoMulticastRules), + .addr_t (addr_t), + .rule_t (mask_rule_t) + ) i_axi_aw_multicast_decode ( + .addr_map_i (multicast_rules), + .addr_i (slv_req_cut.aw.addr), + .mask_i (slv_req_cut.aw.user.collective_mask), + .select_o (dec_aw_multicast_select_mask), + .addr_o (dec_aw_multicast_addr), + .mask_o (dec_aw_multicast_mask), + .dec_valid_o (dec_aw_multicast_valid), + .dec_error_o (dec_aw_multicast_error), + .en_default_idx_i (en_default_mst_port_i), + .default_idx_i (default_rule) + ); + end else begin : gen_no_multiaddr_decode + assign dec_aw_multicast_select_mask = 1'b1 << default_rule.idx; + assign dec_aw_multicast_addr = slv_req_cut.aw.addr; + assign dec_aw_multicast_mask = slv_req_cut.aw.user.collective_mask; + assign dec_aw_multicast_valid = 1'b1; + assign dec_aw_multicast_error = 1'b0; + end + + // Mux the multicast and unicast decoding outputs. + always_comb begin + dec_aw_select_mask = '0; + dec_aw_addr = '0; + dec_aw_mask = '0; + + if (slv_req_cut.aw.user.collective_mask == '0) begin + dec_aw_addr = {'0, {NoMstPorts{slv_req_cut.aw.addr}}}; + if (dec_aw_unicast_error) begin + dec_aw_select_mask = select_error_slave; + end else begin + dec_aw_select_mask = dec_aw_unicast_select_mask & Connectivity; + end + end else begin + dec_aw_addr = {'0, {(NoMstPorts-NoMulticastPorts){slv_req_cut.aw.addr}}, dec_aw_multicast_addr}; + dec_aw_mask = {'0, dec_aw_multicast_mask}; + if (dec_aw_multicast_error) begin + dec_aw_select_mask = select_error_slave; + end else begin + dec_aw_select_mask = {'0, dec_aw_multicast_select_mask} & MulticastConnectivity; + end + end + end + + end else begin : gen_no_multicast + assign dec_aw_addr = {'0, {NoMstPorts{slv_req_cut.aw.addr}}}; + assign dec_aw_mask = '0; + assign dec_aw_select_mask = (dec_aw_unicast_error) ? select_error_slave : + (dec_aw_unicast_select_mask & Connectivity); + end + + // ----------------- + // Demux + // ----------------- + + axi_req_t errslv_req; + axi_resp_t errslv_resp; + logic errslv_is_mcast; + logic errslv_aw_commit; + + axi_mcast_demux_simple #( + .AxiIdWidth ( AxiIdWidth ), + .AtopSupport ( AtopSupport ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .NoMstPorts ( NoMstPortsExt ), + .MaxTrans ( MaxTrans ), + .AxiLookBits ( AxiLookBits ), + .UniqueIds ( UniqueIds ), + .aw_addr_t ( addr_t ), + .NoMulticastPorts ( NoMulticastPorts ), + .MaxMcastTrans ( MaxMcastTrans ) + ) i_mcast_demux_simple ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req_cut ), + .slv_aw_select_i ( dec_aw_select_mask ), + .slv_aw_addr_i ( dec_aw_addr ), + .slv_aw_mask_i ( dec_aw_mask ), + .slv_ar_select_i ( ar_select_idx ), + .slv_resp_o ( slv_resp_cut ), + .mst_reqs_o ( {errslv_req, mst_reqs_o} ), + .mst_resps_i ( {errslv_resp, mst_resps_i} ), + .mst_is_mcast_o ( {errslv_is_mcast, mst_is_mcast_o} ), + .mst_aw_commit_o ( {errslv_aw_commit, mst_aw_commit_o} ) + ); + + axi_err_slv #( + .AxiIdWidth ( AxiIdWidth ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .Resp ( axi_pkg::RESP_DECERR ), + .ATOPs ( AtopSupport ), + // Transactions terminate at this slave, so minimize resource consumption by accepting + // only a few transactions at a time. + .MaxTrans ( 4 ) + ) i_axi_err_slv ( + .clk_i, + .rst_ni, + .slv_req_i ( errslv_req ), + .slv_resp_o ( errslv_resp ) + ); + + // ----------------- + // Assertions + // ----------------- + +// pragma translate_off +`ifndef VERILATOR +`ifndef XSIM + + // Check that multicast address map rules expressed in interval form can be converted to + // mask form, see https://arxiv.org/pdf/2502.19215 + for (genvar i = 0; i < NoMulticastRules; i++) begin : gen_multicast_rule_assertion + addr_t size; + assign size = addr_map_i[i].end_addr - addr_map_i[i].start_addr; + `ASSERT(MulticastRuleSize, + ((size & (size - 1)) == 0), clk_i, !rst_ni, + $sformatf("Size %0d of rule %0d is not a power of 2", size, i)) + `ASSERT(MulticastRuleAlignment, + (addr_map_i[i].start_addr % size) == 0, clk_i, !rst_ni, + $sformatf("Rule %0d, starting at 0x%0x, is not aligned to its size (%0d)", + i, addr_map_i[i].start_addr, size)) + end + // Default rule is only converted to mask form if there are any other multicast rules + if (NoMulticastPorts > 0) begin : gen_multicast_default_rule_assertion + addr_t size; + assign size = default_mst_port_i.end_addr - default_mst_port_i.start_addr; + `ASSERT(DefaultRuleSize, + !en_default_mst_port_i || ((size & (size - 1)) == 0), clk_i, !rst_ni, + $sformatf("Size %0d of default rule is not a power of 2", size)) + `ASSERT(DefaultRuleAlignment, + !en_default_mst_port_i || ((default_mst_port_i.start_addr % size) == 0), clk_i, !rst_ni, + $sformatf("Default rule, starting at 0x%0x, is not aligned to its size (%0d)", + default_mst_port_i.start_addr, size)) + end + + // Check that addrmap and default slave do not change while there is an unserved Ax + `ASSERT(default_mst_port_en_aw_stable, + (slv_req_cut.aw_valid && !slv_resp_cut.aw_ready) |=> $stable(en_default_mst_port_i), + clk_i, !rst_ni, + "It is not allowed to change the default mst port enable when there is an unserved Aw beat.") + `ASSERT(default_mst_port_aw_stable, + (slv_req_cut.aw_valid && !slv_resp_cut.aw_ready) |=> $stable(default_mst_port_i), + clk_i, !rst_ni, + "It is not allowed to change the default mst port when there is an unserved Aw beat.") + `ASSERT(addrmap_aw_stable, + (slv_req_cut.aw_valid && !slv_resp_cut.aw_ready) |=> $stable(addr_map_i), + clk_i, !rst_ni, + "It is not allowed to change the address map when there is an unserved Aw beat.") + `ASSERT(default_mst_port_en_ar_stable, + (slv_req_cut.ar_valid && !slv_resp_cut.ar_ready) |=> $stable(en_default_mst_port_i), + clk_i, !rst_ni, + "It is not allowed to change the default mst port enable when there is an unserved Ar beat.") + `ASSERT(default_mst_port_ar_stable, + (slv_req_cut.ar_valid && !slv_resp_cut.ar_ready) |=> $stable(default_mst_port_i), + clk_i, !rst_ni, + "It is not allowed to change the default mst port when there is an unserved Ar beat.") + `ASSERT(addrmap_ar_stable, + (slv_req_cut.ar_valid && !slv_resp_cut.ar_ready) |=> $stable(addr_map_i), + clk_i, !rst_ni, + "It is not allowed to change the address map when there is an unserved Ar beat.") + +`endif +`endif +// pragma translate_on + +endmodule + +// interface wrapper +`include "axi/assign.svh" +`include "axi/typedef.svh" +module axi_mcast_demux_intf #( + parameter int unsigned AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter bit ATOP_SUPPORT = 1'b1, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned NO_MST_PORTS = 32'd3, + parameter int unsigned MAX_TRANS = 32'd8, + parameter int unsigned AXI_LOOK_BITS = 32'd3, + parameter bit UNIQUE_IDS = 1'b0, + parameter bit SPILL_AW = 1'b1, + parameter bit SPILL_W = 1'b0, + parameter bit SPILL_B = 1'b0, + parameter bit SPILL_AR = 1'b1, + parameter bit SPILL_R = 1'b0, + parameter type rule_t = logic, + // Dependent parameters, DO NOT OVERRIDE! + parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1, + parameter type idx_select_t = logic [SELECT_WIDTH-1:0] // MST port select type +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input rule_t [NO_MST_PORTS-2:0] addr_map_i, + input idx_select_t slv_ar_select_i, // has to be stable, when ar_valid + input logic en_default_mst_port_i, + input rule_t default_mst_port_i, + AXI_BUS.Slave slv, // slave port + AXI_BUS.Master mst [NO_MST_PORTS-1:0], // master ports + output logic [NO_MST_PORTS-1:0] mst_is_mcast_o, + output logic [NO_MST_PORTS-1:0] mst_aw_commit_o +); + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t) + + axi_req_t slv_req; + axi_resp_t slv_resp; + axi_req_t [NO_MST_PORTS-1:0] mst_req; + axi_resp_t [NO_MST_PORTS-1:0] mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + + for (genvar i = 0; i < NO_MST_PORTS; i++) begin : gen_assign_mst_ports + `AXI_ASSIGN_FROM_REQ(mst[i], mst_req[i]) + `AXI_ASSIGN_TO_RESP(mst_resp[i], mst[i]) + end + + axi_mcast_demux #( + .AxiIdWidth ( AXI_ID_WIDTH ), // ID Width + .AtopSupport ( ATOP_SUPPORT ), + .aw_addr_t ( addr_t ), // AW Address Type + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .NoMstPorts ( NO_MST_PORTS ), + .MaxTrans ( MAX_TRANS ), + .AxiLookBits ( AXI_LOOK_BITS ), + .UniqueIds ( UNIQUE_IDS ), + .SpillAw ( SPILL_AW ), + .SpillW ( SPILL_W ), + .SpillB ( SPILL_B ), + .SpillAr ( SPILL_AR ), + .SpillR ( SPILL_R ), + .rule_t ( rule_t ) + ) i_axi_demux ( + .clk_i, // Clock + .rst_ni, // Asynchronous reset active low + .addr_map_i ( addr_map_i ), + .en_default_mst_port_i ( en_default_mst_port_i ), + .default_mst_port_i ( default_mst_port_i ), + // slave port + .slv_req_i ( slv_req ), + .slv_ar_select_i ( slv_ar_select_i ), + .slv_resp_o ( slv_resp ), + // master port + .mst_reqs_o ( mst_req ), + .mst_resps_i ( mst_resp ), + .mst_is_mcast_o ( mst_is_mcast_o ), + .mst_aw_commit_o ( mst_aw_commit_o ) + ); +endmodule diff --git a/src/axi_mcast_demux_simple.sv b/src/axi_mcast_demux_simple.sv new file mode 100644 index 000000000..96b49ddba --- /dev/null +++ b/src/axi_mcast_demux_simple.sv @@ -0,0 +1,746 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Michael Rogenmoser +// - Thomas Benz +// - Andreas Kurth +// - Luca Colagrande + +`include "common_cells/assertions.svh" +`include "common_cells/registers.svh" +`include "axi/assign.svh" + +`ifdef QUESTA +// Derive `TARGET_VSIM`, which is used for tool-specific workarounds in this file, from `QUESTA`, +// which is automatically set in Questa. +`define TARGET_VSIM +`endif + +/// Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports. +/// +/// The AW and AR slave channels each have a `select` input to determine to which master port the +/// current request is sent. The `select` can, for example, be driven by an address decoding module +/// to map address ranges to different AXI slaves. +/// +/// ## Design overview +/// +/// ![Block diagram](module.axi_demux.png "Block diagram") +/// +/// Beats on the W channel are routed by demultiplexer according to the selection for the +/// corresponding AW beat. This relies on the AXI property that W bursts must be sent in the same +/// order as AW beats and beats from different W bursts may not be interleaved. +/// +/// Beats on the B and R channel are multiplexed from the master ports to the slave port with +/// a round-robin arbitration tree. +module axi_mcast_demux_simple #( + parameter int unsigned AxiIdWidth = 32'd0, + parameter bit AtopSupport = 1'b1, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned MaxTrans = 32'd8, + parameter int unsigned AxiLookBits = 32'd3, + parameter bit UniqueIds = 1'b0, + parameter type aw_addr_t = logic, + parameter int unsigned NoMulticastPorts = 32'd0, + parameter int unsigned MaxMcastTrans = 32'd7, + // Dependent parameters, DO NOT OVERRIDE! + parameter int unsigned IdxSelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1, + parameter type idx_select_t = logic [IdxSelectWidth-1:0], + parameter type mask_select_t = logic [NoMstPorts-1:0] +) ( + input logic clk_i, + input logic rst_ni, + // Slave Port + input axi_req_t slv_req_i, + input mask_select_t slv_aw_select_i, + input aw_addr_t [NoMstPorts-1:0] slv_aw_addr_i, + input aw_addr_t [NoMstPorts-1:0] slv_aw_mask_i, + input idx_select_t slv_ar_select_i, + output axi_resp_t slv_resp_o, + // Master Ports + output axi_req_t [NoMstPorts-1:0] mst_reqs_o, + input axi_resp_t [NoMstPorts-1:0] mst_resps_i, + output logic [NoMstPorts-1:0] mst_is_mcast_o, + output logic [NoMstPorts-1:0] mst_aw_commit_o +); + + localparam int unsigned IdCounterWidth = cc_pkg::idx_width(MaxTrans); + typedef logic [IdCounterWidth-1:0] id_cnt_t; + + localparam int unsigned McastCounterWidth = (MaxMcastTrans > 32'd1) ? $clog2(MaxMcastTrans+1) : 32'd1; + typedef logic [McastCounterWidth-1:0] mcast_cnt_t; + + // pass through if only one master port + if (NoMstPorts == 32'h1) begin : gen_no_demux + `AXI_ASSIGN_REQ_STRUCT(mst_reqs_o[0], slv_req_i) + `AXI_ASSIGN_RESP_STRUCT(slv_resp_o, mst_resps_i[0]) + end else begin : gen_demux + + //-------------------------------------- + //-------------------------------------- + // Signal Declarations + //-------------------------------------- + //-------------------------------------- + + //-------------------------------------- + // Write Transaction + //-------------------------------------- + + // Index-form AW select signal for unicast requests + idx_select_t slv_aw_select; + + // AW channel to slave ports + logic [NoMstPorts-1:0] mst_aw_valids, mst_aw_readies; + + // Multicast control signals + logic aw_is_multicast; + logic outstanding_multicast; + logic multicast_stall; + mask_select_t multicast_select_q, multicast_select_d; + mcast_cnt_t outstanding_mcast_cnt_q, outstanding_mcast_cnt_d; + logic [$clog2(NoMstPorts+1)-1:0] aw_select_popcount; + logic accept_aw; + logic mcast_aw_hs_in_progress; + + // Register which locks the AW valid signal + logic lock_aw_valid_d, lock_aw_valid_q, load_aw_lock; + logic aw_valid, aw_ready; + + // AW ID counter + idx_select_t lookup_aw_select; + logic aw_select_occupied, aw_id_cnt_full; + logic aw_any_outstanding_unicast_trx; + // Upon an ATOP load, inject IDs from the AW into the AR channel + logic atop_inject; + + // W select counter: stores the decision to which master(s) W beats should go + logic [NoMstPorts-1:0] mst_w_valids, mst_w_readies; + mask_select_t w_select, w_select_q; + logic w_select_valid; + id_cnt_t w_open; + logic w_cnt_up, w_cnt_down; + + // B channels input into the arbitration (unicast transactions) + // or join module (multicast transactions) + axi_pkg::resp_t [NoMstPorts-1:0] mst_b_resps; + idx_select_t mst_b_valids_tzc; + logic [NoMstPorts-1:0] mst_b_valids, mst_b_readies; + logic [NoMstPorts-1:0] mst_b_readies_arb, mst_b_readies_join; + + // B channel to spill register + logic slv_b_valid_arb, slv_b_valid_join; + + //-------------------------------------- + // Read Transaction + //-------------------------------------- + + // AR ID counter + idx_select_t lookup_ar_select; + logic ar_select_occupied, ar_id_cnt_full; + logic ar_push; + + // Register which locks the AR valid signel + logic lock_ar_valid_d, lock_ar_valid_q, load_ar_lock; + logic ar_valid, ar_ready; + + logic [NoMstPorts-1:0] mst_r_valids, mst_r_readies; + + + + + + + + //-------------------------------------- + // Channel Control + //-------------------------------------- + //-------------------------------------- + + //-------------------------------------- + // AW Channel + //-------------------------------------- + + // Control of the AW handshake + always_comb begin + // AXI Handshakes + slv_resp_o.aw_ready = 1'b0; + aw_valid = 1'b0; + // `lock_aw_valid`, used to be protocol conform as it is not allowed to deassert + // a valid if there was no corresponding ready. As this process has to be able to inject + // an AXI ID into the counter of the AR channel on an ATOP, there could be a case where + // this process waits on `aw_ready` but in the mean time on the AR channel the counter gets + // full. + lock_aw_valid_d = lock_aw_valid_q; + load_aw_lock = 1'b0; + // AW ID counter and W FIFO + w_cnt_up = 1'b0; + // ATOP injection into ar counter + atop_inject = 1'b0; + // we had an arbitration decision, the valid is locked, wait for the transaction + if (lock_aw_valid_q) begin + aw_valid = 1'b1; + // transaction + if (aw_ready) begin + slv_resp_o.aw_ready = 1'b1; + lock_aw_valid_d = 1'b0; + load_aw_lock = 1'b1; + // inject the ATOP if necessary + atop_inject = slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; + end + end else begin + // An AW can be handled if `i_aw_id_counter` and `i_counter_open_w` are not full. An ATOP that + // requires an R response can be handled if additionally `i_ar_id_counter` is not full (this + // only applies if ATOPs are supported at all). + if (!aw_id_cnt_full && (w_open != {IdCounterWidth{1'b1}}) && + (!(ar_id_cnt_full && slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) || + !AtopSupport)) begin + // There is a valid AW vector make the id lookup and go further, if it passes. + // Also stall if previous transmitted AWs still have active W's in flight. + // This prevents deadlocking of the W channel. The counters are there for the + // Handling of the B responses. + if (slv_req_i.aw_valid && + ((w_open == '0) || (w_select == slv_aw_select_i)) && + (!aw_select_occupied || (slv_aw_select == lookup_aw_select)) && + !multicast_stall) begin + // connect the handshake + aw_valid = 1'b1; + // push arbitration to the W FIFO regardless, do not wait for the AW transaction + w_cnt_up = 1'b1; + // on AW transaction + if (aw_ready) begin + slv_resp_o.aw_ready = 1'b1; + atop_inject = slv_req_i.aw.atop[axi_pkg::ATOP_R_RESP] & AtopSupport; + // no AW transaction this cycle, lock the decision + end else begin + lock_aw_valid_d = 1'b1; + load_aw_lock = 1'b1; + end + end + end + end + end + + // lock the valid signal, as the selection gets pushed into the W FIFO on first assertion, + // prevent further pushing + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + + //-------------------------------------- + // Multicast logic + //-------------------------------------- + + // Convert AW select mask to select index since the indices + // are smaller than the masks and thus cheaper to store in + // the ID counters. We anyways don't use the ID counters on + // multicast transactions... + + // Only needed when UniqueIds=0: slv_aw_select feeds the ID counter to track which + // master port a write transaction targets. When UniqueIds=1 the ID counter is absent + // and aw_select_occupied is hardwired to 0, so slv_aw_select is never used. + if (!UniqueIds) begin : gen_onehot_to_bin + cc_onehot_to_bin #( + .OnehotWidth(NoMstPorts) + ) i_onehot_to_bin ( + .onehot_i(slv_aw_select_i & {NoMstPorts{!aw_is_multicast}}), + .bin_o (slv_aw_select) + ); + end else begin : gen_no_onehot_to_bin + assign slv_aw_select = '0; + end + + // Popcount to identify multicast requests + cc_popcount #(NoMstPorts) i_aw_select_popcount ( + .data_i (slv_aw_select_i), + .popcount_o(aw_select_popcount) + ); + + // While there can be multiple outstanding write transactions, i.e. + // multiple AWs can be accepted before the corresponding Bs are returned, + // in the case of multicast transactions this would require the need + // for additional (possibly expensive) hardware. + // The reason is that multicast transactions require merging multiple B + // responses arriving on different master ports. To know which master ports + // need to be merged we need to register the select signal of the + // write transaction. And if we allow multiple outstanding transactions + // we need to register the select signal of each, and we need a big + // associative (by ID) table for this. And actually this still allows + // deadlocks to occur, e.g. if two multicast transactions A and B are partially + // reordered, i.e. some masters respond to A first and some to B. + // If we restrict the outstanding transactions to a single ID then ordering is + // guaranteed, but we anyways need a FIFO to store the selects. + // So for the moment we disallow multiple outstanding transactions in presence + // of a multicast. This means stall an AW request if: + // - there is an outstanding multicast transaction or + // - if the request is a multicast, until there are no more outstanding transactions + // We can slightly loosen this constraint, in the case of successive multicast + // requests going to the same slaves. In this case, we don't need to buffer any + // additional select signals. + assign aw_is_multicast = aw_select_popcount > 1; + assign outstanding_multicast = outstanding_mcast_cnt_q != '0; + assign multicast_stall = (outstanding_multicast && (slv_aw_select_i != multicast_select_q)) || + (aw_is_multicast && aw_any_outstanding_unicast_trx) || + (outstanding_mcast_cnt_q == MaxMcastTrans); + // We can send this signal to all slaves since we will only have one outstanding aw + assign mst_is_mcast_o = {NoMstPorts{aw_is_multicast}}; + + // Keep track of which B responses need to be returned to complete the multicast + `FF(multicast_select_q, multicast_select_d, '0, clk_i, rst_ni) + `FF(outstanding_mcast_cnt_q, outstanding_mcast_cnt_d, '0, clk_i, rst_ni) + + // Logic to update number of outstanding multicast transactions and current multicast + // transactions' select mask. Counter is incremented upon the AW handshake of a multicast + // transaction and decremented upon the "joined" B handshake. + always_comb begin + multicast_select_d = multicast_select_q; + outstanding_mcast_cnt_d = outstanding_mcast_cnt_q; + + // Written as separate if statements as they may both be valid at the same time + // For the same reason the right hand side uses outstanding_mcast_cnt_d + // instead of outstanding_mcast_cnt_q + if (aw_is_multicast && aw_valid && aw_ready) begin + outstanding_mcast_cnt_d = outstanding_mcast_cnt_d + (|slv_aw_select_i); + multicast_select_d = slv_aw_select_i; + end + if (outstanding_multicast && slv_resp_o.b_valid && slv_req_i.b_ready) begin + outstanding_mcast_cnt_d = outstanding_mcast_cnt_d - 1; + end + end + + // Multicast AW transaction handshake state + typedef enum logic {MCastAwHandshakeIdle, MCastAwHandshakeInProgress} mcast_aw_hs_state_e; + mcast_aw_hs_state_e mcast_aw_hs_state_q, mcast_aw_hs_state_d; + + // Update of the multicast AW handshake state + always_comb begin + mcast_aw_hs_state_d = mcast_aw_hs_state_q; + unique case (mcast_aw_hs_state_q) + // Waiting for all selected master ports to be ready + MCastAwHandshakeIdle: + if (accept_aw && aw_is_multicast) begin + mcast_aw_hs_state_d = MCastAwHandshakeInProgress; + end + // Commit is asserted and handshake takes place in the current cycle. + // In the next cycle we are again idle + MCastAwHandshakeInProgress: + mcast_aw_hs_state_d = MCastAwHandshakeIdle; + default: ; + endcase + end + + assign mcast_aw_hs_in_progress = mcast_aw_hs_state_q == MCastAwHandshakeInProgress; + + `FF(mcast_aw_hs_state_q, mcast_aw_hs_state_d, MCastAwHandshakeIdle, clk_i, rst_ni) + + // When a multicast occurs, the upstream valid signals need to + // be forwarded to multiple master ports. + // Proper stream forking is necessary to avoid protocol violations. + // We must also require that downstream handshakes occur + // simultaneously on all addressed master ports, otherwise deadlocks + // may occur. To achieve this we modify the ready-valid protocol by adding + // a third signal, called commit, which is asserted only when we have all + // downstream handshakes. This signal notifies the slaves that the + // handshake can now actually take place. + // Using commit, instead of valid, to this end ensures that we don't have + // any combinational loops. + assign mst_aw_valids = {NoMstPorts{aw_valid}} & slv_aw_select_i; + assign accept_aw = &((mst_aw_valids & mst_aw_readies) | ~slv_aw_select_i); + assign aw_ready = aw_is_multicast ? mcast_aw_hs_in_progress : accept_aw; + assign mst_aw_commit_o = {NoMstPorts{mcast_aw_hs_in_progress}} & slv_aw_select_i; + + // If multicast is enabled, we need to count the number of outstanding transactions + if (UniqueIds) begin : gen_unique_ids_aw + // If the `UniqueIds` parameter is set, each write transaction has an ID that is unique among + // all in-flight write transactions, or all write transactions with a given ID target the same + // master port as all write transactions with the same ID, or both. This means that the + // signals that are driven by the ID counters if this parameter is not set can instead be + // derived from existing signals. The ID counters can therefore be omitted. + assign lookup_aw_select = slv_aw_select; + assign aw_select_occupied = 1'b0; + assign aw_id_cnt_full = 1'b0; + assign aw_any_outstanding_unicast_trx = 1'b0; + + end else begin : gen_aw_id_counter + + axi_demux_id_counters #( + .AxiIdBits ( AxiLookBits ), + .CounterWidth ( IdCounterWidth ), + .mst_port_select_t ( idx_select_t ) + ) i_aw_id_counter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .lookup_axi_id_i ( slv_req_i.aw.id[0+:AxiLookBits] ), + .lookup_mst_select_o ( lookup_aw_select ), + .lookup_mst_select_occupied_o ( aw_select_occupied ), + .full_o ( aw_id_cnt_full ), + .inject_axi_id_i ( '0 ), + .inject_i ( 1'b0 ), + .push_axi_id_i ( slv_req_i.aw.id[0+:AxiLookBits] ), + .push_mst_select_i ( slv_aw_select ), + .push_i ( w_cnt_up && !aw_is_multicast ), + .pop_axi_id_i ( slv_resp_o.b.id[0+:AxiLookBits] ), + .pop_i ( slv_resp_o.b_valid & slv_req_i.b_ready & ~outstanding_multicast ), + .any_outstanding_trx_o ( aw_any_outstanding_unicast_trx ) + ); + // pop from ID counter on outward transaction + end + + // This counter steers the demultiplexer of the W channel. + // `w_select` determines, which handshaking is connected. + // AWs are only forwarded, if the counter is empty, or `w_select_q` is the same as + // `slv_aw_select_i`. + cc_counter #( + .Width ( IdCounterWidth ), + .StickyOverflow ( 1'b0 ) + ) i_counter_open_w ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .en_i ( w_cnt_up ^ w_cnt_down ), + .load_i ( 1'b0 ), + .down_i ( w_cnt_down ), + .d_i ( '0 ), + .q_o ( w_open ), + .overflow_o ( /*not used*/ ) + ); + + `FFL(w_select_q, slv_aw_select_i, w_cnt_up, mask_select_t'(0), clk_i, rst_ni) + assign w_select = (|w_open) ? w_select_q : slv_aw_select_i; + assign w_select_valid = w_cnt_up | (|w_open); + assign w_cnt_down = slv_req_i.w_valid & slv_resp_o.w_ready & slv_req_i.w.last; + + //-------------------------------------- + // W Channel + //-------------------------------------- + + // When a multicast occurs, the upstream valid signals need to + // be forwarded to multiple master ports. + // Proper stream forking is necessary to avoid protocol violations + cc_stream_fork_dynamic #( + .NumOup(NoMstPorts) + ) i_w_stream_fork_dynamic ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_i (1'b0), + .valid_i (slv_req_i.w_valid), + .ready_o (slv_resp_o.w_ready), + .sel_i (w_select), + .sel_valid_i(w_select_valid), + .sel_ready_o(), + .valid_o (mst_w_valids), + .ready_i (mst_w_readies) + ); + + //-------------------------------------- + // B Channel + //-------------------------------------- + logic [cc_pkg::idx_width(NoMstPorts)-1:0] b_idx; + + // Arbitration of the different B responses + cc_rr_arb_tree #( + .NumIn ( NoMstPorts ), + .data_t ( logic ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_b_mux ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .rr_i ( '0 ), + .req_i ( mst_b_valids & {NoMstPorts{!outstanding_multicast}} ), + .gnt_o ( mst_b_readies_arb ), + .data_i ( '0 ), + .gnt_i ( slv_req_i.b_ready ), + .req_o ( slv_b_valid_arb ), + .data_o ( ), + .idx_o ( b_idx ) + ); + + // Streams must be joined instead of arbitrated when multicast + cc_stream_join_dynamic #(NoMstPorts) i_b_stream_join ( + .inp_valid_i(mst_b_valids & {NoMstPorts{outstanding_multicast}}), + .inp_ready_o(mst_b_readies_join), + .sel_i (multicast_select_q), + .oup_valid_o(slv_b_valid_join), + .oup_ready_i(slv_req_i.b_ready) + ); + for (genvar i=0; i 0) else + $fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1"); + AXI_ID_BITS: assume (AxiIdWidth >= AxiLookBits) else + $fatal(1, "AxiIdBits has to be equal or smaller than AxiIdWidth."); + no_multicast_ports: assume (NoMstPorts >= NoMulticastPorts) else + $fatal(1, "NoMstPorts needs to be >= NoMulticastPorts."); + unique_ids_multicast: assume (!UniqueIds || (NoMulticastPorts == 0)) else + $fatal(1, "UniqueIds not supported when multicast is enabled (NoMulticastPorts > 0)."); + end + default disable iff (!rst_ni); + ar_select: assume property( @(posedge clk_i) (slv_req_i.ar_valid |-> + (slv_ar_select_i < NoMstPorts))) else + $fatal(1, "slv_ar_select_i is %d: AR has selected a slave that is not defined.\ + NoMstPorts: %d", slv_ar_select_i, NoMstPorts); + aw_valid_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) |=> aw_valid) else + $fatal(1, "aw_valid was deasserted, when aw_ready = 0 in last cycle."); + ar_valid_stable: assert property( @(posedge clk_i) + (ar_valid && !ar_ready) |=> ar_valid) else + $fatal(1, "ar_valid was deasserted, when ar_ready = 0 in last cycle."); + slv_aw_chan_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) + |=> $stable(slv_req_i.aw)) else + $fatal(1, "slv_aw_chan unstable with valid set."); + slv_aw_select_stable: assert property( @(posedge clk_i) (aw_valid && !aw_ready) + |=> $stable(slv_aw_select_i)) else + $fatal(1, "slv_aw_select_i unstable with valid set."); + slv_ar_chan_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) + |=> $stable(slv_req_i.ar)) else + $fatal(1, "slv_ar_chan unstable with valid set."); + slv_ar_select_stable: assert property( @(posedge clk_i) (ar_valid && !ar_ready) + |=> $stable(slv_ar_select_i)) else + $fatal(1, "slv_ar_select_i unstable with valid set."); + internal_ar_select: assert property( @(posedge clk_i) + (ar_valid |-> slv_ar_select_i < NoMstPorts)) + else $fatal(1, "slv_ar_select_i illegal while ar_valid."); + w_underflow: assert property( @(posedge clk_i) + ((w_open == '0) && (w_cnt_up ^ w_cnt_down) |-> !w_cnt_down)) else + $fatal(1, "W counter underflowed!"); + `ASSUME(NoAtopAllowed, !AtopSupport && slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0) +`endif +`endif +// pragma translate_on + end +endmodule diff --git a/src/axi_mcast_mux.sv b/src/axi_mcast_mux.sv new file mode 100644 index 000000000..72b0eb1f1 --- /dev/null +++ b/src/axi_mcast_mux.sv @@ -0,0 +1,672 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Andreas Kurth + +// AXI Multiplexer: This module multiplexes the AXI4 slave ports down to one master port. +// The AXI IDs from the slave ports get extended with the respective slave port index. +// The extension width can be calculated with `$clog2(NoSlvPorts)`. This means the AXI +// ID for the master port has to be this `$clog2(NoSlvPorts)` wider than the ID for the +// slave ports. +// Responses are switched based on these bits. For example, with 4 slave ports +// a response with ID `6'b100110` will be forwarded to slave port 2 (`2'b10`). + +// register macros +`include "common_cells/assertions.svh" +`include "common_cells/registers.svh" + +module axi_mcast_mux #( + // AXI parameter and channel types + parameter int unsigned SlvAxiIDWidth = 32'd0, // AXI ID width, slave ports + parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports + parameter type mst_aw_chan_t = logic, // AW Channel Type, master port + parameter type w_chan_t = logic, // W Channel Type, all ports + parameter type slv_b_chan_t = logic, // B Channel Type, slave ports + parameter type mst_b_chan_t = logic, // B Channel Type, master port + parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports + parameter type mst_ar_chan_t = logic, // AR Channel Type, master port + parameter type slv_r_chan_t = logic, // R Channel Type, slave ports + parameter type mst_r_chan_t = logic, // R Channel Type, master port + parameter type slv_req_t = logic, // Slave port request type + parameter type slv_resp_t = logic, // Slave port response type + parameter type mst_req_t = logic, // Master ports request type + parameter type mst_resp_t = logic, // Master ports response type + parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports + // Maximum number of outstanding transactions per write + parameter int unsigned MaxWTrans = 32'd8, + // If enabled, this multiplexer is purely combinatorial + parameter bit FallThrough = 1'b0, + // add spill register on write master ports, adds a cycle latency on write channels + parameter bit SpillAw = 1'b1, + parameter bit SpillW = 1'b0, + parameter bit SpillB = 1'b0, + // add spill register on read master ports, adds a cycle latency on read channels + parameter bit SpillAr = 1'b1, + parameter bit SpillR = 1'b0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // slave ports (AXI inputs), connect master modules here + input logic [NoSlvPorts-1:0] slv_is_mcast_i, + input logic [NoSlvPorts-1:0] slv_aw_commit_i, + input slv_req_t [NoSlvPorts-1:0] slv_reqs_i, + output slv_resp_t [NoSlvPorts-1:0] slv_resps_o, + // master port (AXI outputs), connect slave modules here + output mst_req_t mst_req_o, + input mst_resp_t mst_resp_i +); + + localparam int unsigned MstIdxBits = $clog2(NoSlvPorts); + localparam int unsigned MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits; + + // pass through if only one slave port + if (NoSlvPorts == 32'h1) begin : gen_no_mux + cc_spill_register #( + .data_t ( mst_aw_chan_t ), + .Bypass ( ~SpillAw ) + ) i_aw_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( slv_is_mcast_i[0] ? + slv_aw_commit_i[0] : + slv_reqs_i[0].aw_valid ), + .ready_o ( slv_resps_o[0].aw_ready ), + .data_i ( slv_reqs_i[0].aw ), + .valid_o ( mst_req_o.aw_valid ), + .ready_i ( mst_resp_i.aw_ready ), + .data_o ( mst_req_o.aw ) + ); + cc_spill_register #( + .data_t ( w_chan_t ), + .Bypass ( ~SpillW ) + ) i_w_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( slv_reqs_i[0].w_valid ), + .ready_o ( slv_resps_o[0].w_ready ), + .data_i ( slv_reqs_i[0].w ), + .valid_o ( mst_req_o.w_valid ), + .ready_i ( mst_resp_i.w_ready ), + .data_o ( mst_req_o.w ) + ); + cc_spill_register #( + .data_t ( mst_b_chan_t ), + .Bypass ( ~SpillB ) + ) i_b_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( mst_resp_i.b_valid ), + .ready_o ( mst_req_o.b_ready ), + .data_i ( mst_resp_i.b ), + .valid_o ( slv_resps_o[0].b_valid ), + .ready_i ( slv_reqs_i[0].b_ready ), + .data_o ( slv_resps_o[0].b ) + ); + cc_spill_register #( + .data_t ( mst_ar_chan_t ), + .Bypass ( ~SpillAr ) + ) i_ar_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( slv_reqs_i[0].ar_valid ), + .ready_o ( slv_resps_o[0].ar_ready ), + .data_i ( slv_reqs_i[0].ar ), + .valid_o ( mst_req_o.ar_valid ), + .ready_i ( mst_resp_i.ar_ready ), + .data_o ( mst_req_o.ar ) + ); + cc_spill_register #( + .data_t ( mst_r_chan_t ), + .Bypass ( ~SpillR ) + ) i_r_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( mst_resp_i.r_valid ), + .ready_o ( mst_req_o.r_ready ), + .data_i ( mst_resp_i.r ), + .valid_o ( slv_resps_o[0].r_valid ), + .ready_i ( slv_reqs_i[0].r_ready ), + .data_o ( slv_resps_o[0].r ) + ); +// Validate parameters. +// pragma translate_off + `ASSERT_INIT(CorrectIdWidthSlvAw, $bits(slv_reqs_i[0].aw.id) == SlvAxiIDWidth) + `ASSERT_INIT(CorrectIdWidthSlvB, $bits(slv_resps_o[0].b.id) == SlvAxiIDWidth) + `ASSERT_INIT(CorrectIdWidthSlvAr, $bits(slv_reqs_i[0].ar.id) == SlvAxiIDWidth) + `ASSERT_INIT(CorrectIdWidthSlvR, $bits(slv_resps_o[0].r.id) == SlvAxiIDWidth) + `ASSERT_INIT(CorrectIdWidthMstAw, $bits(mst_req_o.aw.id) == SlvAxiIDWidth) + `ASSERT_INIT(CorrectIdWidthMstB, $bits(mst_resp_i.b.id) == SlvAxiIDWidth) + `ASSERT_INIT(CorrectIdWidthMstAr, $bits(mst_req_o.ar.id) == SlvAxiIDWidth) + `ASSERT_INIT(CorrectIdWidthMstR, $bits(mst_resp_i.r.id) == SlvAxiIDWidth) +// pragma translate_on + + // other non degenerate cases + end else begin : gen_mux + + typedef logic [MstIdxBits-1:0] switch_id_t; + + // AXI channels between the ID prepend unit and the rest of the multiplexer + mst_aw_chan_t [NoSlvPorts-1:0] slv_aw_chans; + logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies; + w_chan_t [NoSlvPorts-1:0] slv_w_chans; + logic [NoSlvPorts-1:0] slv_w_valids, slv_w_readies; + mst_b_chan_t [NoSlvPorts-1:0] slv_b_chans; + logic [NoSlvPorts-1:0] slv_b_valids, slv_b_readies; + mst_ar_chan_t [NoSlvPorts-1:0] slv_ar_chans; + logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies; + mst_r_chan_t [NoSlvPorts-1:0] slv_r_chans; + logic [NoSlvPorts-1:0] slv_r_valids, slv_r_readies; + + // These signals are all ID prepended + // AW channel + mst_aw_chan_t mst_aw_chan; + logic mst_aw_valid, mst_aw_ready; + + // AW arbiter signals + mst_aw_chan_t ucast_aw_chan, mcast_aw_chan; + logic ucast_aw_valid, ucast_aw_ready; + logic mcast_aw_valid, mcast_aw_ready, mcast_aw_commit; + logic mcast_not_aw_valid, mcast_aw_priority; + logic [MstIdxBits-1:0] mcast_sel_q, mcast_sel_d; + logic [NoSlvPorts-1:0] mcast_sel_mask; + logic [NoSlvPorts-1:0] ucast_aw_readies, mcast_aw_readies; + + // AW master handshake internal, so that we are able to stall, if w_fifo is full + logic aw_valid, aw_ready; + + // FF to lock the AW valid signal, when a new arbitration decision is made the decision + // gets pushed into the W FIFO, when it now stalls prevent subsequent pushing + // This FF removes AW to W dependency + logic lock_aw_valid_d, lock_aw_valid_q; + logic lock_unicast_d, lock_unicast_q; + logic load_aw_lock; + + // signals for the FIFO that holds the last switching decision of the AW channel + logic w_fifo_full, w_fifo_empty; + logic w_fifo_push, w_fifo_pop; + switch_id_t w_fifo_data; + + // W channel spill reg + w_chan_t mst_w_chan; + logic mst_w_valid, mst_w_ready; + + // master ID in the b_id + switch_id_t switch_b_id; + + // B channel spill reg + mst_b_chan_t mst_b_chan; + logic mst_b_valid; + + // AR channel for when spill is enabled + mst_ar_chan_t mst_ar_chan; + logic ar_valid, ar_ready; + + // master ID in the r_id + switch_id_t switch_r_id; + + // R channel spill reg + mst_r_chan_t mst_r_chan; + logic mst_r_valid; + + //-------------------------------------- + // ID prepend for all slave ports + //-------------------------------------- + for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_id_prepend + axi_id_prepend #( + .NoBus ( 32'd1 ), // one AXI bus per slave port + .AxiIdWidthSlvPort( SlvAxiIDWidth ), + .AxiIdWidthMstPort( MstAxiIDWidth ), + .slv_aw_chan_t ( slv_aw_chan_t ), + .slv_w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .mst_w_chan_t ( w_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ) + ) i_id_prepend ( + .pre_id_i ( switch_id_t'(i) ), + .slv_aw_chans_i ( slv_reqs_i[i].aw ), + .slv_aw_valids_i ( slv_reqs_i[i].aw_valid ), + .slv_aw_readies_o ( slv_resps_o[i].aw_ready ), + .slv_w_chans_i ( slv_reqs_i[i].w ), + .slv_w_valids_i ( slv_reqs_i[i].w_valid ), + .slv_w_readies_o ( slv_resps_o[i].w_ready ), + .slv_b_chans_o ( slv_resps_o[i].b ), + .slv_b_valids_o ( slv_resps_o[i].b_valid ), + .slv_b_readies_i ( slv_reqs_i[i].b_ready ), + .slv_ar_chans_i ( slv_reqs_i[i].ar ), + .slv_ar_valids_i ( slv_reqs_i[i].ar_valid ), + .slv_ar_readies_o ( slv_resps_o[i].ar_ready ), + .slv_r_chans_o ( slv_resps_o[i].r ), + .slv_r_valids_o ( slv_resps_o[i].r_valid ), + .slv_r_readies_i ( slv_reqs_i[i].r_ready ), + .mst_aw_chans_o ( slv_aw_chans[i] ), + .mst_aw_valids_o ( slv_aw_valids[i] ), + .mst_aw_readies_i ( slv_aw_readies[i] ), + .mst_w_chans_o ( slv_w_chans[i] ), + .mst_w_valids_o ( slv_w_valids[i] ), + .mst_w_readies_i ( slv_w_readies[i] ), + .mst_b_chans_i ( slv_b_chans[i] ), + .mst_b_valids_i ( slv_b_valids[i] ), + .mst_b_readies_o ( slv_b_readies[i] ), + .mst_ar_chans_o ( slv_ar_chans[i] ), + .mst_ar_valids_o ( slv_ar_valids[i] ), + .mst_ar_readies_i ( slv_ar_readies[i] ), + .mst_r_chans_i ( slv_r_chans[i] ), + .mst_r_valids_i ( slv_r_valids[i] ), + .mst_r_readies_o ( slv_r_readies[i] ) + ); + end + + //-------------------------------------- + // AW Channel + //-------------------------------------- + // Arbitrate unicast requests in round-robin fashion + cc_rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .data_t ( mst_aw_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_aw_ucast_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .rr_i ( '0 ), + .req_i ( slv_aw_valids & ~slv_is_mcast_i ), + .gnt_o ( ucast_aw_readies ), + .data_i ( slv_aw_chans ), + .gnt_i ( ucast_aw_ready ), + .req_o ( ucast_aw_valid ), + .data_o ( ucast_aw_chan ), + .idx_o ( ) + ); + + // Arbitrate multicast requests in priority encoder fashion + cc_lzc #( + .Width ( NoSlvPorts ), + .Mode ( cc_pkg::LZC_TRAILING_ZERO_CNT ) + ) i_aw_mcast_lzc ( + .in_i ( slv_aw_valids & slv_is_mcast_i ), + .cnt_o ( mcast_sel_d ), + .empty_o ( mcast_not_aw_valid ) + ); + assign mcast_sel_mask = mcast_not_aw_valid ? '0 : 1 << mcast_sel_d; + assign mcast_aw_chan = slv_aw_chans[mcast_sel_q]; + assign mcast_aw_valid = !mcast_not_aw_valid; + assign mcast_aw_commit = |slv_aw_commit_i; + assign mcast_aw_readies = {NoSlvPorts{mcast_aw_ready}} & mcast_sel_mask; + + `FFL(mcast_sel_q, mcast_sel_d, mcast_aw_valid && mcast_aw_ready, '0, clk_i, rst_ni) + + // Arbitrate "winners" of unicast and multicast arbitrations, + // giving priority to multicast. + // On a multicast, the downstream valid is gated until we get the commit signal. + // But the commit signal is only received after we have received the downstream + // ready and propagated it upstream. So the downstream ready will be kept high + // for an additional cycle after there was an upstream handshake. We must thus + // gate it upstream for that additional cycle (with !mcast_aw_commit). + // If we already locked the AW on a unicast transaction, we must wait for it to + // complete before accepting a multicast transaction, so we give priority to the + // unicast. + assign mcast_aw_priority = mcast_aw_valid && !lock_unicast_q; + assign mcast_aw_ready = aw_ready && !mcast_aw_commit && mcast_aw_priority; + assign ucast_aw_ready = aw_ready && !mcast_aw_commit && !mcast_aw_priority; + assign mst_aw_chan = mcast_aw_commit ? mcast_aw_chan : ucast_aw_chan; + assign slv_aw_readies = mcast_aw_readies | ucast_aw_readies; + // In case of a multicast transaction, downstream valid should only be asserted + // on commit. However, a multicast transaction is already accepted on the cycle + // before, when we have mcast_aw_valid. We must prevent a unicast transaction + // from raising the downstream valid in that time (with !mcast_aw_valid). + assign aw_valid = mcast_aw_commit || (ucast_aw_valid && !mcast_aw_valid); + + // control of the AW channel + always_comb begin + // default assignments + lock_aw_valid_d = lock_aw_valid_q; + lock_unicast_d = lock_unicast_q; + load_aw_lock = 1'b0; + w_fifo_push = 1'b0; + mst_aw_valid = 1'b0; + aw_ready = 1'b0; + // had a downstream stall, be valid and send the AW along + if (lock_aw_valid_q) begin + mst_aw_valid = 1'b1; + // transaction + if (mst_aw_ready) begin + aw_ready = 1'b1; + lock_aw_valid_d = 1'b0; + lock_unicast_d = 1'b0; + load_aw_lock = 1'b1; + w_fifo_push = 1'b1; + end + end else begin + if (!w_fifo_full) begin + if (mst_aw_ready) begin + aw_ready = 1'b1; + end + if (aw_valid) begin + mst_aw_valid = 1'b1; + if (!mst_aw_ready) begin + // go to lock if transaction not in this cycle + lock_aw_valid_d = 1'b1; + load_aw_lock = 1'b1; + // remember if it was a unicast transaction + lock_unicast_d = !mcast_aw_commit; + end else begin + w_fifo_push = 1'b1; + end + end + end + end + end + + `FFL(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + `FFL(lock_unicast_q, lock_unicast_d, load_aw_lock, '0, clk_i, rst_ni) + + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( MaxWTrans ), + .data_t ( switch_id_t ) + ) i_w_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .flush_i ( 1'b0 ), + .full_o ( w_fifo_full ), + .empty_o ( w_fifo_empty ), + .usage_o ( ), + .data_i ( mst_aw_chan.id[SlvAxiIDWidth+:MstIdxBits] ), + .push_i ( w_fifo_push ), + .data_o ( w_fifo_data ), + .pop_i ( w_fifo_pop ) + ); + + cc_spill_register #( + .data_t ( mst_aw_chan_t ), + .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg + ) i_aw_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( mst_aw_valid ), + .ready_o ( mst_aw_ready ), + .data_i ( mst_aw_chan ), + .valid_o ( mst_req_o.aw_valid ), + .ready_i ( mst_resp_i.aw_ready ), + .data_o ( mst_req_o.aw ) + ); + + //-------------------------------------- + // W Channel + //-------------------------------------- + // multiplexer + assign mst_w_chan = slv_w_chans[w_fifo_data]; + always_comb begin + // default assignments + mst_w_valid = 1'b0; + slv_w_readies = '0; + w_fifo_pop = 1'b0; + // control + if (!w_fifo_empty) begin + // connect the handshake + mst_w_valid = slv_w_valids[w_fifo_data]; + slv_w_readies[w_fifo_data] = mst_w_ready; + // pop FIFO on a last transaction + w_fifo_pop = slv_w_valids[w_fifo_data] & mst_w_ready & mst_w_chan.last; + end + end + + cc_spill_register #( + .data_t ( w_chan_t ), + .Bypass ( ~SpillW ) + ) i_w_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( mst_w_valid ), + .ready_o ( mst_w_ready ), + .data_i ( mst_w_chan ), + .valid_o ( mst_req_o.w_valid ), + .ready_i ( mst_resp_i.w_ready ), + .data_o ( mst_req_o.w ) + ); + + //-------------------------------------- + // B Channel + //-------------------------------------- + // replicate B channels + assign slv_b_chans = {NoSlvPorts{mst_b_chan}}; + // control B channel handshake + assign switch_b_id = mst_b_chan.id[SlvAxiIDWidth+:MstIdxBits]; + assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0; + + cc_spill_register #( + .data_t ( mst_b_chan_t ), + .Bypass ( ~SpillB ) + ) i_b_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( mst_resp_i.b_valid ), + .ready_o ( mst_req_o.b_ready ), + .data_i ( mst_resp_i.b ), + .valid_o ( mst_b_valid ), + .ready_i ( slv_b_readies[switch_b_id] ), + .data_o ( mst_b_chan ) + ); + + //-------------------------------------- + // AR Channel + //-------------------------------------- + cc_rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .data_t ( mst_ar_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_ar_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .rr_i ( '0 ), + .req_i ( slv_ar_valids ), + .gnt_o ( slv_ar_readies ), + .data_i ( slv_ar_chans ), + .gnt_i ( ar_ready ), + .req_o ( ar_valid ), + .data_o ( mst_ar_chan ), + .idx_o ( ) + ); + + cc_spill_register #( + .data_t ( mst_ar_chan_t ), + .Bypass ( ~SpillAr ) + ) i_ar_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( ar_valid ), + .ready_o ( ar_ready ), + .data_i ( mst_ar_chan ), + .valid_o ( mst_req_o.ar_valid ), + .ready_i ( mst_resp_i.ar_ready ), + .data_o ( mst_req_o.ar ) + ); + + //-------------------------------------- + // R Channel + //-------------------------------------- + // replicate R channels + assign slv_r_chans = {NoSlvPorts{mst_r_chan}}; + // R channel handshake control + assign switch_r_id = mst_r_chan.id[SlvAxiIDWidth+:MstIdxBits]; + assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0; + + cc_spill_register #( + .data_t ( mst_r_chan_t ), + .Bypass ( ~SpillR ) + ) i_r_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .valid_i ( mst_resp_i.r_valid ), + .ready_o ( mst_req_o.r_ready ), + .data_i ( mst_resp_i.r ), + .valid_o ( mst_r_valid ), + .ready_i ( slv_r_readies[switch_r_id] ), + .data_o ( mst_r_chan ) + ); + end + +// pragma translate_off +`ifndef VERILATOR + initial begin + assert (SlvAxiIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!"); + assert (NoSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!"); + assert (MaxWTrans > 0) + else $fatal(1, "Maximum number of outstanding writes must be non-zero!"); + assert (MstAxiIDWidth >= SlvAxiIDWidth + $clog2(NoSlvPorts)) + else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!"); + // Assert ID widths (one slave is sufficient since they all have the same type). + assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of AW channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_reqs_i[0].ar.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of AR channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_resps_o[0].b.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of B channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_resps_o[0].r.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of R channel of slave ports does not match parameter!"); + assert ($unsigned($bits(mst_req_o.aw.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of AW channel of master port is wrong!"); + assert ($unsigned($bits(mst_req_o.ar.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of AR channel of master port is wrong!"); + assert ($unsigned($bits(mst_resp_i.b.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of B channel of master port is wrong!"); + assert ($unsigned($bits(mst_resp_i.r.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of R channel of master port is wrong!"); + end +`endif +// pragma translate_on +endmodule + +// interface wrap +`include "axi/assign.svh" +`include "axi/typedef.svh" +module axi_mcast_mux_intf #( + parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter int unsigned MST_AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports + // Maximum number of outstanding transactions per write + parameter int unsigned MAX_W_TRANS = 32'd8, + // if enabled, this multiplexer is purely combinatorial + parameter bit FALL_THROUGH = 1'b0, + // add spill register on write master ports, adds a cycle latency on write channels + parameter bit SPILL_AW = 1'b1, + parameter bit SPILL_W = 1'b0, + parameter bit SPILL_B = 1'b0, + // add spill register on read master ports, adds a cycle latency on read channels + parameter bit SPILL_AR = 1'b1, + parameter bit SPILL_R = 1'b0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic [NO_SLV_PORTS-1:0] slv_is_mcast_i, + input logic [NO_SLV_PORTS-1:0] slv_aw_commit_i, + AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports + AXI_BUS.Master mst // master port +); + + typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t; + typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + // channels typedef + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t) + + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t) + + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + + slv_req_t [NO_SLV_PORTS-1:0] slv_reqs; + slv_resp_t [NO_SLV_PORTS-1:0] slv_resps; + mst_req_t mst_req; + mst_resp_t mst_resp; + + for (genvar i = 0; i < NO_SLV_PORTS; i++) begin : gen_assign_slv_ports + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) + `AXI_ASSIGN_FROM_RESP(slv[i], slv_resps[i]) + end + + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_mcast_mux #( + .SlvAxiIDWidth ( SLV_AXI_ID_WIDTH ), + .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .w_chan_t ( w_chan_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports + .MaxWTrans ( MAX_W_TRANS ), + .FallThrough ( FALL_THROUGH ), + .SpillAw ( SPILL_AW ), + .SpillW ( SPILL_W ), + .SpillB ( SPILL_B ), + .SpillAr ( SPILL_AR ), + .SpillR ( SPILL_R ) + ) i_axi_mux ( + .clk_i ( clk_i ), // Clock + .rst_ni ( rst_ni ), // Asynchronous reset active low + .slv_is_mcast_i, + .slv_aw_commit_i, + .slv_reqs_i ( slv_reqs ), + .slv_resps_o ( slv_resps ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); +endmodule diff --git a/src/axi_mcast_xbar.sv b/src/axi_mcast_xbar.sv new file mode 100644 index 000000000..4e9bd81fd --- /dev/null +++ b/src/axi_mcast_xbar.sv @@ -0,0 +1,257 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Andreas Kurth +// - Florian Zaruba +// - Luca Colagrande + +/// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. +/// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. +module axi_mcast_xbar +import cc_pkg::idx_width; +#( + /// Configuration struct for the crossbar see `axi_pkg` for fields and definitions. + parameter axi_pkg::xbar_cfg_t Cfg = '0, + /// Enable atomic operations support. + parameter bit ATOPs = 1'b1, + /// Connectivity matrix + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] Connectivity = '1, + /// Connectivity matrix for multicast transactions + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] MulticastConnectivity = '1, + /// AXI4+ATOP AW channel struct type for the slave ports. + parameter type slv_aw_chan_t = logic, + /// AXI4+ATOP AW channel struct type for the master ports. + parameter type mst_aw_chan_t = logic, + /// AXI4+ATOP W channel struct type for all ports. + parameter type w_chan_t = logic, + /// AXI4+ATOP B channel struct type for the slave ports. + parameter type slv_b_chan_t = logic, + /// AXI4+ATOP B channel struct type for the master ports. + parameter type mst_b_chan_t = logic, + /// AXI4+ATOP AR channel struct type for the slave ports. + parameter type slv_ar_chan_t = logic, + /// AXI4+ATOP AR channel struct type for the master ports. + parameter type mst_ar_chan_t = logic, + /// AXI4+ATOP R channel struct type for the slave ports. + parameter type slv_r_chan_t = logic, + /// AXI4+ATOP R channel struct type for the master ports. + parameter type mst_r_chan_t = logic, + /// AXI4+ATOP request struct type for the slave ports. + parameter type slv_req_t = logic, + /// AXI4+ATOP response struct type for the slave ports. + parameter type slv_resp_t = logic, + /// AXI4+ATOP request struct type for the master ports. + parameter type mst_req_t = logic, + /// AXI4+ATOP response struct type for the master ports + parameter type mst_resp_t = logic, + /// Address rule type for the address decoders from `common_cells:addr_decode`. + /// Example types are provided in `axi_pkg`. + /// Required struct fields: + /// ``` + /// typedef struct packed { + /// int unsigned idx; + /// axi_addr_t start_addr; + /// axi_addr_t end_addr; + /// } rule_t; + /// ``` + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + /// Clock, positive edge triggered. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Testmode enable, active high. + /// AXI4+ATOP requests to the slave ports. + input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, + /// AXI4+ATOP responses of the slave ports. + output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, + /// AXI4+ATOP requests of the master ports. + output mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, + /// AXI4+ATOP responses to the master ports. + input mst_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, + /// Address map array input for the crossbar. This map is global for the whole module. + /// It is used for routing the transactions to the respective master ports. + /// Each master port can have multiple different rules. + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + /// Enable default master port. + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + /// Enables a default master port for each slave port. When this is enabled unmapped + /// transactions get issued at the master port given by `default_mst_port_i`. + /// When not used, tie to `'0`. + input rule_t [Cfg.NoSlvPorts-1:0] default_mst_port_i +); + + // signals into the axi_muxes, are of type slave as the multiplexer extends the ID + slv_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; + slv_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + + logic [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_is_mcast; + logic [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_aw_commit; + + axi_mcast_xbar_unmuxed #( + .Cfg (Cfg), + .ATOPs (ATOPs), + .Connectivity (Connectivity), + .MulticastConnectivity (MulticastConnectivity), + .aw_chan_t (slv_aw_chan_t), + .w_chan_t (w_chan_t), + .b_chan_t (slv_b_chan_t), + .ar_chan_t (slv_ar_chan_t), + .r_chan_t (slv_r_chan_t), + .req_t (slv_req_t), + .resp_t (slv_resp_t), + .rule_t (rule_t) + ) i_xbar_unmuxed ( + .clk_i, + .rst_ni, + .slv_ports_req_i, + .slv_ports_resp_o, + .mst_ports_req_o (mst_reqs), + .mst_ports_resp_i (mst_resps), + .mst_is_mcast_o (mst_is_mcast), + .mst_aw_commit_o (mst_aw_commit), + .addr_map_i, + .en_default_mst_port_i, + .default_mst_port_i + ); + + for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux + axi_mcast_mux #( + .SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts ), // ID width of the slave ports + .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .w_chan_t ( w_chan_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module + .MaxWTrans ( Cfg.MaxSlvTrans ), + .FallThrough ( Cfg.FallThrough ), + .SpillAw ( Cfg.LatencyMode[4] ), + .SpillW ( Cfg.LatencyMode[3] ), + .SpillB ( Cfg.LatencyMode[2] ), + .SpillAr ( Cfg.LatencyMode[1] ), + .SpillR ( Cfg.LatencyMode[0] ) + ) i_axi_mux ( + .clk_i, // Clock + .rst_ni, // Asynchronous reset active low + .slv_is_mcast_i ( mst_is_mcast[i] ), + .slv_aw_commit_i ( mst_aw_commit[i] ), + .slv_reqs_i ( mst_reqs[i] ), + .slv_resps_o ( mst_resps[i] ), + .mst_req_o ( mst_ports_req_o[i] ), + .mst_resp_i ( mst_ports_resp_i[i] ) + ); + end + +endmodule + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module axi_mcast_xbar_intf +import cc_pkg::idx_width; +#( + parameter int unsigned AXI_USER_WIDTH = 0, + parameter axi_pkg::xbar_cfg_t Cfg = '0, + parameter bit ATOPS = 1'b1, + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1, + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] MULTICAST_CONNECTIVITY = '1, + parameter type aw_user_t = logic [AXI_USER_WIDTH-1:0], + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], + AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input rule_t [Cfg.NoSlvPorts-1:0] default_mst_port_i +); + + localparam int unsigned AxiIdWidthMstPorts = Cfg.AxiIdWidthSlvPorts + $clog2(Cfg.NoSlvPorts); + + typedef logic [AxiIdWidthMstPorts -1:0] id_mst_t; + typedef logic [Cfg.AxiIdWidthSlvPorts -1:0] id_slv_t; + typedef logic [Cfg.AxiAddrWidth -1:0] addr_t; + typedef logic [Cfg.AxiDataWidth -1:0] data_t; + typedef logic [Cfg.AxiDataWidth/8 -1:0] strb_t; + typedef logic [AXI_USER_WIDTH -1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, aw_user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + mst_req_t [Cfg.NoMstPorts-1:0] mst_reqs; + mst_resp_t [Cfg.NoMstPorts-1:0] mst_resps; + slv_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; + slv_resp_t [Cfg.NoSlvPorts-1:0] slv_resps; + + for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst + `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) + `AXI_ASSIGN_TO_RESP(mst_resps[i], mst_ports[i]) + end + + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) + `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) + end + + axi_mcast_xbar #( + .Cfg (Cfg), + .ATOPs ( ATOPS ), + .Connectivity ( CONNECTIVITY ), + .MulticastConnectivity ( MULTICAST_CONNECTIVITY ), + .slv_aw_chan_t ( slv_aw_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .rule_t ( rule_t ) + ) i_xbar ( + .clk_i, + .rst_ni, + .slv_ports_req_i (slv_reqs ), + .slv_ports_resp_o (slv_resps), + .mst_ports_req_o (mst_reqs ), + .mst_ports_resp_i (mst_resps), + .addr_map_i, + .en_default_mst_port_i, + .default_mst_port_i + ); + +endmodule diff --git a/src/axi_mcast_xbar_unmuxed.sv b/src/axi_mcast_xbar_unmuxed.sv new file mode 100644 index 000000000..db9a375dc --- /dev/null +++ b/src/axi_mcast_xbar_unmuxed.sv @@ -0,0 +1,286 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Andreas Kurth +// - Florian Zaruba + +/// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. +/// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. +module axi_mcast_xbar_unmuxed +import cc_pkg::idx_width; +#( + /// Configuration struct for the crossbar see `axi_pkg` for fields and definitions. + parameter axi_pkg::xbar_cfg_t Cfg = '0, + /// Enable atomic operations support. + parameter bit ATOPs = 1'b1, + /// Connectivity matrix + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] Connectivity = '1, + /// Connectivity matrix for multicast transactions + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] MulticastConnectivity = '1, + /// AXI4+ATOP AW channel struct type for the slave ports. + parameter type aw_chan_t = logic, + /// AXI4+ATOP W channel struct type for all ports. + parameter type w_chan_t = logic, + /// AXI4+ATOP B channel struct type for the slave ports. + parameter type b_chan_t = logic, + /// AXI4+ATOP AR channel struct type for the slave ports. + parameter type ar_chan_t = logic, + /// AXI4+ATOP R channel struct type for the slave ports. + parameter type r_chan_t = logic, + /// AXI4+ATOP request struct type for the slave ports. + parameter type req_t = logic, + /// AXI4+ATOP response struct type for the slave ports. + parameter type resp_t = logic, + /// Address rule type for the address decoders from `common_cells:addr_decode`. + /// Example types are provided in `axi_pkg`. + /// Required struct fields: + /// ``` + /// typedef struct packed { + /// int unsigned idx; + /// axi_addr_t start_addr; + /// axi_addr_t end_addr; + /// } rule_t; + /// ``` + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + /// Clock, positive edge triggered. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Testmode enable, active high. + /// AXI4+ATOP requests to the slave ports. + input req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, + /// AXI4+ATOP responses of the slave ports. + output resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, + /// AXI4+ATOP requests of the master ports. + output req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_ports_req_o, + /// AXI4+ATOP responses to the master ports. + input resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_ports_resp_i, + /// Additional multicast signals to the master ports. + output logic [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_is_mcast_o, + output logic [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_aw_commit_o, + /// Address map array input for the crossbar. This map is global for the whole module. + /// It is used for routing the transactions to the respective master ports. + /// Each master port can have multiple different rules. + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + /// Enable default master port. + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + /// Enables a default master port for each slave port. When this is enabled unmapped + /// transactions get issued at the master port given by `default_mst_port_i`. + /// When not used, tie to `'0`. + input rule_t [Cfg.NoSlvPorts-1:0] default_mst_port_i +); + + localparam bit EnableMulticast = (Cfg.NoMulticastPorts > 0) || (Cfg.NoMulticastRules > 0); + + // signals from the axi_demuxes + req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] slv_reqs; + resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] slv_resps; + logic [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] slv_is_mcast; + logic [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] slv_aw_commit; + + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux + + axi_mcast_demux_mapped #( + .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), // ID Width + .AxiAddrWidth ( Cfg.AxiAddrWidth ), + .AtopSupport ( ATOPs ), + .aw_chan_t ( aw_chan_t ), // AW Channel Type + .w_chan_t ( w_chan_t ), // W Channel Type + .b_chan_t ( b_chan_t ), // B Channel Type + .ar_chan_t ( ar_chan_t ), // AR Channel Type + .r_chan_t ( r_chan_t ), // R Channel Type + .axi_req_t ( req_t ), + .axi_resp_t ( resp_t ), + .NoMstPorts ( Cfg.NoMstPorts ), + .MaxTrans ( Cfg.MaxMstTrans ), + .AxiLookBits ( Cfg.AxiIdUsedSlvPorts ), + .UniqueIds ( Cfg.UniqueIds ), + .SpillAw ( Cfg.LatencyMode[9] ), + .SpillW ( Cfg.LatencyMode[8] ), + .SpillB ( Cfg.LatencyMode[7] ), + .SpillAr ( Cfg.LatencyMode[6] ), + .SpillR ( Cfg.LatencyMode[5] ), + .Connectivity ( Connectivity[i] ), + .MulticastConnectivity ( MulticastConnectivity[i] ), + .rule_t ( rule_t ), + .NoAddrRules ( Cfg.NoAddrRules ), + .NoMulticastRules ( Cfg.NoMulticastRules ), + .NoMulticastPorts ( Cfg.NoMulticastPorts ) + ) i_axi_demux ( + .clk_i, // Clock + .rst_ni, // Asynchronous reset active low + .addr_map_i ( addr_map_i ), + .en_default_mst_port_i ( en_default_mst_port_i[i] ), + .default_mst_port_i ( default_mst_port_i[i] ), + .slv_req_i ( slv_ports_req_i[i] ), + .slv_resp_o ( slv_ports_resp_o[i] ), + .mst_reqs_o ( slv_reqs[i] ), + .mst_resps_i ( slv_resps[i] ), + .mst_is_mcast_o ( slv_is_mcast[i] ), + .mst_aw_commit_o ( slv_aw_commit[i] ) + ); + + end + + // cross all channels + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_xbar_slv_cross + for (genvar j = 0; j < Cfg.NoMstPorts; j++) begin : gen_xbar_mst_cross + if (Connectivity[i][j]) begin : gen_connection + + assign mst_is_mcast_o[j][i] = slv_is_mcast[i][j]; + assign mst_aw_commit_o[j][i] = slv_aw_commit[i][j]; + + axi_multicut #( + .NoCuts ( Cfg.PipelineStages ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .axi_req_t ( req_t ), + .axi_resp_t ( resp_t ) + ) i_axi_multicut_xbar_pipeline ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_reqs[i][j] ), + .slv_resp_o ( slv_resps[i][j] ), + .mst_req_o ( mst_ports_req_o[j][i] ), + .mst_resp_i ( mst_ports_resp_i[j][i] ) + ); + + end else begin : gen_no_connection + + assign mst_is_mcast_o[j][i] = 1'b0; + assign mst_aw_commit_o[j][i] = 1'b0; + + assign mst_ports_req_o[j][i] = '0; + axi_err_slv #( + .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), + .axi_req_t ( req_t ), + .axi_resp_t ( resp_t ), + .Resp ( axi_pkg::RESP_DECERR ), + .ATOPs ( ATOPs ), + .MaxTrans ( 1 ) + ) i_axi_err_slv ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_reqs[i][j] ), + .slv_resp_o ( slv_resps[i][j] ) + ); + end + end + end + + // pragma translate_off + `ifndef VERILATOR + `ifndef XSIM + initial begin : check_params + id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else + $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); + id_slv_resp_ports: assert ($bits(slv_ports_resp_o[0].r.id) == Cfg.AxiIdWidthSlvPorts) else + $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); + addr_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.addr) == Cfg.AxiAddrWidth) else + $fatal(1, $sformatf("Slv_req and aw_addr width not equal.")); + addr_mst_req_ports: assert ($bits(mst_ports_req_o[0][0].aw.addr) == Cfg.AxiAddrWidth) else + $fatal(1, $sformatf("Mst_req and aw_addr width not equal.")); + no_cuts_if_mcast: assert (!EnableMulticast || (Cfg.PipelineStages == 0)) else + $fatal(1, $sformatf("Multicast XBAR currently does not support pipeline stages.")); + end + `endif + `endif + // pragma translate_on +endmodule + +`ifndef VCS +// As of now, VCS does not support multi-dimensional array of interfaces. +`include "axi/assign.svh" +`include "axi/typedef.svh" + +module axi_mcast_xbar_unmuxed_intf +import cc_pkg::idx_width; +#( + parameter int unsigned AXI_USER_WIDTH = 0, + parameter axi_pkg::xbar_cfg_t Cfg = '0, + parameter bit ATOPS = 1'b1, + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1, + parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] MULTICAST_CONNECTIVITY = '1, + parameter type rule_t = axi_pkg::xbar_rule_64_t +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], + AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0], + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i +); + + typedef logic [Cfg.AxiIdWidthSlvPorts -1:0] id_t; + typedef logic [Cfg.AxiAddrWidth -1:0] addr_t; + typedef logic [Cfg.AxiDataWidth -1:0] data_t; + typedef logic [Cfg.AxiDataWidth/8 -1:0] strb_t; + typedef logic [AXI_USER_WIDTH -1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; + resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + req_t [Cfg.NoSlvPorts-1:0] slv_reqs; + resp_t [Cfg.NoSlvPorts-1:0] slv_resps; + + for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst + for (genvar j = 0; j < Cfg.NoSlvPorts; j++) begin : gen_assign_mst_inner + `AXI_ASSIGN_FROM_REQ(mst_ports[i][j], mst_reqs[i][j]) + `AXI_ASSIGN_TO_RESP(mst_resps[i][j], mst_ports[i][j]) + end + end + + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) + `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) + end + + axi_mcast_xbar_unmuxed #( + .Cfg ( Cfg ), + .ATOPs ( ATOPS ), + .Connectivity ( CONNECTIVITY ), + .MulticastConnectivity ( MULTICAST_CONNECTIVITY ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .req_t ( req_t ), + .resp_t ( resp_t ), + .rule_t ( rule_t ) + ) i_xbar ( + .clk_i, + .rst_ni, + .slv_ports_req_i (slv_reqs ), + .slv_ports_resp_o (slv_resps), + .mst_ports_req_o (mst_reqs ), + .mst_ports_resp_i (mst_resps), + .addr_map_i, + .en_default_mst_port_i, + .default_mst_port_i + ); + +endmodule + +`endif diff --git a/src/axi_mux.sv b/src/axi_mux.sv index da17e2b8c..3dc3fd2cf 100644 --- a/src/axi_mux.sv +++ b/src/axi_mux.sv @@ -56,7 +56,6 @@ module axi_mux #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Test Mode enable // slave ports (AXI inputs), connect master modules here input slv_req_t [NoSlvPorts-1:0] slv_reqs_i, output slv_resp_t [NoSlvPorts-1:0] slv_resps_o, @@ -65,433 +64,40 @@ module axi_mux #( input mst_resp_t mst_resp_i ); - localparam int unsigned MstIdxBits = $clog2(NoSlvPorts); - localparam int unsigned MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits; - - // pass through if only one slave port - if (NoSlvPorts == 32'h1) begin : gen_no_mux - spill_register #( - .T ( mst_aw_chan_t ), - .Bypass ( ~SpillAw ) - ) i_aw_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].aw_valid ), - .ready_o ( slv_resps_o[0].aw_ready ), - .data_i ( slv_reqs_i[0].aw ), - .valid_o ( mst_req_o.aw_valid ), - .ready_i ( mst_resp_i.aw_ready ), - .data_o ( mst_req_o.aw ) - ); - spill_register #( - .T ( w_chan_t ), - .Bypass ( ~SpillW ) - ) i_w_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].w_valid ), - .ready_o ( slv_resps_o[0].w_ready ), - .data_i ( slv_reqs_i[0].w ), - .valid_o ( mst_req_o.w_valid ), - .ready_i ( mst_resp_i.w_ready ), - .data_o ( mst_req_o.w ) - ); - spill_register #( - .T ( mst_b_chan_t ), - .Bypass ( ~SpillB ) - ) i_b_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( mst_resp_i.b_valid ), - .ready_o ( mst_req_o.b_ready ), - .data_i ( mst_resp_i.b ), - .valid_o ( slv_resps_o[0].b_valid ), - .ready_i ( slv_reqs_i[0].b_ready ), - .data_o ( slv_resps_o[0].b ) - ); - spill_register #( - .T ( mst_ar_chan_t ), - .Bypass ( ~SpillAr ) - ) i_ar_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( slv_reqs_i[0].ar_valid ), - .ready_o ( slv_resps_o[0].ar_ready ), - .data_i ( slv_reqs_i[0].ar ), - .valid_o ( mst_req_o.ar_valid ), - .ready_i ( mst_resp_i.ar_ready ), - .data_o ( mst_req_o.ar ) - ); - spill_register #( - .T ( mst_r_chan_t ), - .Bypass ( ~SpillR ) - ) i_r_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( mst_resp_i.r_valid ), - .ready_o ( mst_req_o.r_ready ), - .data_i ( mst_resp_i.r ), - .valid_o ( slv_resps_o[0].r_valid ), - .ready_i ( slv_reqs_i[0].r_ready ), - .data_o ( slv_resps_o[0].r ) - ); -// Validate parameters. -// pragma translate_off - `ASSERT_INIT(CorrectIdWidthSlvAw, $bits(slv_reqs_i[0].aw.id) == SlvAxiIDWidth) - `ASSERT_INIT(CorrectIdWidthSlvB, $bits(slv_resps_o[0].b.id) == SlvAxiIDWidth) - `ASSERT_INIT(CorrectIdWidthSlvAr, $bits(slv_reqs_i[0].ar.id) == SlvAxiIDWidth) - `ASSERT_INIT(CorrectIdWidthSlvR, $bits(slv_resps_o[0].r.id) == SlvAxiIDWidth) - `ASSERT_INIT(CorrectIdWidthMstAw, $bits(mst_req_o.aw.id) == SlvAxiIDWidth) - `ASSERT_INIT(CorrectIdWidthMstB, $bits(mst_resp_i.b.id) == SlvAxiIDWidth) - `ASSERT_INIT(CorrectIdWidthMstAr, $bits(mst_req_o.ar.id) == SlvAxiIDWidth) - `ASSERT_INIT(CorrectIdWidthMstR, $bits(mst_resp_i.r.id) == SlvAxiIDWidth) -// pragma translate_on - - // other non degenerate cases - end else begin : gen_mux - - typedef logic [MstIdxBits-1:0] switch_id_t; - - // AXI channels between the ID prepend unit and the rest of the multiplexer - mst_aw_chan_t [NoSlvPorts-1:0] slv_aw_chans; - logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies; - w_chan_t [NoSlvPorts-1:0] slv_w_chans; - logic [NoSlvPorts-1:0] slv_w_valids, slv_w_readies; - mst_b_chan_t [NoSlvPorts-1:0] slv_b_chans; - logic [NoSlvPorts-1:0] slv_b_valids, slv_b_readies; - mst_ar_chan_t [NoSlvPorts-1:0] slv_ar_chans; - logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies; - mst_r_chan_t [NoSlvPorts-1:0] slv_r_chans; - logic [NoSlvPorts-1:0] slv_r_valids, slv_r_readies; - - // These signals are all ID prepended - // AW channel - mst_aw_chan_t mst_aw_chan; - logic mst_aw_valid, mst_aw_ready; - - // AW master handshake internal, so that we are able to stall, if w_fifo is full - logic aw_valid, aw_ready; - - // FF to lock the AW valid signal, when a new arbitration decision is made the decision - // gets pushed into the W FIFO, when it now stalls prevent subsequent pushing - // This FF removes AW to W dependency - logic lock_aw_valid_d, lock_aw_valid_q; - logic load_aw_lock; - - // signals for the FIFO that holds the last switching decision of the AW channel - logic w_fifo_full, w_fifo_empty; - logic w_fifo_push, w_fifo_pop; - switch_id_t w_fifo_data; - - // W channel spill reg - w_chan_t mst_w_chan; - logic mst_w_valid, mst_w_ready; - - // master ID in the b_id - switch_id_t switch_b_id; - - // B channel spill reg - mst_b_chan_t mst_b_chan; - logic mst_b_valid; - - // AR channel for when spill is enabled - mst_ar_chan_t mst_ar_chan; - logic ar_valid, ar_ready; - - // master ID in the r_id - switch_id_t switch_r_id; - - // R channel spill reg - mst_r_chan_t mst_r_chan; - logic mst_r_valid; - - //-------------------------------------- - // ID prepend for all slave ports - //-------------------------------------- - for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_id_prepend - axi_id_prepend #( - .NoBus ( 32'd1 ), // one AXI bus per slave port - .AxiIdWidthSlvPort( SlvAxiIDWidth ), - .AxiIdWidthMstPort( MstAxiIDWidth ), - .slv_aw_chan_t ( slv_aw_chan_t ), - .slv_w_chan_t ( w_chan_t ), - .slv_b_chan_t ( slv_b_chan_t ), - .slv_ar_chan_t ( slv_ar_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .mst_aw_chan_t ( mst_aw_chan_t ), - .mst_w_chan_t ( w_chan_t ), - .mst_b_chan_t ( mst_b_chan_t ), - .mst_ar_chan_t ( mst_ar_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ) - ) i_id_prepend ( - .pre_id_i ( switch_id_t'(i) ), - .slv_aw_chans_i ( slv_reqs_i[i].aw ), - .slv_aw_valids_i ( slv_reqs_i[i].aw_valid ), - .slv_aw_readies_o ( slv_resps_o[i].aw_ready ), - .slv_w_chans_i ( slv_reqs_i[i].w ), - .slv_w_valids_i ( slv_reqs_i[i].w_valid ), - .slv_w_readies_o ( slv_resps_o[i].w_ready ), - .slv_b_chans_o ( slv_resps_o[i].b ), - .slv_b_valids_o ( slv_resps_o[i].b_valid ), - .slv_b_readies_i ( slv_reqs_i[i].b_ready ), - .slv_ar_chans_i ( slv_reqs_i[i].ar ), - .slv_ar_valids_i ( slv_reqs_i[i].ar_valid ), - .slv_ar_readies_o ( slv_resps_o[i].ar_ready ), - .slv_r_chans_o ( slv_resps_o[i].r ), - .slv_r_valids_o ( slv_resps_o[i].r_valid ), - .slv_r_readies_i ( slv_reqs_i[i].r_ready ), - .mst_aw_chans_o ( slv_aw_chans[i] ), - .mst_aw_valids_o ( slv_aw_valids[i] ), - .mst_aw_readies_i ( slv_aw_readies[i] ), - .mst_w_chans_o ( slv_w_chans[i] ), - .mst_w_valids_o ( slv_w_valids[i] ), - .mst_w_readies_i ( slv_w_readies[i] ), - .mst_b_chans_i ( slv_b_chans[i] ), - .mst_b_valids_i ( slv_b_valids[i] ), - .mst_b_readies_o ( slv_b_readies[i] ), - .mst_ar_chans_o ( slv_ar_chans[i] ), - .mst_ar_valids_o ( slv_ar_valids[i] ), - .mst_ar_readies_i ( slv_ar_readies[i] ), - .mst_r_chans_i ( slv_r_chans[i] ), - .mst_r_valids_i ( slv_r_valids[i] ), - .mst_r_readies_o ( slv_r_readies[i] ) - ); - end - - //-------------------------------------- - // AW Channel - //-------------------------------------- - rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( mst_aw_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) - ) i_aw_arbiter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), - .rr_i ( '0 ), - .req_i ( slv_aw_valids ), - .gnt_o ( slv_aw_readies ), - .data_i ( slv_aw_chans ), - .gnt_i ( aw_ready ), - .req_o ( aw_valid ), - .data_o ( mst_aw_chan ), - .idx_o ( ) - ); - - // control of the AW channel - always_comb begin - // default assignments - lock_aw_valid_d = lock_aw_valid_q; - load_aw_lock = 1'b0; - w_fifo_push = 1'b0; - mst_aw_valid = 1'b0; - aw_ready = 1'b0; - // had a downstream stall, be valid and send the AW along - if (lock_aw_valid_q) begin - mst_aw_valid = 1'b1; - // transaction - if (mst_aw_ready) begin - aw_ready = 1'b1; - lock_aw_valid_d = 1'b0; - load_aw_lock = 1'b1; - end - end else begin - if (!w_fifo_full && aw_valid) begin - mst_aw_valid = 1'b1; - w_fifo_push = 1'b1; - if (mst_aw_ready) begin - aw_ready = 1'b1; - end else begin - // go to lock if transaction not in this cycle - lock_aw_valid_d = 1'b1; - load_aw_lock = 1'b1; - end - end - end - end - - `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) - - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( MaxWTrans ), - .dtype ( switch_id_t ) - ) i_w_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( 1'b0 ), - .testmode_i( test_i ), - .full_o ( w_fifo_full ), - .empty_o ( w_fifo_empty ), - .usage_o ( ), - .data_i ( mst_aw_chan.id[SlvAxiIDWidth+:MstIdxBits] ), - .push_i ( w_fifo_push ), - .data_o ( w_fifo_data ), - .pop_i ( w_fifo_pop ) - ); - - spill_register #( - .T ( mst_aw_chan_t ), - .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg - ) i_aw_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( mst_aw_valid ), - .ready_o ( mst_aw_ready ), - .data_i ( mst_aw_chan ), - .valid_o ( mst_req_o.aw_valid ), - .ready_i ( mst_resp_i.aw_ready ), - .data_o ( mst_req_o.aw ) - ); - - //-------------------------------------- - // W Channel - //-------------------------------------- - // multiplexer - assign mst_w_chan = slv_w_chans[w_fifo_data]; - always_comb begin - // default assignments - mst_w_valid = 1'b0; - slv_w_readies = '0; - w_fifo_pop = 1'b0; - // control - if (!w_fifo_empty) begin - // connect the handshake - mst_w_valid = slv_w_valids[w_fifo_data]; - slv_w_readies[w_fifo_data] = mst_w_ready; - // pop FIFO on a last transaction - w_fifo_pop = slv_w_valids[w_fifo_data] & mst_w_ready & mst_w_chan.last; - end - end - - spill_register #( - .T ( w_chan_t ), - .Bypass ( ~SpillW ) - ) i_w_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( mst_w_valid ), - .ready_o ( mst_w_ready ), - .data_i ( mst_w_chan ), - .valid_o ( mst_req_o.w_valid ), - .ready_i ( mst_resp_i.w_ready ), - .data_o ( mst_req_o.w ) - ); - - //-------------------------------------- - // B Channel - //-------------------------------------- - // replicate B channels - assign slv_b_chans = {NoSlvPorts{mst_b_chan}}; - // control B channel handshake - assign switch_b_id = mst_b_chan.id[SlvAxiIDWidth+:MstIdxBits]; - assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0; - - spill_register #( - .T ( mst_b_chan_t ), - .Bypass ( ~SpillB ) - ) i_b_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( mst_resp_i.b_valid ), - .ready_o ( mst_req_o.b_ready ), - .data_i ( mst_resp_i.b ), - .valid_o ( mst_b_valid ), - .ready_i ( slv_b_readies[switch_b_id] ), - .data_o ( mst_b_chan ) - ); - - //-------------------------------------- - // AR Channel - //-------------------------------------- - rr_arb_tree #( - .NumIn ( NoSlvPorts ), - .DataType ( mst_ar_chan_t ), - .AxiVldRdy( 1'b1 ), - .LockIn ( 1'b1 ) - ) i_ar_arbiter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i( 1'b0 ), - .rr_i ( '0 ), - .req_i ( slv_ar_valids ), - .gnt_o ( slv_ar_readies ), - .data_i ( slv_ar_chans ), - .gnt_i ( ar_ready ), - .req_o ( ar_valid ), - .data_o ( mst_ar_chan ), - .idx_o ( ) - ); - - spill_register #( - .T ( mst_ar_chan_t ), - .Bypass ( ~SpillAr ) - ) i_ar_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( ar_valid ), - .ready_o ( ar_ready ), - .data_i ( mst_ar_chan ), - .valid_o ( mst_req_o.ar_valid ), - .ready_i ( mst_resp_i.ar_ready ), - .data_o ( mst_req_o.ar ) - ); - - //-------------------------------------- - // R Channel - //-------------------------------------- - // replicate R channels - assign slv_r_chans = {NoSlvPorts{mst_r_chan}}; - // R channel handshake control - assign switch_r_id = mst_r_chan.id[SlvAxiIDWidth+:MstIdxBits]; - assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0; - - spill_register #( - .T ( mst_r_chan_t ), - .Bypass ( ~SpillR ) - ) i_r_spill_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( mst_resp_i.r_valid ), - .ready_o ( mst_req_o.r_ready ), - .data_i ( mst_resp_i.r ), - .valid_o ( mst_r_valid ), - .ready_i ( slv_r_readies[switch_r_id] ), - .data_o ( mst_r_chan ) - ); - end + axi_mcast_mux #( + .SlvAxiIDWidth(SlvAxiIDWidth), + .slv_aw_chan_t(slv_aw_chan_t), + .mst_aw_chan_t(mst_aw_chan_t), + .w_chan_t (w_chan_t), + .slv_b_chan_t (slv_b_chan_t), + .mst_b_chan_t (mst_b_chan_t), + .slv_ar_chan_t(slv_ar_chan_t), + .mst_ar_chan_t(mst_ar_chan_t), + .slv_r_chan_t (slv_r_chan_t), + .mst_r_chan_t (mst_r_chan_t), + .slv_req_t (slv_req_t), + .slv_resp_t (slv_resp_t), + .mst_req_t (mst_req_t), + .mst_resp_t (mst_resp_t), + .NoSlvPorts (NoSlvPorts), + .MaxWTrans (MaxWTrans), + .FallThrough (FallThrough), + .SpillAw (SpillAw), + .SpillW (SpillW), + .SpillB (SpillB), + .SpillAr (SpillAr), + .SpillR (SpillR) + ) i_axi_mcast_mux ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_is_mcast_i ('0), + .slv_aw_commit_i('0), + .slv_reqs_i (slv_reqs_i), + .slv_resps_o (slv_resps_o), + .mst_req_o (mst_req_o), + .mst_resp_i (mst_resp_i) + ); -// pragma translate_off -`ifndef VERILATOR - initial begin - assert (SlvAxiIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!"); - assert (NoSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!"); - assert (MaxWTrans > 0) - else $fatal(1, "Maximum number of outstanding writes must be non-zero!"); - assert (MstAxiIDWidth >= SlvAxiIDWidth + $clog2(NoSlvPorts)) - else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!"); - // Assert ID widths (one slave is sufficient since they all have the same type). - assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvAxiIDWidth) - else $fatal(1, "ID width of AW channel of slave ports does not match parameter!"); - assert ($unsigned($bits(slv_reqs_i[0].ar.id)) == SlvAxiIDWidth) - else $fatal(1, "ID width of AR channel of slave ports does not match parameter!"); - assert ($unsigned($bits(slv_resps_o[0].b.id)) == SlvAxiIDWidth) - else $fatal(1, "ID width of B channel of slave ports does not match parameter!"); - assert ($unsigned($bits(slv_resps_o[0].r.id)) == SlvAxiIDWidth) - else $fatal(1, "ID width of R channel of slave ports does not match parameter!"); - assert ($unsigned($bits(mst_req_o.aw.id)) == MstAxiIDWidth) - else $fatal(1, "ID width of AW channel of master port is wrong!"); - assert ($unsigned($bits(mst_req_o.ar.id)) == MstAxiIDWidth) - else $fatal(1, "ID width of AR channel of master port is wrong!"); - assert ($unsigned($bits(mst_resp_i.b.id)) == MstAxiIDWidth) - else $fatal(1, "ID width of B channel of master port is wrong!"); - assert ($unsigned($bits(mst_resp_i.r.id)) == MstAxiIDWidth) - else $fatal(1, "ID width of R channel of master port is wrong!"); - end -`endif -// pragma translate_on endmodule // interface wrap @@ -518,7 +124,6 @@ module axi_mux_intf #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports AXI_BUS.Master mst // master port ); @@ -589,7 +194,6 @@ module axi_mux_intf #( ) i_axi_mux ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low - .test_i ( test_i ), // Test Mode enable .slv_reqs_i ( slv_reqs ), .slv_resps_o ( slv_resps ), .mst_req_o ( mst_req ), diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv index f14d6c36e..d3937433c 100644 --- a/src/axi_pkg.sv +++ b/src/axi_pkg.sv @@ -519,6 +519,12 @@ package axi_pkg; /// Each master port can have multiple rules, should have however at least one. /// If a transaction can not be routed the xbar will answer with an `axi_pkg::RESP_DECERR`. int unsigned NoAddrRules; + /// The number of address rules to be considered for multicasting, + /// assumed to be at the start of `addr_map_i`. + int unsigned NoMulticastRules; + /// Number of master ports of the crossbar which can be targets of a multicast request. + /// These are assumed to be connected at the lower indices. + int unsigned NoMulticastPorts; } xbar_cfg_t; /// Commonly used rule types for `axi_xbar` (64-bit addresses). diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv index 317faa062..5db18c77f 100644 --- a/src/axi_serializer.sv +++ b/src/axi_serializer.sv @@ -146,15 +146,15 @@ module axi_serializer #( mst_req_o.r_ready = slv_req_i.r_ready & ~rd_fifo_empty; end - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), // No fall-through as response has to come a cycle later anyway - .DEPTH ( MaxReadTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), // No fall-through as response has to come a cycle later anyway + .Depth ( MaxReadTxns ), + .data_t ( id_t ) ) i_rd_id_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( ar_id ), .push_i ( rd_fifo_push ), .full_o ( rd_fifo_full ), @@ -166,15 +166,15 @@ module axi_serializer #( // Assign as this condition is needed in FSM assign rd_fifo_pop = slv_resp_o.r_valid & slv_req_i.r_ready & slv_resp_o.r.last; - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MaxWriteTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MaxWriteTxns ), + .data_t ( id_t ) ) i_wr_id_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( slv_req_i.aw.id ), .push_i ( wr_fifo_push ), .full_o ( wr_fifo_full ), @@ -186,7 +186,7 @@ module axi_serializer #( // Assign as this condition is needed in FSM assign wr_fifo_pop = slv_resp_o.b_valid & slv_req_i.b_ready; - `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni) + `FF(state_q, state_d, AtopIdle, clk_i, rst_ni) // pragma translate_off `ifndef VERILATOR @@ -197,7 +197,7 @@ module axi_serializer #( assert (MaxWriteTxns >= 1) else $fatal(1, "Maximum number of write transactions must be >= 1!"); end -`ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (~rst_ni); aw_lost : assert property( @(posedge clk_i) (slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready)) diff --git a/src/axi_slave_compare.sv b/src/axi_slave_compare.sv index 6cda82e05..fd91b2a01 100644 --- a/src/axi_slave_compare.sv +++ b/src/axi_slave_compare.sv @@ -47,8 +47,6 @@ module axi_slave_compare #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Testmode - input logic testmode_i, /// AXI4+ATOP channel request in input axi_req_t axi_mst_req_i, /// AXI4+ATOP channel response out @@ -92,33 +90,36 @@ module axi_slave_compare #( logic w_ready_mst; logic ar_ready_mst; - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_mst_req_i.aw_valid ), .ready_o ( aw_ready_mst ), .valid_o ( { aw_valid_ref, aw_valid_test } ), .ready_i ( { aw_ready_ref, aw_ready_test } ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_mst_req_i.ar_valid ), .ready_o ( ar_ready_mst ), .valid_o ( { ar_valid_ref, ar_valid_test } ), .ready_i ( { ar_ready_ref, ar_ready_test } ) ); - stream_fork #( - .N_OUP ( 32'd2 ) + cc_stream_fork #( + .NumOup ( 32'd2 ) ) i_stream_fork_w ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( axi_mst_req_i.w_valid ), .ready_o ( w_ready_mst ), .valid_o ( { w_valid_ref, w_valid_test } ), @@ -170,7 +171,6 @@ module axi_slave_compare #( ) i_axi_bus_compare ( .clk_i, .rst_ni, - .testmode_i, .aw_mismatch_o, .w_mismatch_o, .b_mismatch_o, diff --git a/src/axi_test.sv b/src/axi_test.sv index a782422c2..b9ba8b8c2 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -15,6 +15,7 @@ // - Fabian Schuiki // - Thomas Benz // - Matheus Cavalcante +// - Luca Colagrande /// A set of testbench utilities for AXI interfaces. @@ -710,6 +711,8 @@ package axi_test; parameter bit UNIQUE_IDS = 1'b0, // guarantee that the ID of each transaction is // unique among all in-flight transactions in the // same direction + // Custom features + parameter bit ENABLE_MULTICAST = 1'b0, // Dependent parameters, do not override. parameter int AXI_STRB_WIDTH = DW/8, parameter int N_AXI_IDS = 2**IW, @@ -770,6 +773,8 @@ package axi_test; } traffic_shape[$]; int unsigned max_cprob; + int unsigned mcast_prob; + function new( virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AW), @@ -808,6 +813,13 @@ package axi_test; atop_resp_r = '0; endfunction + // Sets the probability to generate a transaction with a non-zero multicast mask. + // `prob` should be a percentage, as Questa 2022.3 doesn't support real types + // in SystemVerilog `dist` constraints. + function void set_multicast_probability(int unsigned prob); + mcast_prob = prob; + endfunction + function void add_memory_region(input addr_t addr_begin, input addr_t addr_end, input mem_type_t mem_type); mem_map.push_back({addr_begin, addr_end, mem_type}); endfunction @@ -867,6 +879,8 @@ package axi_test; automatic int unsigned mem_region_idx; automatic mem_region_t mem_region; automatic int cprob; + automatic bit mcast; + automatic addr_t mcast_mask; // No memory regions defined if (mem_map.size() == 0) begin @@ -964,11 +978,21 @@ package axi_test; ax_beat.ax_addr = axi_pkg::aligned_addr(addr, axi_pkg::size_t'(SIZE_ALIGN) ); rand_success = std::randomize(id); assert(rand_success); rand_success = std::randomize(qos); assert(rand_success); + // Randomize multicast mask. + if (ENABLE_MULTICAST && !is_read) begin + rand_success = std::randomize(mcast, mcast_mask) with { + mcast dist {0 := (100 - mcast_prob), 1 := mcast_prob}; + !mcast -> mcast_mask == 0; + mcast -> mcast_mask != 0; + }; assert(rand_success); + ax_beat.ax_user = mcast_mask; + end else begin + ax_beat.ax_user = user; + end // The random ID *must* be legalized with `legalize_id()` before the beat is sent! This is // currently done in the functions `create_aws()` and `send_ars()`. ax_beat.ax_id = id; ax_beat.ax_qos = qos; - ax_beat.ax_user = user; return ax_beat; endfunction @@ -980,6 +1004,13 @@ package axi_test; // We can emit ATOPs only if INCR bursts are allowed. $warning("ATOP suppressed because INCR bursts are disabled!"); beat.ax_atop[5:4] = 2'b00; + break; + end + if (ENABLE_MULTICAST && beat.ax_atop[5:4] != 2'b00 && beat.ax_user != '0) begin + // We can emit ATOPs only if current burst is not a multicast. + $warning("ATOP suppressed because burst is a multicast!"); + beat.ax_atop[5:4] = 2'b00; + break; end if (beat.ax_atop[5:4] != 2'b00) begin // ATOP // Determine `ax_atop`. @@ -1253,7 +1284,7 @@ package axi_test; automatic logic [AXI_STRB_WIDTH-1:0] rand_strb, strb_mask; addr = axi_pkg::beat_addr(aw_beat.ax_addr, aw_beat.ax_size, aw_beat.ax_len, aw_beat.ax_burst, i); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); @@ -1300,7 +1331,8 @@ package axi_test; aw_done = 1'b0; fork // Cache-Partition: randomize the patid - automatic user_t ax_user = rand_user(AX_USER_RANGE, AX_USER_RAND); + // Multicast: randomize each burst separately + automatic user_t ax_user = ENABLE_MULTICAST ? '0 : rand_user(AX_USER_RANGE, AX_USER_RAND); begin send_ars(n_reads, ax_user); ar_done = 1'b1; @@ -1416,7 +1448,7 @@ package axi_test; wait (ar_queue.size > 0); ar_beat = ar_queue.peek(); byte_addr = axi_pkg::aligned_addr(ar_beat.ax_addr, axi_pkg::size_t'($clog2(DW/8))); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(r_beat) may behave differently to r_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(r_beat); assert(rand_success); @@ -1516,7 +1548,7 @@ package axi_test; automatic logic rand_success; wait (b_wait_cnt > 0 && (aw_queue.size() != 0)); aw_beat = aw_queue.pop_front(); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(b_beat) may behave differently to b_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(b_beat); assert (rand_success); @@ -2613,7 +2645,8 @@ module axi_chan_logger #( parameter type w_chan_t = logic, // axi W type parameter type b_chan_t = logic, // axi B type parameter type ar_chan_t = logic, // axi AR type - parameter type r_chan_t = logic // axi R type + parameter type r_chan_t = logic, // axi R type + parameter bit ENABLE_MULTICAST = 1'b0 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low, when `1'b0` no sampling @@ -2643,6 +2676,10 @@ module axi_chan_logger #( localparam int unsigned IdWidth = $bits(aw_chan_i.id); localparam int unsigned NoIds = 2**IdWidth; + // addr width from channel + localparam int unsigned AddrWidth = $bits(aw_chan_i.addr); + typedef logic [AddrWidth-1:0] addr_t; + // queues for writes and reads aw_chan_t aw_queue[$]; w_chan_t w_queue[$]; @@ -2656,6 +2693,8 @@ module axi_chan_logger #( automatic int fd; automatic string log_file; automatic string log_str; + automatic addr_t aw_mcast_mask; + automatic addr_t aw_addr; // only execute when reset is high if (rst_ni) begin // AW channel @@ -2664,8 +2703,13 @@ module axi_chan_logger #( log_file = $sformatf("./axi_log/%s/write.log", LoggerName); fd = $fopen(log_file, "a"); if (fd) begin - log_str = $sformatf("%0t> ID: %h AW on channel: LEN: %d, ATOP: %b", - $time, aw_chan_i.id, aw_chan_i.len, aw_chan_i.atop); + aw_addr = aw_chan_i.addr; + if (ENABLE_MULTICAST) begin + aw_mcast_mask = aw_chan_i.user[AddrWidth-1:0]; + for (int i = 0; i < AddrWidth; i++) if (aw_mcast_mask[i]) aw_addr[i] = 1'bx; + end + log_str = $sformatf("%0t> ID: %h AW on channel: LEN: %d, ATOP: %b, ADDR: %b", + $time, aw_chan_i.id, aw_chan_i.len, aw_chan_i.atop, aw_addr); $fdisplay(fd, log_str); $fclose(fd); end diff --git a/src/axi_throttle.sv b/src/axi_throttle.sv index 3e7973a08..05f006b91 100644 --- a/src/axi_throttle.sv +++ b/src/axi_throttle.sv @@ -19,9 +19,9 @@ module axi_throttle #( /// AXI4+ATOP response type parameter type axi_rsp_t = logic, /// The width of the write credit counter (*DO NOT OVERWRITE*) - parameter int unsigned WCntWidth = cf_math_pkg::idx_width(MaxNumAwPending), + parameter int unsigned WCntWidth = cc_pkg::idx_width(MaxNumAwPending), /// The width of the read credit counter (*DO NOT OVERWRITE*) - parameter int unsigned RCntWidth = cf_math_pkg::idx_width(MaxNumArPending), + parameter int unsigned RCntWidth = cc_pkg::idx_width(MaxNumArPending), /// The type of the write credit counter (*DO NOT OVERWRITE*) parameter type w_credit_t = logic [WCntWidth-1:0], /// The type of the read credit counter (*DO NOT OVERWRITE*) @@ -56,11 +56,12 @@ module axi_throttle #( logic throttled_ar_ready; // limit Aw requests -> wait for b - stream_throttle #( + cc_stream_throttle #( .MaxNumPending ( MaxNumAwPending ) ) i_stream_throttle_aw ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .req_valid_i ( req_i.aw_valid ), .req_valid_o ( throttled_aw_valid ), .req_ready_i ( rsp_i.aw_ready ), @@ -71,11 +72,12 @@ module axi_throttle #( ); // limit Ar requests -> wait for r.last - stream_throttle #( + cc_stream_throttle #( .MaxNumPending ( MaxNumArPending ) ) i_stream_throttle_ar ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .req_valid_i ( req_i.ar_valid ), .req_valid_o ( throttled_ar_valid ), .req_ready_i ( rsp_i.ar_ready ), diff --git a/src/axi_to_axi_lite.sv b/src/axi_to_axi_lite.sv index ad2e41414..c42120484 100644 --- a/src/axi_to_axi_lite.sv +++ b/src/axi_to_axi_lite.sv @@ -31,7 +31,6 @@ module axi_to_axi_lite #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave port full AXI4+ATOP input full_req_t slv_req_i, output full_resp_t slv_resp_o, @@ -91,7 +90,6 @@ module axi_to_axi_lite #( ) i_axi_to_axi_lite_id_reflect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_i ( test_i ), .slv_req_i ( splitted_req ), .slv_resp_o ( splitted_resp ), .mst_req_o ( mst_req_o ), @@ -127,7 +125,6 @@ module axi_to_axi_lite_id_reflect #( ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic test_i, // Testmode enable // slave port full AXI input full_req_t slv_req_i, output full_resp_t slv_resp_o, @@ -165,15 +162,15 @@ module axi_to_axi_lite_id_reflect #( // Write ID reflection assign aw_push = mst_req_o.aw_valid & slv_resp_o.aw_ready; assign aw_pop = slv_resp_o.b_valid & mst_req_o.b_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( AxiMaxWriteTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( AxiMaxWriteTxns ), + .data_t ( id_t ) ) i_aw_id_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( aw_full ), .empty_o ( aw_empty ), .usage_o ( /*not used*/ ), @@ -186,15 +183,15 @@ module axi_to_axi_lite_id_reflect #( // Read ID reflection assign ar_push = mst_req_o.ar_valid & slv_resp_o.ar_ready; assign ar_pop = slv_resp_o.r_valid & mst_req_o.r_ready; - fifo_v3 #( - .FALL_THROUGH ( FallThrough ), - .DEPTH ( AxiMaxReadTxns ), - .dtype ( id_t ) + cc_fifo #( + .FallThrough ( FallThrough ), + .Depth ( AxiMaxReadTxns ), + .data_t ( id_t ) ) i_ar_id_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i( test_i ), .full_o ( ar_full ), .empty_o ( ar_empty ), .usage_o ( /*not used*/ ), @@ -262,7 +259,6 @@ module axi_to_axi_lite_intf #( ) ( input logic clk_i, input logic rst_ni, - input logic testmode_i, AXI_BUS.Slave slv, AXI_LITE.Master mst ); @@ -315,7 +311,6 @@ module axi_to_axi_lite_intf #( ) i_axi_to_axi_lite ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_i ( testmode_i ), // slave port full AXI4+ATOP .slv_req_i ( full_req ), .slv_resp_o ( full_resp ), diff --git a/src/axi_to_detailed_mem.sv b/src/axi_to_detailed_mem.sv index 376a48f07..16a64cec9 100644 --- a/src/axi_to_detailed_mem.sv +++ b/src/axi_to_detailed_mem.sv @@ -264,9 +264,9 @@ module axi_to_detailed_mem #( end // Arbitrate between reads and writes. - stream_mux #( - .DATA_T ( meta_t ), - .N_INP ( 32'd2 ) + cc_stream_mux #( + .data_t ( meta_t ), + .NumInp ( 32'd2 ) ) i_ax_mux ( .inp_data_i ({wr_meta, rd_meta }), .inp_valid_i ({wr_valid, rd_valid}), @@ -321,11 +321,12 @@ module axi_to_detailed_mem #( end // Fork arbitrated stream to meta data, memory requests, and R/B channel selection. - stream_fork #( - .N_OUP ( 32'd3 ) + cc_stream_fork #( + .NumOup ( 32'd3 ) ) i_fork ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( arb_valid ), .ready_o ( arb_ready ), .valid_o ({sel_valid, meta_valid, m2s_req_valid}), @@ -335,15 +336,15 @@ module axi_to_detailed_mem #( assign sel_b = meta.write & meta.last; assign sel_r = ~meta.write | meta.atop[5]; - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( 32'd1 + BufDepth ), - .T ( logic[1:0] ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( 32'd1 + BufDepth ), + .data_t ( logic[1:0] ) ) i_sel_buf ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ({sel_b, sel_r }), .valid_i ( sel_valid ), .ready_o ( sel_ready ), @@ -353,15 +354,15 @@ module axi_to_detailed_mem #( .usage_o ( /* unused */ ) ); - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DEPTH ( 32'd1 + BufDepth ), - .T ( meta_t ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .Depth ( 32'd1 + BufDepth ), + .data_t ( meta_t ) ) i_meta_buf ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .data_i ( meta ), .valid_i ( meta_valid ), .ready_o ( meta_ready ), @@ -470,8 +471,8 @@ module axi_to_detailed_mem #( // Join memory read data and meta data stream. logic mem_join_valid, mem_join_ready; - stream_join #( - .N_INP ( 32'd2 ) + cc_stream_join #( + .NumInp ( 32'd2 ) ) i_join ( .inp_valid_i ({m2s_resp_valid, meta_buf_valid}), .inp_ready_o ({m2s_resp_ready, meta_buf_ready}), @@ -480,11 +481,12 @@ module axi_to_detailed_mem #( ); // Dynamically fork the joined stream to B and R channels. - stream_fork_dynamic #( - .N_OUP ( 32'd2 ) + cc_stream_fork_dynamic #( + .NumOup ( 32'd2 ) ) i_fork_dynamic ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( mem_join_valid ), .ready_o ( mem_join_ready ), .sel_i ({sel_buf_b, sel_buf_r }), @@ -555,19 +557,19 @@ module axi_to_detailed_mem #( }; // Registers - `FFARN(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni) - `FFARN(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni) - `FFARN(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FFARN(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FFARN(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni) - `FFARN(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni) - `FFARN(collect_b_err_q, collect_b_err_d, '0, clk_i, rst_ni) - `FFARN(collect_b_exokay_q, collect_b_exokay_d, 1'b1, clk_i, rst_ni) + `FF(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni) + `FF(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni) + `FF(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni) + `FF(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni) + `FF(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni) + `FF(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni) + `FF(collect_b_err_q, collect_b_err_d, '0, clk_i, rst_ni) + `FF(collect_b_exokay_q, collect_b_exokay_d, 1'b1, clk_i, rst_ni) // Assertions // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assume property (@(posedge clk_i) axi_req_i.ar_valid && !axi_resp_o.ar_ready |=> $stable(axi_req_i.ar)) @@ -864,7 +866,7 @@ module mem_stream_to_banks_detailed #( assign mem_req_valid = req_i & cnt_req_ready; // Register - `FFARN(cnt_q, cnt_d, '0, clk_i, rst_ni) + `FF(cnt_q, cnt_d, '0, clk_i, rst_ni) end // Handle requests. @@ -875,16 +877,16 @@ module mem_stream_to_banks_detailed #( assign bank_req[i].strb = strb_i[i*BytesPerBank+:BytesPerBank]; assign bank_req[i].wuser = wuser_i; assign bank_req[i].we = we_i; - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DATA_WIDTH ( $bits(req_t) ), - .DEPTH ( OutFifoDepth ), - .T ( req_t ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .DataWidth ( $bits(req_t) ), + .Depth ( OutFifoDepth ), + .data_t ( req_t ) ) i_ft_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .usage_o (), .data_i ( bank_req[i] ), .valid_i ( req_valid ), @@ -921,15 +923,15 @@ module mem_stream_to_banks_detailed #( for (genvar i = 0; unsigned'(i) < NumBanks; i++) begin assign zero_strobe_on_input[i] = (strb_i[i*BytesPerBank+:BytesPerBank] == '0); end - fifo_v3 #( - .FALL_THROUGH ( 1'b0 ), - .DEPTH ( MaxTrans+1 ), - .DATA_WIDTH ( NumBanks ) + cc_fifo #( + .FallThrough ( 1'b0 ), + .Depth ( MaxTrans+1 ), + .DataWidth ( NumBanks ) ) i_dead_write_fifo ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( dead_write_fifo_full ), .empty_o ( dead_write_fifo_empty ), .usage_o ( ), @@ -948,15 +950,15 @@ module mem_stream_to_banks_detailed #( // Handle responses. for (genvar i = 0; unsigned'(i) < NumBanks; i++) begin : gen_resp_regs - stream_fifo #( - .FALL_THROUGH ( 1'b1 ), - .DATA_WIDTH ( $bits(oup_data_t) + $bits(oup_ruser_t) ), - .DEPTH ( MaxTrans ) + cc_stream_fifo #( + .FallThrough ( 1'b1 ), + .DataWidth ( $bits(oup_data_t) + $bits(oup_ruser_t) ), + .Depth ( MaxTrans ) ) i_ft_reg ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .usage_o (), .data_i ( {bank_rdata_i[i], bank_ruser_i[i]} ), .valid_i ( bank_rvalid_i[i] ), diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv index 548339f37..5a8db0a40 100644 --- a/src/axi_to_mem_banked.sv +++ b/src/axi_to_mem_banked.sv @@ -69,7 +69,6 @@ module axi_to_mem_banked #( /// Asynchronous reset, active low input logic rst_ni, /// Testmode enable - input logic test_i, /// AXI4+ATOP slave port, request struct input axi_req_t axi_req_i, /// AXI4+ATOP slave port, response struct @@ -101,7 +100,7 @@ module axi_to_mem_banked #( localparam int unsigned BankSelOffset = $clog2(MemDataWidth / 32'd8); /// Selection signal width of the xbar. This is the reason for power of two banks, otherwise /// There are holes in the address mapping. - localparam int unsigned BankSelWidth = cf_math_pkg::idx_width(MemNumBanks); + localparam int unsigned BankSelWidth = cc_pkg::idx_width(MemNumBanks); typedef logic [BankSelWidth-1:0] xbar_sel_t; // Typedef for defining the channels @@ -159,7 +158,6 @@ module axi_to_mem_banked #( ) i_axi_demux ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( axi_req_i ), .slv_aw_select_i ( WriteAccess ), .slv_ar_select_i ( ReadAccess ), @@ -240,12 +238,13 @@ module axi_to_mem_banked #( assign res_rdata[j] = mem_rdata_i[r_shift_oup.sel]; // Connect for the response data `MemLatency` cycles after a request was made to the xbar. - shift_reg #( - .dtype ( read_sel_t ), - .Depth ( MemLatency ) + cc_shift_register #( + .data_t ( read_sel_t ), + .Depth ( MemLatency ) ) i_shift_reg_rdata_mux ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .d_i ( r_shift_inp ), .d_o ( r_shift_oup ) ); @@ -255,7 +254,7 @@ module axi_to_mem_banked #( // Xbar to arbitrate data over the different memory banks xbar_payload_t [MemNumBanks-1:0] mem_payload; - stream_xbar #( + cc_stream_xbar #( .NumInp ( 32'd2 * BanksPerAxiChannel ), .NumOut ( MemNumBanks ), .payload_t ( xbar_payload_t ), @@ -266,7 +265,8 @@ module axi_to_mem_banked #( ) i_stream_xbar ( .clk_i, .rst_ni, - .flush_i ( 1'b0 ), + .clr_arb_i ( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .data_i ( inter_payload ), .sel_i ( inter_sel ), @@ -306,6 +306,7 @@ module axi_to_mem_banked #( // pragma translate_on endmodule + `include "axi/typedef.svh" `include "axi/assign.svh" /// AXI4+ATOP interface wrapper for `axi_to_mem` @@ -346,7 +347,6 @@ module axi_to_mem_banked_intf #( /// Asynchronous reset, active low input logic rst_ni, /// Testmode enable - input logic test_i, /// AXI4+ATOP slave port AXI_BUS.Slave slv, /// Memory bank request @@ -407,7 +407,6 @@ module axi_to_mem_banked_intf #( ) i_axi_to_mem_banked ( .clk_i, .rst_ni, - .test_i, .axi_to_mem_busy_o, .axi_req_i ( mem_axi_req ), .axi_resp_o ( mem_axi_resp ), @@ -432,4 +431,3 @@ module axi_to_mem_banked_intf #( `endif // pragma translate_on endmodule - diff --git a/src/axi_to_mem_interleaved.sv b/src/axi_to_mem_interleaved.sv index 94d2bbef0..b2cef75e9 100644 --- a/src/axi_to_mem_interleaved.sv +++ b/src/axi_to_mem_interleaved.sv @@ -48,7 +48,6 @@ module axi_to_mem_interleaved #( /// Asynchronous reset, active low. input logic rst_ni, /// Testmode enable - input logic test_i, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, /// AXI4+ATOP slave port, request input. @@ -113,7 +112,6 @@ module axi_to_mem_interleaved #( ) i_split_read_write ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( axi_req_i ), .slv_ar_select_i ( 1'b0 ), .slv_aw_select_i ( 1'b1 ), @@ -221,13 +219,13 @@ module axi_to_mem_interleaved #( assign r_axi_to_mem_gnt[i] = r_mem_gnt[i] & ~fifo_full[i]; // fine-grain arbitration - rr_arb_tree #( - .NumIn ( 2 ), - .DataType ( mem_req_payload_t ) + cc_rr_arb_tree #( + .NumIn ( 2 ), + .data_t ( mem_req_payload_t ) ) i_rr_arb_tree ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .flush_i ( 1'b0 ), + .clr_i ( 1'b0 ), .rr_i ( '0 ), .req_i ( { r_mem_req[i], w_mem_req[i] } ), .gnt_o ( { r_mem_gnt[i], w_mem_gnt[i] } ), @@ -239,14 +237,14 @@ module axi_to_mem_interleaved #( ); // back-routing store - fifo_v3 #( - .DATA_WIDTH ( 1 ), - .DEPTH ( BufDepth + 1 ) + cc_fifo #( + .DataWidth ( 1 ), + .Depth ( BufDepth + 1 ) ) i_fifo_v3_response_trgt_store ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .full_o ( fifo_full[i] ), .empty_o ( ), .usage_o ( ), @@ -294,7 +292,6 @@ module axi_to_mem_interleaved_intf #( /// Asynchronous reset, active low input logic rst_ni, /// Testmode enable - input logic test_i, /// Status output, busy flag of `axi_to_mem` output logic busy_o, /// AXI4+ATOP slave port @@ -350,7 +347,6 @@ module axi_to_mem_interleaved_intf #( ) i_axi_to_mem_interleaved ( .clk_i, .rst_ni, - .test_i, .busy_o, .axi_req_i ( mem_axi_req ), .axi_resp_o ( mem_axi_resp ), diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv index 3e98bda2e..df52d3c2a 100644 --- a/src/axi_to_mem_split.sv +++ b/src/axi_to_mem_split.sv @@ -51,7 +51,6 @@ module axi_to_mem_split #( /// Asynchronous reset, active low. input logic rst_ni, /// Testmode enable - input logic test_i, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, /// AXI4+ATOP slave port, request input. @@ -97,7 +96,6 @@ module axi_to_mem_split #( ) i_split_read_write ( .clk_i, .rst_ni, - .test_i, .slv_req_i ( axi_req_i ), .slv_ar_select_i ( 1'b0 ), .slv_aw_select_i ( 1'b1 ), @@ -197,7 +195,6 @@ module axi_to_mem_split_intf #( /// Asynchronous reset, active low. input logic rst_ni, /// Testmode enable - input logic test_i, /// See `axi_to_mem_split`, port `busy_o`. output logic busy_o, /// AXI4+ATOP slave interface port. @@ -246,7 +243,6 @@ module axi_to_mem_split_intf #( ) i_axi_to_mem_split ( .clk_i, .rst_ni, - .test_i, .busy_o, .axi_req_i (axi_req), .axi_resp_o (axi_resp), diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index 5baa854ba..a89987fcb 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -16,7 +16,7 @@ /// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. /// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. module axi_xbar -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( /// Configuration struct for the crossbar see `axi_pkg` for fields and definitions. parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -68,8 +68,6 @@ import cf_math_pkg::idx_width; input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, - /// Testmode enable, active high. - input logic test_i, /// AXI4+ATOP requests to the slave ports. input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, /// AXI4+ATOP responses of the slave ports. @@ -90,77 +88,53 @@ import cf_math_pkg::idx_width; input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i ); - // signals into the axi_muxes, are of type slave as the multiplexer extends the ID - slv_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - slv_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + rule_t [Cfg.NoSlvPorts-1:0] default_rules; + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_default_rules + assign default_rules[i] = '{ + idx: default_mst_port_i[i], + start_addr: '0, + end_addr: '0 + }; + end - axi_xbar_unmuxed #( - .Cfg (Cfg), - .ATOPs (ATOPs), - .Connectivity (Connectivity), - .aw_chan_t (slv_aw_chan_t), - .w_chan_t (w_chan_t), - .b_chan_t (slv_b_chan_t), - .ar_chan_t (slv_ar_chan_t), - .r_chan_t (slv_r_chan_t), - .req_t (slv_req_t), - .resp_t (slv_resp_t), - .rule_t (rule_t) - ) i_xbar_unmuxed ( - .clk_i, - .rst_ni, - .test_i, - .slv_ports_req_i, - .slv_ports_resp_o, - .mst_ports_req_o (mst_reqs), - .mst_ports_resp_i (mst_resps), - .addr_map_i, - .en_default_mst_port_i, - .default_mst_port_i + axi_mcast_xbar #( + .Cfg (Cfg), + .ATOPs (ATOPs), + .Connectivity (Connectivity), + .MulticastConnectivity('1), + .slv_aw_chan_t (slv_aw_chan_t), + .mst_aw_chan_t (mst_aw_chan_t), + .w_chan_t (w_chan_t), + .slv_b_chan_t (slv_b_chan_t), + .mst_b_chan_t (mst_b_chan_t), + .slv_ar_chan_t (slv_ar_chan_t), + .mst_ar_chan_t (mst_ar_chan_t), + .slv_r_chan_t (slv_r_chan_t), + .mst_r_chan_t (mst_r_chan_t), + .slv_req_t (slv_req_t), + .slv_resp_t (slv_resp_t), + .mst_req_t (mst_req_t), + .mst_resp_t (mst_resp_t), + .rule_t (rule_t) + ) i_axi_mcast_xbar ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_ports_req_i (slv_ports_req_i), + .slv_ports_resp_o (slv_ports_resp_o), + .mst_ports_req_o (mst_ports_req_o), + .mst_ports_resp_i (mst_ports_resp_i), + .addr_map_i (addr_map_i), + .en_default_mst_port_i(en_default_mst_port_i), + .default_mst_port_i (default_rules) ); - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux - axi_mux #( - .SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts ), // ID width of the slave ports - .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports - .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port - .w_chan_t ( w_chan_t ), // W Channel Type, all ports - .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports - .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port - .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports - .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port - .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports - .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ), - .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module - .MaxWTrans ( Cfg.MaxSlvTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[4] ), - .SpillW ( Cfg.LatencyMode[3] ), - .SpillB ( Cfg.LatencyMode[2] ), - .SpillAr ( Cfg.LatencyMode[1] ), - .SpillR ( Cfg.LatencyMode[0] ) - ) i_axi_mux ( - .clk_i, // Clock - .rst_ni, // Asynchronous reset active low - .test_i, // Test Mode enable - .slv_reqs_i ( mst_reqs[i] ), - .slv_resps_o ( mst_resps[i] ), - .mst_req_o ( mst_ports_req_o[i] ), - .mst_resp_i ( mst_ports_resp_i[i] ) - ); - end - endmodule `include "axi/assign.svh" `include "axi/typedef.svh" module axi_xbar_intf -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter int unsigned AXI_USER_WIDTH = 0, parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -172,7 +146,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_i, AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, @@ -239,7 +212,6 @@ import cf_math_pkg::idx_width; ) i_xbar ( .clk_i, .rst_ni, - .test_i, .slv_ports_req_i (slv_reqs ), .slv_ports_resp_o (slv_resps), .mst_ports_req_o (mst_reqs ), diff --git a/src/axi_xbar_unmuxed.sv b/src/axi_xbar_unmuxed.sv index 73e50975c..c672213d5 100644 --- a/src/axi_xbar_unmuxed.sv +++ b/src/axi_xbar_unmuxed.sv @@ -16,7 +16,7 @@ /// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. /// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. module axi_xbar_unmuxed -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( /// Configuration struct for the crossbar see `axi_pkg` for fields and definitions. parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -56,8 +56,6 @@ import cf_math_pkg::idx_width; input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, - /// Testmode enable, active high. - input logic test_i, /// AXI4+ATOP requests to the slave ports. input req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, /// AXI4+ATOP responses of the slave ports. @@ -69,286 +67,46 @@ import cf_math_pkg::idx_width; /// Address map array input for the crossbar. This map is global for the whole module. /// It is used for routing the transactions to the respective master ports. /// Each master port can have multiple different rules. - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, /// Enable default master port. - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, + input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, /// Enables a default master port for each slave port. When this is enabled unmapped /// transactions get issued at the master port given by `default_mst_port_i`. /// When not used, tie to `'0`. - input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i + input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0] default_mst_port_i ); - // Address tpye for inidvidual address signals - typedef logic [Cfg.AxiAddrWidth-1:0] addr_t; - // to account for the decoding error slave - localparam int unsigned MstPortsIdxWidthOne = - (Cfg.NoMstPorts == 32'd1) ? 32'd1 : unsigned'($clog2(Cfg.NoMstPorts + 1)); - typedef logic [MstPortsIdxWidthOne-1:0] mst_port_idx_t; - - // signals from the axi_demuxes, one index more for decode error - req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; - resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; - - // workaround for issue #133 (problem with vsim 10.6c) - localparam int unsigned cfg_NoMstPorts = Cfg.NoMstPorts; - - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux - logic [MstPortsIdxWidth-1:0] dec_aw, dec_ar; - mst_port_idx_t slv_aw_select, slv_ar_select; - logic dec_aw_valid, dec_aw_error; - logic dec_ar_valid, dec_ar_error; - - addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .NoRules ( Cfg.NoAddrRules ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) - ) i_axi_aw_decode ( - .addr_i ( slv_ports_req_i[i].aw.addr ), - .addr_map_i ( addr_map_i ), - .idx_o ( dec_aw ), - .dec_valid_o ( dec_aw_valid ), - .dec_error_o ( dec_aw_error ), - .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) - ); - - addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .addr_t ( addr_t ), - .NoRules ( Cfg.NoAddrRules ), - .rule_t ( rule_t ) - ) i_axi_ar_decode ( - .addr_i ( slv_ports_req_i[i].ar.addr ), - .addr_map_i ( addr_map_i ), - .idx_o ( dec_ar ), - .dec_valid_o ( dec_ar_valid ), - .dec_error_o ( dec_ar_error ), - .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) - ); - - assign slv_aw_select = (dec_aw_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_aw); - assign slv_ar_select = (dec_ar_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_ar); - - // make sure that the default slave does not get changed, if there is an unserved Ax - // pragma translate_off - `ifndef VERILATOR - `ifndef XSIM - default disable iff (~rst_ni); - default_aw_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) - |=> $stable(en_default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - enable, when there is an unserved Aw beat. Slave Port: %0d", i)); - default_aw_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) - |=> $stable(default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - when there is an unserved Aw beat. Slave Port: %0d", i)); - default_ar_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready) - |=> $stable(en_default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the enable, when\ - there is an unserved Ar beat. Slave Port: %0d", i)); - default_ar_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready) - |=> $stable(default_mst_port_i[i])) - else $fatal (1, $sformatf("It is not allowed to change the default mst port\ - when there is an unserved Ar beat. Slave Port: %0d", i)); - `endif - `endif - // pragma translate_on - axi_demux #( - .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), // ID Width - .AtopSupport ( ATOPs ), - .aw_chan_t ( aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( b_chan_t ), // B Channel Type - .ar_chan_t ( ar_chan_t ), // AR Channel Type - .r_chan_t ( r_chan_t ), // R Channel Type - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), - .NoMstPorts ( Cfg.NoMstPorts + 1 ), - .MaxTrans ( Cfg.MaxMstTrans ), - .AxiLookBits ( Cfg.AxiIdUsedSlvPorts ), - .UniqueIds ( Cfg.UniqueIds ), - .SpillAw ( Cfg.LatencyMode[9] ), - .SpillW ( Cfg.LatencyMode[8] ), - .SpillB ( Cfg.LatencyMode[7] ), - .SpillAr ( Cfg.LatencyMode[6] ), - .SpillR ( Cfg.LatencyMode[5] ) - ) i_axi_demux ( - .clk_i, // Clock - .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable - .slv_req_i ( slv_ports_req_i[i] ), - .slv_aw_select_i ( slv_aw_select ), - .slv_ar_select_i ( slv_ar_select ), - .slv_resp_o ( slv_ports_resp_o[i] ), - .mst_reqs_o ( slv_reqs[i] ), - .mst_resps_i ( slv_resps[i] ) - ); - - axi_err_slv #( - .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), - .Resp ( axi_pkg::RESP_DECERR ), - .ATOPs ( ATOPs ), - .MaxTrans ( 4 ) // Transactions terminate at this slave, so minimize - // resource consumption by accepting only a few - // transactions at a time. - ) i_axi_err_slv ( - .clk_i, // Clock - .rst_ni, // Asynchronous reset active low - .test_i, // Testmode enable - // slave port - .slv_req_i ( slv_reqs[i][Cfg.NoMstPorts] ), - .slv_resp_o ( slv_resps[i][cfg_NoMstPorts] ) - ); - end - - // cross all channels - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_xbar_slv_cross - for (genvar j = 0; j < Cfg.NoMstPorts; j++) begin : gen_xbar_mst_cross - if (Connectivity[i][j]) begin : gen_connection - axi_multicut #( - .NoCuts ( Cfg.PipelineStages ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ) - ) i_axi_multicut_xbar_pipeline ( - .clk_i, - .rst_ni, - .slv_req_i ( slv_reqs[i][j] ), - .slv_resp_o ( slv_resps[i][j] ), - .mst_req_o ( mst_ports_req_o[j][i] ), - .mst_resp_i ( mst_ports_resp_i[j][i] ) - ); - - end else begin : gen_no_connection - assign mst_ports_req_o[j][i] = '0; - axi_err_slv #( - .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), - .axi_req_t ( req_t ), - .axi_resp_t ( resp_t ), - .Resp ( axi_pkg::RESP_DECERR ), - .ATOPs ( ATOPs ), - .MaxTrans ( 1 ) - ) i_axi_err_slv ( - .clk_i, - .rst_ni, - .test_i, - .slv_req_i ( slv_reqs[i][j] ), - .slv_resp_o ( slv_resps[i][j] ) - ); - end - end + rule_t [Cfg.NoSlvPorts-1:0] default_rules; + for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_default_rules + assign default_rules[i] = '{ + idx: default_mst_port_i[i], + start_addr: '0, + end_addr: '0 + }; end - // pragma translate_off - `ifndef VERILATOR - `ifndef XSIM - initial begin : check_params - id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else - $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); - id_slv_resp_ports: assert ($bits(slv_ports_resp_o[0].r.id) == Cfg.AxiIdWidthSlvPorts) else - $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); - end - `endif - `endif - // pragma translate_on -endmodule - -`ifndef VCS -`ifndef TARGET_GENUS -// As of now, VCS and Genus does not support multi-dimensional array of interfaces. -`include "axi/assign.svh" -`include "axi/typedef.svh" - -module axi_xbar_unmuxed_intf -import cf_math_pkg::idx_width; -#( - parameter int unsigned AXI_USER_WIDTH = 0, - parameter axi_pkg::xbar_cfg_t Cfg = '0, - parameter bit ATOPS = 1'b1, - parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1, - parameter type rule_t = axi_pkg::xbar_rule_64_t -) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], - AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0], - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i -); - - typedef logic [Cfg.AxiIdWidthSlvPorts -1:0] id_t; - typedef logic [Cfg.AxiAddrWidth -1:0] addr_t; - typedef logic [Cfg.AxiDataWidth -1:0] data_t; - typedef logic [Cfg.AxiDataWidth/8 -1:0] strb_t; - typedef logic [AXI_USER_WIDTH -1:0] user_t; - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) - - req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; - req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - resp_t [Cfg.NoSlvPorts-1:0] slv_resps; - - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst - for (genvar j = 0; j < Cfg.NoSlvPorts; j++) begin : gen_assign_mst_inner - `AXI_ASSIGN_FROM_REQ(mst_ports[i][j], mst_reqs[i][j]) - `AXI_ASSIGN_TO_RESP(mst_resps[i][j], mst_ports[i][j]) - end - end - - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv - `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) - `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) - end - - axi_xbar_unmuxed #( - .Cfg ( Cfg ), - .ATOPs ( ATOPS ), - .Connectivity ( CONNECTIVITY ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( r_chan_t ), - .req_t ( req_t ), - .resp_t ( resp_t ), - .rule_t ( rule_t ) - ) i_xbar ( - .clk_i, - .rst_ni, - .test_i, - .slv_ports_req_i (slv_reqs ), - .slv_ports_resp_o (slv_resps), - .mst_ports_req_o (mst_reqs ), - .mst_ports_resp_i (mst_resps), - .addr_map_i, - .en_default_mst_port_i, - .default_mst_port_i + axi_mcast_xbar_unmuxed #( + .Cfg (Cfg), + .ATOPs (ATOPs), + .Connectivity (Connectivity), + .aw_chan_t (aw_chan_t), + .w_chan_t (w_chan_t), + .b_chan_t (b_chan_t), + .ar_chan_t (ar_chan_t), + .r_chan_t (r_chan_t), + .req_t (req_t), + .resp_t (resp_t), + .rule_t (rule_t) + ) i_axi_mcast_xbar_unmuxed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_ports_req_i (slv_ports_req_i), + .slv_ports_resp_o (slv_ports_resp_o), + .mst_ports_req_o (mst_ports_req_o), + .mst_ports_resp_i (mst_ports_resp_i), + .addr_map_i (addr_map_i), + .en_default_mst_port_i(en_default_mst_port_i), + .default_mst_port_i (default_rules) ); endmodule - -`endif -`endif diff --git a/src/axi_xp.sv b/src/axi_xp.sv index 5ccbfb9ff..b0af8c4b0 100644 --- a/src/axi_xp.sv +++ b/src/axi_xp.sv @@ -84,8 +84,6 @@ module axi_xp #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, - /// Test mode enable - input logic test_en_i, /// Slave ports request input axi_req_t [NumSlvPorts-1:0] slv_req_i, /// Slave ports response @@ -135,7 +133,6 @@ module axi_xp #( ) i_xbar ( .clk_i, .rst_ni, - .test_i ( test_en_i ), .slv_ports_req_i ( slv_req_i ), .slv_ports_resp_o ( slv_resp_o ), .mst_ports_req_o ( xbar_req ), @@ -171,7 +168,7 @@ endmodule `include "axi/typedef.svh" module axi_xp_intf -import cf_math_pkg::idx_width; +import cc_pkg::idx_width; #( parameter bit ATOPs = 1'b1, parameter axi_pkg::xbar_cfg_t Cfg = '0, @@ -192,7 +189,6 @@ import cf_math_pkg::idx_width; ) ( input logic clk_i, input logic rst_ni, - input logic test_en_i, AXI_BUS.Slave slv_ports [NumSlvPorts-1:0], AXI_BUS.Master mst_ports [NumMstPorts-1:0], input rule_t [NumAddrRules-1:0] addr_map_i @@ -245,7 +241,6 @@ import cf_math_pkg::idx_width; ) i_xp ( .clk_i, .rst_ni, - .test_en_i, .slv_req_i (slv_reqs ), .slv_resp_o (slv_resps), .mst_req_o (mst_reqs ), diff --git a/test/axi_synth_bench.sv b/test/axi_synth_bench.sv index 334846abc..34372e88b 100644 --- a/test/axi_synth_bench.sv +++ b/test/axi_synth_bench.sv @@ -13,6 +13,7 @@ // - Andreas Kurth // - Fabian Schuiki // - Michael Rogenmoser +// - Luca Colagrande /// A synthesis test bench which instantiates various adapter variants. module axi_synth_bench ( @@ -241,7 +242,6 @@ module synth_slice #( ) a ( .clk_i (clk_i), .rst_ni (rst_ni), - .testmode_i (1'b0), .slv (a_full.Slave), .mst (a_lite.Master) ); @@ -434,7 +434,6 @@ module synth_axi_lite_xbar #( }; axi_pkg::xbar_rule_32_t [NoSlvMst-1:0] addr_map; - logic test; axi_req_t [NoSlvMst-1:0] mst_reqs, slv_reqs; axi_resp_t [NoSlvMst-1:0] mst_resps, slv_resps; @@ -451,7 +450,6 @@ module synth_axi_lite_xbar #( ) i_xbar_dut ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_i ( test ), .slv_ports_req_i ( mst_reqs ), .slv_ports_resp_o ( mst_resps ), .mst_ports_req_o ( slv_reqs ), @@ -477,7 +475,6 @@ module synth_axi_lite_mailbox #( .AXI_DATA_WIDTH (32'd32) ) slv [1:0] (); - logic test; logic [1:0] irq; addr_t [1:0] base_addr; @@ -490,7 +487,6 @@ module synth_axi_lite_mailbox #( ) i_axi_lite_mailbox ( .clk_i ( clk_i ), // Clock .rst_ni ( rst_ni ), // Asynchronous reset active low - .test_i ( test ), // Testmode enable // slave ports [1:0] .slv ( slv ), .irq_o ( irq ), // interrupt output for each port @@ -720,7 +716,6 @@ module synth_axi_to_mem_banked #( ) axi (); // Misc signals - logic test; logic [1:0] axi_to_mem_busy; // Signals for mem macros logic [BankNum-1:0] mem_req; @@ -745,7 +740,6 @@ module synth_axi_to_mem_banked #( ) i_axi_to_mem_banked_intf ( .clk_i, .rst_ni, - .test_i ( test ), .slv ( axi ), .mem_req_o ( mem_req ), .mem_gnt_i ( mem_gnt ), @@ -793,3 +787,1011 @@ module synth_axi_lite_dw_converter #( ); endmodule + + +module synth_axi_xbar #( + parameter int unsigned NoSlvMst = 32'd8, // Max 16, as the addr rules defined below + parameter bit EnableMulticast = 0, + parameter bit UniqueIds = 0, + parameter axi_pkg::xbar_latency_e LatencyMode = axi_pkg::NO_LATENCY, + // axi configuration + parameter int unsigned AxiIdWidthMasters = 4, + parameter int unsigned AxiIdUsed = 3, // Has to be <= AxiIdWidthMasters + parameter int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoSlvMst), + parameter int unsigned AxiAddrWidth = 32, // Axi Address Width + parameter int unsigned AxiDataWidth = 32, // Axi Data Width + parameter int unsigned AxiStrbWidth = AxiDataWidth / 8, + parameter int unsigned AxiUserWidth = 1, + parameter int unsigned AxiAwUserWidth = EnableMulticast ? AxiAddrWidth : 1, + // axi types + parameter type id_mst_t = logic [AxiIdWidthSlaves-1:0], + parameter type id_slv_t = logic [AxiIdWidthMasters-1:0], + parameter type addr_t = logic [AxiAddrWidth-1:0], + parameter type data_t = logic [AxiDataWidth-1:0], + parameter type strb_t = logic [AxiStrbWidth-1:0], + parameter type user_t = logic [AxiUserWidth-1:0], + parameter type aw_user_t = struct packed {logic [AxiAwUserWidth-1:0] mcast;} +) ( + input logic clk_i, + input logic rst_ni, + + //////////////////////////////// + // Slave ports request inputs // + //////////////////////////////// + + // AW + input id_slv_t [NoSlvMst-1:0] slv_aw_id, + input addr_t [NoSlvMst-1:0] slv_aw_addr, + input axi_pkg::len_t [NoSlvMst-1:0] slv_aw_len, + input axi_pkg::size_t [NoSlvMst-1:0] slv_aw_size, + input axi_pkg::burst_t [NoSlvMst-1:0] slv_aw_burst, + input logic [NoSlvMst-1:0] slv_aw_lock, + input axi_pkg::cache_t [NoSlvMst-1:0] slv_aw_cache, + input axi_pkg::prot_t [NoSlvMst-1:0] slv_aw_prot, + input axi_pkg::qos_t [NoSlvMst-1:0] slv_aw_qos, + input axi_pkg::region_t [NoSlvMst-1:0] slv_aw_region, + input axi_pkg::atop_t [NoSlvMst-1:0] slv_aw_atop, + input aw_user_t [NoSlvMst-1:0] slv_aw_user, + input logic [NoSlvMst-1:0] slv_aw_valid, + // W + input data_t [NoSlvMst-1:0] slv_w_data, + input strb_t [NoSlvMst-1:0] slv_w_strb, + input logic [NoSlvMst-1:0] slv_w_last, + input user_t [NoSlvMst-1:0] slv_w_user, + input logic [NoSlvMst-1:0] slv_w_valid, + // B + input logic [NoSlvMst-1:0] slv_b_ready, + // AR + input id_slv_t [NoSlvMst-1:0] slv_ar_id, + input addr_t [NoSlvMst-1:0] slv_ar_addr, + input axi_pkg::len_t [NoSlvMst-1:0] slv_ar_len, + input axi_pkg::size_t [NoSlvMst-1:0] slv_ar_size, + input axi_pkg::burst_t [NoSlvMst-1:0] slv_ar_burst, + input logic [NoSlvMst-1:0] slv_ar_lock, + input axi_pkg::cache_t [NoSlvMst-1:0] slv_ar_cache, + input axi_pkg::prot_t [NoSlvMst-1:0] slv_ar_prot, + input axi_pkg::qos_t [NoSlvMst-1:0] slv_ar_qos, + input axi_pkg::region_t [NoSlvMst-1:0] slv_ar_region, + input user_t [NoSlvMst-1:0] slv_ar_user, + input logic [NoSlvMst-1:0] slv_ar_valid, + // R + input logic [NoSlvMst-1:0] slv_r_ready, + + ////////////////////////////////// + // Slave ports response outputs // + ////////////////////////////////// + + // AW + output logic [NoSlvMst-1:0] slv_aw_ready, + // AR + output logic [NoSlvMst-1:0] slv_ar_ready, + // W + output logic [NoSlvMst-1:0] slv_w_ready, + // B + output logic [NoSlvMst-1:0] slv_b_valid, + output id_slv_t [NoSlvMst-1:0] slv_b_id, + output axi_pkg::resp_t [NoSlvMst-1:0] slv_b_resp, + output user_t [NoSlvMst-1:0] slv_b_user, + // R + output logic [NoSlvMst-1:0] slv_r_valid, + output id_slv_t [NoSlvMst-1:0] slv_r_id, + output data_t [NoSlvMst-1:0] slv_r_data, + output axi_pkg::resp_t [NoSlvMst-1:0] slv_r_resp, + output logic [NoSlvMst-1:0] slv_r_last, + output user_t [NoSlvMst-1:0] slv_r_user, + + ////////////////////////////////// + // Master ports request outputs // + ////////////////////////////////// + + // AW + output id_mst_t [NoSlvMst-1:0] mst_aw_id, + output addr_t [NoSlvMst-1:0] mst_aw_addr, + output axi_pkg::len_t [NoSlvMst-1:0] mst_aw_len, + output axi_pkg::size_t [NoSlvMst-1:0] mst_aw_size, + output axi_pkg::burst_t [NoSlvMst-1:0] mst_aw_burst, + output logic [NoSlvMst-1:0] mst_aw_lock, + output axi_pkg::cache_t [NoSlvMst-1:0] mst_aw_cache, + output axi_pkg::prot_t [NoSlvMst-1:0] mst_aw_prot, + output axi_pkg::qos_t [NoSlvMst-1:0] mst_aw_qos, + output axi_pkg::region_t [NoSlvMst-1:0] mst_aw_region, + output axi_pkg::atop_t [NoSlvMst-1:0] mst_aw_atop, + output aw_user_t [NoSlvMst-1:0] mst_aw_user, + output logic [NoSlvMst-1:0] mst_aw_valid, + // W + output data_t [NoSlvMst-1:0] mst_w_data, + output strb_t [NoSlvMst-1:0] mst_w_strb, + output logic [NoSlvMst-1:0] mst_w_last, + output user_t [NoSlvMst-1:0] mst_w_user, + output logic [NoSlvMst-1:0] mst_w_valid, + // B + output logic [NoSlvMst-1:0] mst_b_ready, + // AR + output id_mst_t [NoSlvMst-1:0] mst_ar_id, + output addr_t [NoSlvMst-1:0] mst_ar_addr, + output axi_pkg::len_t [NoSlvMst-1:0] mst_ar_len, + output axi_pkg::size_t [NoSlvMst-1:0] mst_ar_size, + output axi_pkg::burst_t [NoSlvMst-1:0] mst_ar_burst, + output logic [NoSlvMst-1:0] mst_ar_lock, + output axi_pkg::cache_t [NoSlvMst-1:0] mst_ar_cache, + output axi_pkg::prot_t [NoSlvMst-1:0] mst_ar_prot, + output axi_pkg::qos_t [NoSlvMst-1:0] mst_ar_qos, + output axi_pkg::region_t [NoSlvMst-1:0] mst_ar_region, + output user_t [NoSlvMst-1:0] mst_ar_user, + output logic [NoSlvMst-1:0] mst_ar_valid, + // R + output logic [NoSlvMst-1:0] mst_r_ready, + + ////////////////////////////////// + // Master ports response inputs // + ////////////////////////////////// + + // AW + input logic [NoSlvMst-1:0] mst_aw_ready, + // AR + input logic [NoSlvMst-1:0] mst_ar_ready, + // W + input logic [NoSlvMst-1:0] mst_w_ready, + // B + input logic [NoSlvMst-1:0] mst_b_valid, + input id_mst_t [NoSlvMst-1:0] mst_b_id, + input axi_pkg::resp_t [NoSlvMst-1:0] mst_b_resp, + input user_t [NoSlvMst-1:0] mst_b_user, + // R + input logic [NoSlvMst-1:0] mst_r_valid, + input id_mst_t [NoSlvMst-1:0] mst_r_id, + input data_t [NoSlvMst-1:0] mst_r_data, + input axi_pkg::resp_t [NoSlvMst-1:0] mst_r_resp, + input logic [NoSlvMst-1:0] mst_r_last, + input user_t [NoSlvMst-1:0] mst_r_user + +); + + localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ + NoSlvPorts: NoSlvMst, + NoMstPorts: NoSlvMst, + MaxMstTrans: 10, + MaxSlvTrans: 6, + FallThrough: 1'b0, + LatencyMode: LatencyMode, + PipelineStages: 0, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + UniqueIds: UniqueIds, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoSlvMst, + NoMulticastRules: EnableMulticast ? NoSlvMst : 0, + NoMulticastPorts: EnableMulticast ? NoSlvMst : 0 + }; + + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, aw_user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) + + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + // Each slave has its own address range: + localparam rule_t [xbar_cfg.NoAddrRules-1:0] addr_map = addr_map_gen(); + + function rule_t [xbar_cfg.NoAddrRules-1:0] addr_map_gen (); + for (int unsigned i = 0; i < xbar_cfg.NoAddrRules; i++) begin + addr_map_gen[i] = rule_t'{ + idx: unsigned'(i), + start_addr: i * 32'h0000_2000, + end_addr: (i+1) * 32'h0000_2000, + default: '0 + }; + end + endfunction + + slv_req_t [NoSlvMst-1:0] slv_reqs; + mst_req_t [NoSlvMst-1:0] mst_reqs; + slv_resp_t [NoSlvMst-1:0] slv_resps; + mst_resp_t [NoSlvMst-1:0] mst_resps; + + // Connect XBAR interfaces + generate + for (genvar i = 0; i < NoSlvMst; i++) begin : g_connect_slv_port + // Request + assign slv_reqs[i].aw.id = slv_aw_id[i]; + assign slv_reqs[i].aw.addr = slv_aw_addr[i]; + assign slv_reqs[i].aw.len = slv_aw_len[i]; + assign slv_reqs[i].aw.size = slv_aw_size[i]; + assign slv_reqs[i].aw.burst = slv_aw_burst[i]; + assign slv_reqs[i].aw.lock = slv_aw_lock[i]; + assign slv_reqs[i].aw.cache = slv_aw_cache[i]; + assign slv_reqs[i].aw.prot = slv_aw_prot[i]; + assign slv_reqs[i].aw.qos = slv_aw_qos[i]; + assign slv_reqs[i].aw.region = slv_aw_region[i]; + assign slv_reqs[i].aw.atop = slv_aw_atop[i]; + assign slv_reqs[i].aw.user = slv_aw_user[i]; + assign slv_reqs[i].aw_valid = slv_aw_valid[i]; + assign slv_reqs[i].w.data = slv_w_data[i]; + assign slv_reqs[i].w.strb = slv_w_strb[i]; + assign slv_reqs[i].w.last = slv_w_last[i]; + assign slv_reqs[i].w.user = slv_w_user[i]; + assign slv_reqs[i].w_valid = slv_w_valid[i]; + assign slv_reqs[i].b_ready = slv_b_ready[i]; + assign slv_reqs[i].ar.id = slv_ar_id[i]; + assign slv_reqs[i].ar.addr = slv_ar_addr[i]; + assign slv_reqs[i].ar.len = slv_ar_len[i]; + assign slv_reqs[i].ar.size = slv_ar_size[i]; + assign slv_reqs[i].ar.burst = slv_ar_burst[i]; + assign slv_reqs[i].ar.lock = slv_ar_lock[i]; + assign slv_reqs[i].ar.cache = slv_ar_cache[i]; + assign slv_reqs[i].ar.prot = slv_ar_prot[i]; + assign slv_reqs[i].ar.qos = slv_ar_qos[i]; + assign slv_reqs[i].ar.region = slv_ar_region[i]; + assign slv_reqs[i].ar.user = slv_ar_user[i]; + assign slv_reqs[i].ar_valid = slv_ar_valid[i]; + assign slv_reqs[i].r_ready = slv_r_ready[i]; + // Response + assign slv_aw_ready[i] = slv_resps[i].aw_ready; + assign slv_ar_ready[i] = slv_resps[i].ar_ready; + assign slv_w_ready[i] = slv_resps[i].w_ready; + assign slv_b_valid[i] = slv_resps[i].b_valid; + assign slv_b_id[i] = slv_resps[i].b.id; + assign slv_b_resp[i] = slv_resps[i].b.resp; + assign slv_b_user[i] = slv_resps[i].b.user; + assign slv_r_valid[i] = slv_resps[i].r_valid; + assign slv_r_id[i] = slv_resps[i].r.id; + assign slv_r_data[i] = slv_resps[i].r.data; + assign slv_r_resp[i] = slv_resps[i].r.resp; + assign slv_r_last[i] = slv_resps[i].r.last; + assign slv_r_user[i] = slv_resps[i].r.user; + end + + for (genvar i = 0; i < NoSlvMst; i++) begin : g_connect_mst_port + // Request + assign mst_aw_id[i] = mst_reqs[i].aw.id; + assign mst_aw_addr[i] = mst_reqs[i].aw.addr; + assign mst_aw_len[i] = mst_reqs[i].aw.len; + assign mst_aw_size[i] = mst_reqs[i].aw.size; + assign mst_aw_burst[i] = mst_reqs[i].aw.burst; + assign mst_aw_lock[i] = mst_reqs[i].aw.lock; + assign mst_aw_cache[i] = mst_reqs[i].aw.cache; + assign mst_aw_prot[i] = mst_reqs[i].aw.prot; + assign mst_aw_qos[i] = mst_reqs[i].aw.qos; + assign mst_aw_region[i] = mst_reqs[i].aw.region; + assign mst_aw_atop[i] = mst_reqs[i].aw.atop; + assign mst_aw_user[i] = mst_reqs[i].aw.user; + assign mst_aw_valid[i] = mst_reqs[i].aw_valid; + assign mst_w_data[i] = mst_reqs[i].w.data; + assign mst_w_strb[i] = mst_reqs[i].w.strb; + assign mst_w_last[i] = mst_reqs[i].w.last; + assign mst_w_user[i] = mst_reqs[i].w.user; + assign mst_w_valid[i] = mst_reqs[i].w_valid; + assign mst_b_ready[i] = mst_reqs[i].b_ready; + assign mst_ar_id[i] = mst_reqs[i].ar.id; + assign mst_ar_addr[i] = mst_reqs[i].ar.addr; + assign mst_ar_len[i] = mst_reqs[i].ar.len; + assign mst_ar_size[i] = mst_reqs[i].ar.size; + assign mst_ar_burst[i] = mst_reqs[i].ar.burst; + assign mst_ar_lock[i] = mst_reqs[i].ar.lock; + assign mst_ar_cache[i] = mst_reqs[i].ar.cache; + assign mst_ar_prot[i] = mst_reqs[i].ar.prot; + assign mst_ar_qos[i] = mst_reqs[i].ar.qos; + assign mst_ar_region[i] = mst_reqs[i].ar.region; + assign mst_ar_user[i] = mst_reqs[i].ar.user; + assign mst_ar_valid[i] = mst_reqs[i].ar_valid; + assign mst_r_ready[i] = mst_reqs[i].r_ready; + // Response + assign mst_resps[i].aw_ready = mst_aw_ready[i]; + assign mst_resps[i].ar_ready = mst_ar_ready[i]; + assign mst_resps[i].w_ready = mst_w_ready[i]; + assign mst_resps[i].b_valid = mst_b_valid[i]; + assign mst_resps[i].b.id = mst_b_id[i]; + assign mst_resps[i].b.resp = mst_b_resp[i]; + assign mst_resps[i].b.user = mst_b_user[i]; + assign mst_resps[i].r_valid = mst_r_valid[i]; + assign mst_resps[i].r.id = mst_r_id[i]; + assign mst_resps[i].r.data = mst_r_data[i]; + assign mst_resps[i].r.resp = mst_r_resp[i]; + assign mst_resps[i].r.last = mst_r_last[i]; + assign mst_resps[i].r.user = mst_r_user[i]; + end + endgenerate + + if (EnableMulticast) begin : g_multicast + axi_mcast_xbar #( + .Cfg (xbar_cfg), + .slv_aw_chan_t(slv_aw_chan_t), + .mst_aw_chan_t(mst_aw_chan_t), + .w_chan_t (w_chan_t), + .slv_b_chan_t (slv_b_chan_t), + .mst_b_chan_t (mst_b_chan_t), + .slv_ar_chan_t(slv_ar_chan_t), + .mst_ar_chan_t(mst_ar_chan_t), + .slv_r_chan_t (slv_r_chan_t), + .mst_r_chan_t (mst_r_chan_t), + .slv_req_t (slv_req_t), + .slv_resp_t (slv_resp_t), + .mst_req_t (mst_req_t), + .mst_resp_t (mst_resp_t), + .rule_t (rule_t) + ) i_xbar_dut ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_ports_req_i (slv_reqs), + .slv_ports_resp_o (slv_resps), + .mst_ports_req_o (mst_reqs), + .mst_ports_resp_i (mst_resps), + .addr_map_i (addr_map), + .en_default_mst_port_i('0), + .default_mst_port_i ('0) + ); + end else begin : g_no_multicast + axi_xbar #( + .Cfg (xbar_cfg), + .slv_aw_chan_t(slv_aw_chan_t), + .mst_aw_chan_t(mst_aw_chan_t), + .w_chan_t (w_chan_t), + .slv_b_chan_t (slv_b_chan_t), + .mst_b_chan_t (mst_b_chan_t), + .slv_ar_chan_t(slv_ar_chan_t), + .mst_ar_chan_t(mst_ar_chan_t), + .slv_r_chan_t (slv_r_chan_t), + .mst_r_chan_t (mst_r_chan_t), + .slv_req_t (slv_req_t), + .slv_resp_t (slv_resp_t), + .mst_req_t (mst_req_t), + .mst_resp_t (mst_resp_t), + .rule_t (rule_t) + ) i_xbar_dut ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_ports_req_i (slv_reqs), + .slv_ports_resp_o (slv_resps), + .mst_ports_req_o (mst_reqs), + .mst_ports_resp_i (mst_resps), + .addr_map_i (addr_map), + .en_default_mst_port_i('0), + .default_mst_port_i ('0) + ); + end + +endmodule + +module synth_axi_demux import axi_pkg::*; #( + parameter int unsigned NoMstPorts = 32'd8, + parameter bit UniqueIds = 0, + parameter xbar_latency_e LatencyMode = NO_LATENCY, + // axi configuration + parameter int unsigned AxiIdWidthMasters = 4, + parameter int unsigned AxiIdUsed = 3, // Has to be <= AxiIdWidthMasters + parameter int unsigned AxiAddrWidth = 32, // Axi Address Width + parameter int unsigned AxiDataWidth = 32, // Axi Data Width + parameter int unsigned AxiStrbWidth = AxiDataWidth / 8, + parameter int unsigned AxiUserWidth = 1, + // axi types + parameter type id_t = logic [AxiIdWidthMasters-1:0], + parameter type addr_t = logic [AxiAddrWidth-1:0], + parameter type data_t = logic [AxiDataWidth-1:0], + parameter type strb_t = logic [AxiStrbWidth-1:0], + parameter type user_t = logic [AxiUserWidth-1:0], + // select signal types + parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1, + parameter type select_t = logic [SelectWidth-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + // Select signals + input select_t slv_aw_select_i, + input select_t slv_ar_select_i, + + //////////////////////////////// + // Slave ports request inputs // + //////////////////////////////// + + // AW + input id_t slv_aw_id, + input addr_t slv_aw_addr, + input axi_pkg::len_t slv_aw_len, + input axi_pkg::size_t slv_aw_size, + input axi_pkg::burst_t slv_aw_burst, + input logic slv_aw_lock, + input axi_pkg::cache_t slv_aw_cache, + input axi_pkg::prot_t slv_aw_prot, + input axi_pkg::qos_t slv_aw_qos, + input axi_pkg::region_t slv_aw_region, + input axi_pkg::atop_t slv_aw_atop, + input user_t slv_aw_user, + input logic slv_aw_valid, + // W + input data_t slv_w_data, + input strb_t slv_w_strb, + input logic slv_w_last, + input user_t slv_w_user, + input logic slv_w_valid, + // B + input logic slv_b_ready, + // AR + input id_t slv_ar_id, + input addr_t slv_ar_addr, + input axi_pkg::len_t slv_ar_len, + input axi_pkg::size_t slv_ar_size, + input axi_pkg::burst_t slv_ar_burst, + input logic slv_ar_lock, + input axi_pkg::cache_t slv_ar_cache, + input axi_pkg::prot_t slv_ar_prot, + input axi_pkg::qos_t slv_ar_qos, + input axi_pkg::region_t slv_ar_region, + input user_t slv_ar_user, + input logic slv_ar_valid, + // R + input logic slv_r_ready, + + ////////////////////////////////// + // Slave ports response outputs // + ////////////////////////////////// + + // AW + output logic slv_aw_ready, + // AR + output logic slv_ar_ready, + // W + output logic slv_w_ready, + // B + output logic slv_b_valid, + output id_t slv_b_id, + output axi_pkg::resp_t slv_b_resp, + output user_t slv_b_user, + // R + output logic slv_r_valid, + output id_t slv_r_id, + output data_t slv_r_data, + output axi_pkg::resp_t slv_r_resp, + output logic slv_r_last, + output user_t slv_r_user, + + ////////////////////////////////// + // Master ports request outputs // + ////////////////////////////////// + + // AW + output id_t [NoMstPorts-1:0] mst_aw_id, + output addr_t [NoMstPorts-1:0] mst_aw_addr, + output axi_pkg::len_t [NoMstPorts-1:0] mst_aw_len, + output axi_pkg::size_t [NoMstPorts-1:0] mst_aw_size, + output axi_pkg::burst_t [NoMstPorts-1:0] mst_aw_burst, + output logic [NoMstPorts-1:0] mst_aw_lock, + output axi_pkg::cache_t [NoMstPorts-1:0] mst_aw_cache, + output axi_pkg::prot_t [NoMstPorts-1:0] mst_aw_prot, + output axi_pkg::qos_t [NoMstPorts-1:0] mst_aw_qos, + output axi_pkg::region_t [NoMstPorts-1:0] mst_aw_region, + output axi_pkg::atop_t [NoMstPorts-1:0] mst_aw_atop, + output user_t [NoMstPorts-1:0] mst_aw_user, + output logic [NoMstPorts-1:0] mst_aw_valid, + // W + output data_t [NoMstPorts-1:0] mst_w_data, + output strb_t [NoMstPorts-1:0] mst_w_strb, + output logic [NoMstPorts-1:0] mst_w_last, + output user_t [NoMstPorts-1:0] mst_w_user, + output logic [NoMstPorts-1:0] mst_w_valid, + // B + output logic [NoMstPorts-1:0] mst_b_ready, + // AR + output id_t [NoMstPorts-1:0] mst_ar_id, + output addr_t [NoMstPorts-1:0] mst_ar_addr, + output axi_pkg::len_t [NoMstPorts-1:0] mst_ar_len, + output axi_pkg::size_t [NoMstPorts-1:0] mst_ar_size, + output axi_pkg::burst_t [NoMstPorts-1:0] mst_ar_burst, + output logic [NoMstPorts-1:0] mst_ar_lock, + output axi_pkg::cache_t [NoMstPorts-1:0] mst_ar_cache, + output axi_pkg::prot_t [NoMstPorts-1:0] mst_ar_prot, + output axi_pkg::qos_t [NoMstPorts-1:0] mst_ar_qos, + output axi_pkg::region_t [NoMstPorts-1:0] mst_ar_region, + output user_t [NoMstPorts-1:0] mst_ar_user, + output logic [NoMstPorts-1:0] mst_ar_valid, + // R + output logic [NoMstPorts-1:0] mst_r_ready, + + ////////////////////////////////// + // Master ports response inputs // + ////////////////////////////////// + + // AW + input logic [NoMstPorts-1:0] mst_aw_ready, + // AR + input logic [NoMstPorts-1:0] mst_ar_ready, + // W + input logic [NoMstPorts-1:0] mst_w_ready, + // B + input logic [NoMstPorts-1:0] mst_b_valid, + input id_t [NoMstPorts-1:0] mst_b_id, + input axi_pkg::resp_t [NoMstPorts-1:0] mst_b_resp, + input user_t [NoMstPorts-1:0] mst_b_user, + // R + input logic [NoMstPorts-1:0] mst_r_valid, + input id_t [NoMstPorts-1:0] mst_r_id, + input data_t [NoMstPorts-1:0] mst_r_data, + input axi_pkg::resp_t [NoMstPorts-1:0] mst_r_resp, + input logic [NoMstPorts-1:0] mst_r_last, + input user_t [NoMstPorts-1:0] mst_r_user + +); + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req; + req_t [NoMstPorts-1:0] mst_reqs; + resp_t slv_resp; + resp_t [NoMstPorts-1:0] mst_resps; + + // Connect XBAR interfaces + assign slv_req.aw.id = slv_aw_id; + assign slv_req.aw.addr = slv_aw_addr; + assign slv_req.aw.len = slv_aw_len; + assign slv_req.aw.size = slv_aw_size; + assign slv_req.aw.burst = slv_aw_burst; + assign slv_req.aw.lock = slv_aw_lock; + assign slv_req.aw.cache = slv_aw_cache; + assign slv_req.aw.prot = slv_aw_prot; + assign slv_req.aw.qos = slv_aw_qos; + assign slv_req.aw.region = slv_aw_region; + assign slv_req.aw.atop = slv_aw_atop; + assign slv_req.aw.user = slv_aw_user; + assign slv_req.aw_valid = slv_aw_valid; + assign slv_req.w.data = slv_w_data; + assign slv_req.w.strb = slv_w_strb; + assign slv_req.w.last = slv_w_last; + assign slv_req.w.user = slv_w_user; + assign slv_req.w_valid = slv_w_valid; + assign slv_req.b_ready = slv_b_ready; + assign slv_req.ar.id = slv_ar_id; + assign slv_req.ar.addr = slv_ar_addr; + assign slv_req.ar.len = slv_ar_len; + assign slv_req.ar.size = slv_ar_size; + assign slv_req.ar.burst = slv_ar_burst; + assign slv_req.ar.lock = slv_ar_lock; + assign slv_req.ar.cache = slv_ar_cache; + assign slv_req.ar.prot = slv_ar_prot; + assign slv_req.ar.qos = slv_ar_qos; + assign slv_req.ar.region = slv_ar_region; + assign slv_req.ar.user = slv_ar_user; + assign slv_req.ar_valid = slv_ar_valid; + assign slv_req.r_ready = slv_r_ready; + // Response + assign slv_aw_ready = slv_resp.aw_ready; + assign slv_ar_ready = slv_resp.ar_ready; + assign slv_w_ready = slv_resp.w_ready; + assign slv_b_valid = slv_resp.b_valid; + assign slv_b_id = slv_resp.b.id; + assign slv_b_resp = slv_resp.b.resp; + assign slv_b_user = slv_resp.b.user; + assign slv_r_valid = slv_resp.r_valid; + assign slv_r_id = slv_resp.r.id; + assign slv_r_data = slv_resp.r.data; + assign slv_r_resp = slv_resp.r.resp; + assign slv_r_last = slv_resp.r.last; + assign slv_r_user = slv_resp.r.user; + + generate + for (genvar i = 0; i < NoMstPorts; i++) begin : g_connect_mst_port + // Request + assign mst_aw_id[i] = mst_reqs[i].aw.id; + assign mst_aw_addr[i] = mst_reqs[i].aw.addr; + assign mst_aw_len[i] = mst_reqs[i].aw.len; + assign mst_aw_size[i] = mst_reqs[i].aw.size; + assign mst_aw_burst[i] = mst_reqs[i].aw.burst; + assign mst_aw_lock[i] = mst_reqs[i].aw.lock; + assign mst_aw_cache[i] = mst_reqs[i].aw.cache; + assign mst_aw_prot[i] = mst_reqs[i].aw.prot; + assign mst_aw_qos[i] = mst_reqs[i].aw.qos; + assign mst_aw_region[i] = mst_reqs[i].aw.region; + assign mst_aw_atop[i] = mst_reqs[i].aw.atop; + assign mst_aw_user[i] = mst_reqs[i].aw.user; + assign mst_aw_valid[i] = mst_reqs[i].aw_valid; + assign mst_w_data[i] = mst_reqs[i].w.data; + assign mst_w_strb[i] = mst_reqs[i].w.strb; + assign mst_w_last[i] = mst_reqs[i].w.last; + assign mst_w_user[i] = mst_reqs[i].w.user; + assign mst_w_valid[i] = mst_reqs[i].w_valid; + assign mst_b_ready[i] = mst_reqs[i].b_ready; + assign mst_ar_id[i] = mst_reqs[i].ar.id; + assign mst_ar_addr[i] = mst_reqs[i].ar.addr; + assign mst_ar_len[i] = mst_reqs[i].ar.len; + assign mst_ar_size[i] = mst_reqs[i].ar.size; + assign mst_ar_burst[i] = mst_reqs[i].ar.burst; + assign mst_ar_lock[i] = mst_reqs[i].ar.lock; + assign mst_ar_cache[i] = mst_reqs[i].ar.cache; + assign mst_ar_prot[i] = mst_reqs[i].ar.prot; + assign mst_ar_qos[i] = mst_reqs[i].ar.qos; + assign mst_ar_region[i] = mst_reqs[i].ar.region; + assign mst_ar_user[i] = mst_reqs[i].ar.user; + assign mst_ar_valid[i] = mst_reqs[i].ar_valid; + assign mst_r_ready[i] = mst_reqs[i].r_ready; + // Response + assign mst_resps[i].aw_ready = mst_aw_ready[i]; + assign mst_resps[i].ar_ready = mst_ar_ready[i]; + assign mst_resps[i].w_ready = mst_w_ready[i]; + assign mst_resps[i].b_valid = mst_b_valid[i]; + assign mst_resps[i].b.id = mst_b_id[i]; + assign mst_resps[i].b.resp = mst_b_resp[i]; + assign mst_resps[i].b.user = mst_b_user[i]; + assign mst_resps[i].r_valid = mst_r_valid[i]; + assign mst_resps[i].r.id = mst_r_id[i]; + assign mst_resps[i].r.data = mst_r_data[i]; + assign mst_resps[i].r.resp = mst_r_resp[i]; + assign mst_resps[i].r.last = mst_r_last[i]; + assign mst_resps[i].r.user = mst_r_user[i]; + end + endgenerate + + axi_demux #( + .AxiIdWidth (AxiIdWidthMasters), + .AtopSupport(1'b0), + .aw_chan_t (aw_chan_t), + .w_chan_t (w_chan_t), + .b_chan_t (b_chan_t), + .ar_chan_t (ar_chan_t), + .r_chan_t (r_chan_t), + .axi_req_t (req_t), + .axi_resp_t (resp_t), + .NoMstPorts (NoMstPorts), + .MaxTrans (10), + .AxiLookBits(AxiIdUsed), + .UniqueIds (UniqueIds), + .SpillAw (LatencyMode[9]), + .SpillW (LatencyMode[8]), + .SpillB (LatencyMode[7]), + .SpillAr (LatencyMode[6]), + .SpillR (LatencyMode[5]) + ) i_axi_demux ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_req_i (slv_req), + .slv_aw_select_i(slv_aw_select_i), + .slv_ar_select_i(slv_ar_select_i), + .slv_resp_o (slv_resp), + .mst_reqs_o (mst_reqs), + .mst_resps_i (mst_resps) + ); +endmodule + +module synth_axi_mcast_demux import axi_pkg::*; #( + parameter int unsigned NoMstPorts = 32'd8, + parameter bit UniqueIds = 0, + parameter xbar_latency_e LatencyMode = NO_LATENCY, + // axi configuration + parameter int unsigned AxiIdWidthMasters = 4, + parameter int unsigned AxiIdUsed = 3, // Has to be <= AxiIdWidthMasters + parameter int unsigned AxiAddrWidth = 32, // Axi Address Width + parameter int unsigned AxiDataWidth = 32, // Axi Data Width + parameter int unsigned AxiStrbWidth = AxiDataWidth / 8, + parameter int unsigned AxiUserWidth = 32, + // axi types + parameter type id_t = logic [AxiIdWidthMasters-1:0], + parameter type addr_t = logic [AxiAddrWidth-1:0], + parameter type data_t = logic [AxiDataWidth-1:0], + parameter type strb_t = logic [AxiStrbWidth-1:0], + parameter type user_t = logic [AxiUserWidth-1:0], + // select signal types + parameter int unsigned IdxSelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1, + parameter type idx_select_t = logic [IdxSelectWidth-1:0], + parameter type mask_select_t = logic [NoMstPorts-1:0], + parameter type multi_addr_t = struct packed { + addr_t aw_addr; + addr_t aw_mask; + } +) ( + input logic clk_i, + input logic rst_ni, + + // Address decoder signals + input mask_select_t slv_aw_select_i, + input idx_select_t slv_ar_select_i, + input multi_addr_t [NoMstPorts-1:0] slv_aw_mcast_i, + + //////////////////////////////// + // Slave ports request inputs // + //////////////////////////////// + + // AW + input id_t slv_aw_id, + input addr_t slv_aw_addr, + input axi_pkg::len_t slv_aw_len, + input axi_pkg::size_t slv_aw_size, + input axi_pkg::burst_t slv_aw_burst, + input logic slv_aw_lock, + input axi_pkg::cache_t slv_aw_cache, + input axi_pkg::prot_t slv_aw_prot, + input axi_pkg::qos_t slv_aw_qos, + input axi_pkg::region_t slv_aw_region, + input axi_pkg::atop_t slv_aw_atop, + input user_t slv_aw_user, + input logic slv_aw_valid, + // W + input data_t slv_w_data, + input strb_t slv_w_strb, + input logic slv_w_last, + input user_t slv_w_user, + input logic slv_w_valid, + // B + input logic slv_b_ready, + // AR + input id_t slv_ar_id, + input addr_t slv_ar_addr, + input axi_pkg::len_t slv_ar_len, + input axi_pkg::size_t slv_ar_size, + input axi_pkg::burst_t slv_ar_burst, + input logic slv_ar_lock, + input axi_pkg::cache_t slv_ar_cache, + input axi_pkg::prot_t slv_ar_prot, + input axi_pkg::qos_t slv_ar_qos, + input axi_pkg::region_t slv_ar_region, + input user_t slv_ar_user, + input logic slv_ar_valid, + // R + input logic slv_r_ready, + + ////////////////////////////////// + // Slave ports response outputs // + ////////////////////////////////// + + // AW + output logic slv_aw_ready, + // AR + output logic slv_ar_ready, + // W + output logic slv_w_ready, + // B + output logic slv_b_valid, + output id_t slv_b_id, + output axi_pkg::resp_t slv_b_resp, + output user_t slv_b_user, + // R + output logic slv_r_valid, + output id_t slv_r_id, + output data_t slv_r_data, + output axi_pkg::resp_t slv_r_resp, + output logic slv_r_last, + output user_t slv_r_user, + + ////////////////////////////////// + // Master ports request outputs // + ////////////////////////////////// + + // AW + output id_t [NoMstPorts-1:0] mst_aw_id, + output addr_t [NoMstPorts-1:0] mst_aw_addr, + output axi_pkg::len_t [NoMstPorts-1:0] mst_aw_len, + output axi_pkg::size_t [NoMstPorts-1:0] mst_aw_size, + output axi_pkg::burst_t [NoMstPorts-1:0] mst_aw_burst, + output logic [NoMstPorts-1:0] mst_aw_lock, + output axi_pkg::cache_t [NoMstPorts-1:0] mst_aw_cache, + output axi_pkg::prot_t [NoMstPorts-1:0] mst_aw_prot, + output axi_pkg::qos_t [NoMstPorts-1:0] mst_aw_qos, + output axi_pkg::region_t [NoMstPorts-1:0] mst_aw_region, + output axi_pkg::atop_t [NoMstPorts-1:0] mst_aw_atop, + output user_t [NoMstPorts-1:0] mst_aw_user, + output logic [NoMstPorts-1:0] mst_aw_valid, + // W + output data_t [NoMstPorts-1:0] mst_w_data, + output strb_t [NoMstPorts-1:0] mst_w_strb, + output logic [NoMstPorts-1:0] mst_w_last, + output user_t [NoMstPorts-1:0] mst_w_user, + output logic [NoMstPorts-1:0] mst_w_valid, + // B + output logic [NoMstPorts-1:0] mst_b_ready, + // AR + output id_t [NoMstPorts-1:0] mst_ar_id, + output addr_t [NoMstPorts-1:0] mst_ar_addr, + output axi_pkg::len_t [NoMstPorts-1:0] mst_ar_len, + output axi_pkg::size_t [NoMstPorts-1:0] mst_ar_size, + output axi_pkg::burst_t [NoMstPorts-1:0] mst_ar_burst, + output logic [NoMstPorts-1:0] mst_ar_lock, + output axi_pkg::cache_t [NoMstPorts-1:0] mst_ar_cache, + output axi_pkg::prot_t [NoMstPorts-1:0] mst_ar_prot, + output axi_pkg::qos_t [NoMstPorts-1:0] mst_ar_qos, + output axi_pkg::region_t [NoMstPorts-1:0] mst_ar_region, + output user_t [NoMstPorts-1:0] mst_ar_user, + output logic [NoMstPorts-1:0] mst_ar_valid, + // R + output logic [NoMstPorts-1:0] mst_r_ready, + + ////////////////////////////////// + // Master ports response inputs // + ////////////////////////////////// + + // AW + input logic [NoMstPorts-1:0] mst_aw_ready, + // AR + input logic [NoMstPorts-1:0] mst_ar_ready, + // W + input logic [NoMstPorts-1:0] mst_w_ready, + // B + input logic [NoMstPorts-1:0] mst_b_valid, + input id_t [NoMstPorts-1:0] mst_b_id, + input axi_pkg::resp_t [NoMstPorts-1:0] mst_b_resp, + input user_t [NoMstPorts-1:0] mst_b_user, + // R + input logic [NoMstPorts-1:0] mst_r_valid, + input id_t [NoMstPorts-1:0] mst_r_id, + input data_t [NoMstPorts-1:0] mst_r_data, + input axi_pkg::resp_t [NoMstPorts-1:0] mst_r_resp, + input logic [NoMstPorts-1:0] mst_r_last, + input user_t [NoMstPorts-1:0] mst_r_user + +); + + typedef struct packed { + logic [AxiUserWidth-1:0] mcast; + } aw_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_t, user_t) + + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + slv_req_t slv_req; + mst_req_t [NoMstPorts-1:0] mst_reqs; + slv_resp_t slv_resp; + mst_resp_t [NoMstPorts-1:0] mst_resps; + + // Connect XBAR interfaces + assign slv_req.aw.id = slv_aw_id; + assign slv_req.aw.addr = slv_aw_addr; + assign slv_req.aw.len = slv_aw_len; + assign slv_req.aw.size = slv_aw_size; + assign slv_req.aw.burst = slv_aw_burst; + assign slv_req.aw.lock = slv_aw_lock; + assign slv_req.aw.cache = slv_aw_cache; + assign slv_req.aw.prot = slv_aw_prot; + assign slv_req.aw.qos = slv_aw_qos; + assign slv_req.aw.region = slv_aw_region; + assign slv_req.aw.atop = slv_aw_atop; + assign slv_req.aw.user = slv_aw_user; + assign slv_req.aw_valid = slv_aw_valid; + assign slv_req.w.data = slv_w_data; + assign slv_req.w.strb = slv_w_strb; + assign slv_req.w.last = slv_w_last; + assign slv_req.w.user = slv_w_user; + assign slv_req.w_valid = slv_w_valid; + assign slv_req.b_ready = slv_b_ready; + assign slv_req.ar.id = slv_ar_id; + assign slv_req.ar.addr = slv_ar_addr; + assign slv_req.ar.len = slv_ar_len; + assign slv_req.ar.size = slv_ar_size; + assign slv_req.ar.burst = slv_ar_burst; + assign slv_req.ar.lock = slv_ar_lock; + assign slv_req.ar.cache = slv_ar_cache; + assign slv_req.ar.prot = slv_ar_prot; + assign slv_req.ar.qos = slv_ar_qos; + assign slv_req.ar.region = slv_ar_region; + assign slv_req.ar.user = slv_ar_user; + assign slv_req.ar_valid = slv_ar_valid; + assign slv_req.r_ready = slv_r_ready; + // Response + assign slv_aw_ready = slv_resp.aw_ready; + assign slv_ar_ready = slv_resp.ar_ready; + assign slv_w_ready = slv_resp.w_ready; + assign slv_b_valid = slv_resp.b_valid; + assign slv_b_id = slv_resp.b.id; + assign slv_b_resp = slv_resp.b.resp; + assign slv_b_user = slv_resp.b.user; + assign slv_r_valid = slv_resp.r_valid; + assign slv_r_id = slv_resp.r.id; + assign slv_r_data = slv_resp.r.data; + assign slv_r_resp = slv_resp.r.resp; + assign slv_r_last = slv_resp.r.last; + assign slv_r_user = slv_resp.r.user; + + generate + for (genvar i = 0; i < NoMstPorts; i++) begin : g_connect_mst_port + // Request + assign mst_aw_id[i] = mst_reqs[i].aw.id; + assign mst_aw_addr[i] = mst_reqs[i].aw.addr; + assign mst_aw_len[i] = mst_reqs[i].aw.len; + assign mst_aw_size[i] = mst_reqs[i].aw.size; + assign mst_aw_burst[i] = mst_reqs[i].aw.burst; + assign mst_aw_lock[i] = mst_reqs[i].aw.lock; + assign mst_aw_cache[i] = mst_reqs[i].aw.cache; + assign mst_aw_prot[i] = mst_reqs[i].aw.prot; + assign mst_aw_qos[i] = mst_reqs[i].aw.qos; + assign mst_aw_region[i] = mst_reqs[i].aw.region; + assign mst_aw_atop[i] = mst_reqs[i].aw.atop; + assign mst_aw_user[i] = mst_reqs[i].aw.user; + assign mst_aw_valid[i] = mst_reqs[i].aw_valid; + assign mst_w_data[i] = mst_reqs[i].w.data; + assign mst_w_strb[i] = mst_reqs[i].w.strb; + assign mst_w_last[i] = mst_reqs[i].w.last; + assign mst_w_user[i] = mst_reqs[i].w.user; + assign mst_w_valid[i] = mst_reqs[i].w_valid; + assign mst_b_ready[i] = mst_reqs[i].b_ready; + assign mst_ar_id[i] = mst_reqs[i].ar.id; + assign mst_ar_addr[i] = mst_reqs[i].ar.addr; + assign mst_ar_len[i] = mst_reqs[i].ar.len; + assign mst_ar_size[i] = mst_reqs[i].ar.size; + assign mst_ar_burst[i] = mst_reqs[i].ar.burst; + assign mst_ar_lock[i] = mst_reqs[i].ar.lock; + assign mst_ar_cache[i] = mst_reqs[i].ar.cache; + assign mst_ar_prot[i] = mst_reqs[i].ar.prot; + assign mst_ar_qos[i] = mst_reqs[i].ar.qos; + assign mst_ar_region[i] = mst_reqs[i].ar.region; + assign mst_ar_user[i] = mst_reqs[i].ar.user; + assign mst_ar_valid[i] = mst_reqs[i].ar_valid; + assign mst_r_ready[i] = mst_reqs[i].r_ready; + // Response + assign mst_resps[i].aw_ready = mst_aw_ready[i]; + assign mst_resps[i].ar_ready = mst_ar_ready[i]; + assign mst_resps[i].w_ready = mst_w_ready[i]; + assign mst_resps[i].b_valid = mst_b_valid[i]; + assign mst_resps[i].b.id = mst_b_id[i]; + assign mst_resps[i].b.resp = mst_b_resp[i]; + assign mst_resps[i].b.user = mst_b_user[i]; + assign mst_resps[i].r_valid = mst_r_valid[i]; + assign mst_resps[i].r.id = mst_r_id[i]; + assign mst_resps[i].r.data = mst_r_data[i]; + assign mst_resps[i].r.resp = mst_r_resp[i]; + assign mst_resps[i].r.last = mst_r_last[i]; + assign mst_resps[i].r.user = mst_r_user[i]; + end + endgenerate + + axi_mcast_demux #( + .AxiIdWidth (AxiIdWidthMasters), + .AtopSupport(1'b0), + .aw_addr_t (addr_t), + .aw_chan_t (slv_aw_chan_t), + .w_chan_t (w_chan_t), + .b_chan_t (slv_b_chan_t), + .ar_chan_t (slv_ar_chan_t), + .r_chan_t (slv_r_chan_t), + .axi_req_t (slv_req_t), + .axi_resp_t (slv_resp_t), + .NoMstPorts (NoMstPorts), + .MaxTrans (10), + .AxiLookBits(AxiIdUsed), + .UniqueIds (UniqueIds), + .SpillAw (LatencyMode[9]), + .SpillW (LatencyMode[8]), + .SpillB (LatencyMode[7]), + .SpillAr (LatencyMode[6]), + .SpillR (LatencyMode[5]) + ) i_axi_mcast_demux ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_req_i (slv_req), + .slv_aw_select_i(slv_aw_select_i), + .slv_ar_select_i(slv_ar_select_i), + .slv_aw_mcast_i (slv_aw_mcast_i), + .slv_resp_o (slv_resp), + .mst_reqs_o (mst_reqs), + .mst_resps_i (mst_resps) + ); + +endmodule diff --git a/test/tb_axi_bus_compare.sv b/test/tb_axi_bus_compare.sv index c8cd1c91c..9283ae408 100644 --- a/test/tb_axi_bus_compare.sv +++ b/test/tb_axi_bus_compare.sv @@ -79,27 +79,30 @@ module tb_axi_bus_compare #( logic w_ready; logic ar_ready; - stream_fork #(.N_OUP(32'd2)) i_stream_fork_aw ( + cc_stream_fork #(.NumOup(32'd2)) i_stream_fork_aw ( .clk_i ( clk ), .rst_ni ( rst_n ), + .clr_i ( 1'b0 ), .valid_i ( axi_req.aw_valid ), .ready_o ( aw_ready ), .valid_o ( { aw_valid_a, aw_valid_b } ), .ready_i ( { aw_ready_a, aw_ready_b } ) ); - stream_fork #(.N_OUP(32'd2)) i_stream_fork_ar ( + cc_stream_fork #(.NumOup(32'd2)) i_stream_fork_ar ( .clk_i ( clk ), .rst_ni ( rst_n ), + .clr_i ( 1'b0 ), .valid_i ( axi_req.ar_valid ), .ready_o ( ar_ready ), .valid_o ( { ar_valid_a, ar_valid_b } ), .ready_i ( { ar_ready_a, ar_ready_b } ) ); - stream_fork #(.N_OUP(32'd2)) i_stream_fork_w ( + cc_stream_fork #(.NumOup(32'd2)) i_stream_fork_w ( .clk_i ( clk ), .rst_ni ( rst_n ), + .clr_i ( 1'b0 ), .valid_i ( axi_req.w_valid ), .ready_o ( w_ready ), .valid_o ( { w_valid_a, w_valid_b } ), @@ -149,7 +152,6 @@ module tb_axi_bus_compare #( ) i_axi_bus_compare ( .clk_i ( clk ), .rst_ni ( rst_n ), - .testmode_i ( 1'b0 ), .axi_a_req_i ( axi_req_a_in ), .axi_a_rsp_o ( axi_rsp_a_in ), .axi_a_req_o ( axi_req_a_out ), @@ -257,7 +259,7 @@ module tb_axi_bus_compare #( drv.reset_master(); wait (rst_n); // AW -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(aw_beat); assert (rand_success); @@ -272,7 +274,7 @@ module tb_axi_bus_compare #( drv.send_aw(aw_beat); // W beats for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); diff --git a/test/tb_axi_delayer.sv b/test/tb_axi_delayer.sv index 5b9c15dc4..186a10334 100644 --- a/test/tb_axi_delayer.sv +++ b/test/tb_axi_delayer.sv @@ -83,7 +83,7 @@ module tb_axi_delayer; @(posedge clk); repeat (200) begin @(posedge clk); -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(ax_beat) may behave differently to ax_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(ax_beat); assert(rand_success); diff --git a/test/tb_axi_fifo.sv b/test/tb_axi_fifo.sv index 2e79044e0..b962fa952 100644 --- a/test/tb_axi_fifo.sv +++ b/test/tb_axi_fifo.sv @@ -111,7 +111,6 @@ module tb_axi_fifo #( ) i_dut ( .clk_i (clk), // clock .rst_ni(rst_n), // asynchronous reset active low - .test_i(1'b0), .slv (master), // slave port .mst (slave) // master port ); diff --git a/test/tb_axi_fifo.wave.do b/test/tb_axi_fifo.wave.do index bdf1d9e20..5e0fdf5a6 100644 --- a/test/tb_axi_fifo.wave.do +++ b/test/tb_axi_fifo.wave.do @@ -98,7 +98,6 @@ add wave -noupdate -divider Custom add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/clk_i add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/rst_ni add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/flush_i -add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/testmode_i add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/full_o add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/empty_o add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_aw_fifo/usage_o @@ -109,7 +108,6 @@ add wave -noupdate -expand -group {AW FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_ax add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/clk_i add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/rst_ni add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/flush_i -add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/testmode_i add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/full_o add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/empty_o add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_w_fifo/usage_o @@ -120,7 +118,6 @@ add wave -noupdate -expand -group {W FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/clk_i add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/rst_ni add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/flush_i -add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/testmode_i add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/full_o add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/empty_o add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_b_fifo/usage_o @@ -131,7 +128,6 @@ add wave -noupdate -expand -group {B FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/clk_i add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/rst_ni add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/flush_i -add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/testmode_i add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/full_o add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/empty_o add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_ar_fifo/usage_o @@ -142,7 +138,6 @@ add wave -noupdate -expand -group {Ar FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_ax add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/clk_i add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/rst_ni add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/flush_i -add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/testmode_i add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/full_o add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/empty_o add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/usage_o diff --git a/test/tb_axi_lite_mailbox.sv b/test/tb_axi_lite_mailbox.sv index 255702922..14fab56fe 100644 --- a/test/tb_axi_lite_mailbox.sv +++ b/test/tb_axi_lite_mailbox.sv @@ -456,7 +456,6 @@ module tb_axi_lite_mailbox; ) i_mailbox_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .slv ( master ), .irq_o ( irq ), .base_addr_i ( '0 ) // set base address to '0 diff --git a/test/tb_axi_lite_mailbox.wave.do b/test/tb_axi_lite_mailbox.wave.do index c272b4fa2..3e1572ba3 100644 --- a/test/tb_axi_lite_mailbox.wave.do +++ b/test/tb_axi_lite_mailbox.wave.do @@ -3,7 +3,6 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/clk_i add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/rst_ni -add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/test_i add wave -noupdate -divider Ports add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/slv_reqs_i add wave -noupdate /tb_axi_lite_mailbox/i_mailbox_dut/i_axi_lite_mailbox/slv_resps_o diff --git a/test/tb_axi_lite_xbar.sv b/test/tb_axi_lite_xbar.sv index 54697344a..d4d460af1 100644 --- a/test/tb_axi_lite_xbar.sv +++ b/test/tb_axi_lite_xbar.sv @@ -175,7 +175,6 @@ module tb_axi_lite_xbar; ) i_xbar_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .slv_ports ( master ), .mst_ports ( slave ), .addr_map_i ( AddrMap ), diff --git a/test/tb_axi_lite_xbar.wave.do b/test/tb_axi_lite_xbar.wave.do index 604e70c80..1eb256870 100644 --- a/test/tb_axi_lite_xbar.wave.do +++ b/test/tb_axi_lite_xbar.wave.do @@ -3,7 +3,6 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_lite_xbar/i_xbar_dut/clk_i add wave -noupdate -label Reset /tb_axi_lite_xbar/i_xbar_dut/rst_ni -add wave -noupdate -label {Test Mode} /tb_axi_lite_xbar/i_xbar_dut/test_i add wave -noupdate -divider {Slave Ports} add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/slv_ports_req_i add wave -noupdate /tb_axi_lite_xbar/i_xbar_dut/slv_ports_resp_o diff --git a/test/tb_axi_mcast_xbar.sv b/test/tb_axi_mcast_xbar.sv new file mode 100644 index 000000000..e76445963 --- /dev/null +++ b/test/tb_axi_mcast_xbar.sv @@ -0,0 +1,496 @@ +// Copyright (c) 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Florian Zaruba +// - Andreas Kurth +// - Luca Colagrande + +// Directed Random Verification Testbench for `axi_xbar`: The crossbar is instantiated with +// a number of random axi master and slave modules. Each random master executes a fixed number of +// writes and reads over the whole addess map. All masters simultaneously issue transactions +// through the crossbar, thereby saturating it. A monitor, which snoops the transactions of each +// master and slave port and models the crossbar with a network of FIFOs, checks whether each +// transaction follows the expected route. + +`include "axi/typedef.svh" +`include "axi/assign.svh" + +/// Testbench for the module `axi_mcast_xbar`. +module tb_axi_mcast_xbar #( + /// Number of AXI masters connected to the xbar. (Number of slave ports) + parameter int unsigned TbNumMasters = 32'd6, + /// Number of AXI slaves connected to the xbar which can be targeted by multicast + /// transactions. (Number of multicast-enabled master ports) + parameter int unsigned TbNumMcastSlaves = 32'd8, + /// Number of write transactions per master. + parameter int unsigned TbNumWrites = 32'd200, + /// Number of read transactions per master. + parameter int unsigned TbNumReads = 32'd200, + /// AXI4+ATOP ID width of the masters connected to the slave ports of the DUT. + /// The ID width of the slaves is calculated depending on the xbar configuration. + parameter int unsigned TbAxiIdWidthMasters = 32'd5, + /// The used ID width of the DUT. + /// Has to be `TbAxiIdWidthMasters >= TbAxiIdUsed`. + parameter int unsigned TbAxiIdUsed = 32'd3, + /// Data width of the AXI channels. + parameter int unsigned TbAxiDataWidth = 32'd64, + /// Pipeline stages in the xbar itself (between demux and mux). + parameter int unsigned TbPipeline = 32'd1, + /// Enable ATOP generation + parameter bit TbEnAtop = 1'b1, + /// Enable exclusive accesses + parameter bit TbEnExcl = 1'b0, + /// Restrict to only unique IDs + parameter bit TbUniqueIds = 1'b0 +); + + // TB timing parameters + localparam time CyclTime = 10ns; + localparam time ApplTime = 2ns; + localparam time TestTime = 8ns; + + // AXI configuration which is automatically derived. + localparam int unsigned TbAxiIdWidthSlaves = TbAxiIdWidthMasters + $clog2(TbNumMasters); + localparam int unsigned TbAxiAddrWidth = 32'd32; + localparam int unsigned TbAxiStrbWidth = TbAxiDataWidth / 8; + localparam int unsigned TbAxiUserWidth = TbAxiAddrWidth; + // In the bench can change this variables which are set here freely, + localparam TbNumSlaves = TbNumMcastSlaves + 1; + localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ + NoSlvPorts: TbNumMasters, + NoMstPorts: TbNumSlaves, + MaxMstTrans: 10, + MaxSlvTrans: 6, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + PipelineStages: TbPipeline, + AxiIdWidthSlvPorts: TbAxiIdWidthMasters, + AxiIdUsedSlvPorts: TbAxiIdUsed, + UniqueIds: TbUniqueIds, + AxiAddrWidth: TbAxiAddrWidth, + AxiDataWidth: TbAxiDataWidth, + NoAddrRules: TbNumMcastSlaves * 2 + 1, + NoMulticastRules: TbNumMcastSlaves * 2, + NoMulticastPorts: TbNumMcastSlaves + }; + typedef logic [TbAxiIdWidthMasters-1:0] id_mst_t; + typedef logic [TbAxiIdWidthSlaves-1:0] id_slv_t; + typedef logic [TbAxiAddrWidth-1:0] addr_t; + typedef struct packed { + int unsigned idx; + addr_t start_addr; + addr_t end_addr; + } rule_t; + typedef logic [TbAxiDataWidth-1:0] data_t; + typedef logic [TbAxiStrbWidth-1:0] strb_t; + typedef logic [TbAxiUserWidth-1:0] user_t; + // For collectives, AW channel should contain collective mask in USER field + typedef struct packed { + addr_t collective_mask; + } aw_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, aw_user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, aw_user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mst_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_slv_t, id_slv_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mst_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t) + + `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_mst_t, r_chan_mst_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_slv_t, r_chan_slv_t) + + // Each slave has its own address range: + localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = { + rule_t'{ + idx: TbNumMcastSlaves, + start_addr: 32'h7000_0000, + end_addr: 32'h7008_0000 + }, + addr_map_gen(32'h1000_0000, 32'h10_0000), + addr_map_gen(32'h0b00_0000, 32'h1_0000) + }; + + function rule_t [xbar_cfg.NoMulticastPorts-1:0] addr_map_gen (addr_t base, addr_t offset); + for (int unsigned i = 0; i < xbar_cfg.NoMulticastPorts; i++) begin + addr_map_gen[i] = rule_t'{ + idx: unsigned'(i), + start_addr: base + offset * i, + end_addr: base + offset * (i + 1), + default: '0 + }; + end + endfunction + + typedef axi_test::axi_rand_master #( + // AXI interface parameters + .AW ( TbAxiAddrWidth ), + .DW ( TbAxiDataWidth ), + .IW ( TbAxiIdWidthMasters ), + .UW ( TbAxiUserWidth ), + // Stimuli application and test time + .TA ( ApplTime ), + .TT ( TestTime ), + // Maximum number of read and write transactions in flight + .MAX_READ_TXNS ( 20 ), + .MAX_WRITE_TXNS ( 20 ), + .AXI_EXCLS ( TbEnExcl ), + .AXI_ATOPS ( TbEnAtop ), + .UNIQUE_IDS ( TbUniqueIds ), + .ENABLE_MULTICAST ( 1 ) + ) axi_rand_master_t; + typedef axi_test::axi_rand_slave #( + // AXI interface parameters + .AW ( TbAxiAddrWidth ), + .DW ( TbAxiDataWidth ), + .IW ( TbAxiIdWidthSlaves ), + .UW ( TbAxiUserWidth ), + // Stimuli application and test time + .TA ( ApplTime ), + .TT ( TestTime ) + ) axi_rand_slave_t; + + // ------------- + // DUT signals + // ------------- + logic clk; + // DUT signals + logic rst_n; + logic [TbNumMasters-1:0] end_of_sim; + + // master structs + mst_req_t [TbNumMasters-1:0] masters_req; + mst_resp_t [TbNumMasters-1:0] masters_resp; + + // slave structs + slv_req_t [TbNumSlaves-1:0] slaves_req; + slv_resp_t [TbNumSlaves-1:0] slaves_resp; + + // ------------------------------- + // AXI Interfaces + // ------------------------------- + AXI_BUS #( + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) master [TbNumMasters-1:0] (); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) master_dv [TbNumMasters-1:0] (clk); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) master_monitor_dv [TbNumMasters-1:0] (clk); + for (genvar i = 0; i < TbNumMasters; i++) begin : gen_conn_dv_masters + `AXI_ASSIGN (master[i], master_dv[i]) + `AXI_ASSIGN_TO_REQ(masters_req[i], master[i]) + `AXI_ASSIGN_TO_RESP(masters_resp[i], master[i]) + end + + AXI_BUS #( + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) slave [TbNumSlaves-1:0] (); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) slave_dv [TbNumSlaves-1:0](clk); + AXI_BUS_DV #( + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) slave_monitor_dv [TbNumSlaves-1:0](clk); + for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_conn_dv_slaves + `AXI_ASSIGN(slave_dv[i], slave[i]) + `AXI_ASSIGN_TO_REQ(slaves_req[i], slave[i]) + `AXI_ASSIGN_TO_RESP(slaves_resp[i], slave[i]) + end + // ------------------------------- + // AXI Rand Masters and Slaves + // ------------------------------- + // Masters control simulation run time + axi_rand_master_t axi_rand_master [TbNumMasters]; + for (genvar i = 0; i < TbNumMasters; i++) begin : gen_rand_master + initial begin + axi_rand_master[i] = new( master_dv[i] ); + end_of_sim[i] <= 1'b0; + axi_rand_master[i].add_memory_region(AddrMap[0].start_addr, + AddrMap[xbar_cfg.NoMulticastPorts-1].end_addr, + axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_master[i].add_memory_region(AddrMap[xbar_cfg.NoMulticastPorts].start_addr, + AddrMap[xbar_cfg.NoMulticastRules-1].end_addr, + axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_master[i].add_memory_region(AddrMap[xbar_cfg.NoMulticastRules].start_addr, + AddrMap[xbar_cfg.NoAddrRules-1].end_addr, + axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_master[i].set_multicast_probability(50); + axi_rand_master[i].reset(); + @(posedge rst_n); + axi_rand_master[i].run(TbNumReads, TbNumWrites); + end_of_sim[i] <= 1'b1; + end + end + + axi_rand_slave_t axi_rand_slave [TbNumSlaves]; + for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_rand_slave + initial begin + axi_rand_slave[i] = new( slave_dv[i] ); + axi_rand_slave[i].reset(); + @(posedge rst_n); + axi_rand_slave[i].run(); + end + end + + initial begin : proc_monitor + static tb_axi_xbar_pkg::axi_xbar_monitor #( + .AxiAddrWidth ( TbAxiAddrWidth ), + .AxiDataWidth ( TbAxiDataWidth ), + .AxiIdWidthMasters ( TbAxiIdWidthMasters ), + .AxiIdWidthSlaves ( TbAxiIdWidthSlaves ), + .AxiUserWidth ( TbAxiUserWidth ), + .NoMasters ( TbNumMasters ), + .NoSlaves ( TbNumSlaves ), + .NoAddrRules ( xbar_cfg.NoAddrRules ), + .NoMulticastRules ( xbar_cfg.NoMulticastRules ), + .rule_t ( rule_t ), + .AddrMap ( AddrMap ), + .TimeTest ( TestTime ) + ) monitor = new( master_monitor_dv, slave_monitor_dv ); + fork + monitor.run(); + do begin + #TestTime; + if(end_of_sim == '1) begin + monitor.print_result(); + $stop(); + end + @(posedge clk); + end while (1'b1); + join + end + + //----------------------------------- + // Clock generator + //----------------------------------- + clk_rst_gen #( + .ClkPeriod ( CyclTime ), + .RstClkCycles ( 5 ) + ) i_clk_gen ( + .clk_o (clk), + .rst_no(rst_n) + ); + + //----------------------------------- + // DUT + //----------------------------------- + + axi_mcast_xbar_intf #( + .AXI_USER_WIDTH ( TbAxiUserWidth ), + .Cfg ( xbar_cfg ), + .aw_user_t ( aw_user_t ), + .rule_t ( rule_t ) + ) i_xbar_dut ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .slv_ports ( master ), + .mst_ports ( slave ), + .addr_map_i ( AddrMap ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) + ); + + // logger for master modules + for (genvar i = 0; i < TbNumMasters; i++) begin : gen_master_logger + axi_chan_logger #( + .TestTime ( TestTime ), // Time after clock, where sampling happens + .LoggerName( $sformatf("axi_logger_master_%0d", i)), + .aw_chan_t ( aw_chan_mst_t ), // axi AW type + .w_chan_t ( w_chan_t ), // axi W type + .b_chan_t ( b_chan_mst_t ), // axi B type + .ar_chan_t ( ar_chan_mst_t ), // axi AR type + .r_chan_t ( r_chan_mst_t ), // axi R type + .ENABLE_MULTICAST(1) + ) i_mst_channel_logger ( + .clk_i ( clk ), // Clock + .rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling + .end_sim_i ( &end_of_sim ), + // AW channel + .aw_chan_i ( masters_req[i].aw ), + .aw_valid_i ( masters_req[i].aw_valid ), + .aw_ready_i ( masters_resp[i].aw_ready ), + // W channel + .w_chan_i ( masters_req[i].w ), + .w_valid_i ( masters_req[i].w_valid ), + .w_ready_i ( masters_resp[i].w_ready ), + // B channel + .b_chan_i ( masters_resp[i].b ), + .b_valid_i ( masters_resp[i].b_valid ), + .b_ready_i ( masters_req[i].b_ready ), + // AR channel + .ar_chan_i ( masters_req[i].ar ), + .ar_valid_i ( masters_req[i].ar_valid ), + .ar_ready_i ( masters_resp[i].ar_ready ), + // R channel + .r_chan_i ( masters_resp[i].r ), + .r_valid_i ( masters_resp[i].r_valid ), + .r_ready_i ( masters_req[i].r_ready ) + ); + end + // logger for slave modules + for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_slave_logger + axi_chan_logger #( + .TestTime ( TestTime ), // Time after clock, where sampling happens + .LoggerName( $sformatf("axi_logger_slave_%0d",i)), + .aw_chan_t ( aw_chan_slv_t ), // axi AW type + .w_chan_t ( w_chan_t ), // axi W type + .b_chan_t ( b_chan_slv_t ), // axi B type + .ar_chan_t ( ar_chan_slv_t ), // axi AR type + .r_chan_t ( r_chan_slv_t ) // axi R type + ) i_slv_channel_logger ( + .clk_i ( clk ), // Clock + .rst_ni ( rst_n ), // Asynchronous reset active low, when `1'b0` no sampling + .end_sim_i ( &end_of_sim ), + // AW channel + .aw_chan_i ( slaves_req[i].aw ), + .aw_valid_i ( slaves_req[i].aw_valid ), + .aw_ready_i ( slaves_resp[i].aw_ready ), + // W channel + .w_chan_i ( slaves_req[i].w ), + .w_valid_i ( slaves_req[i].w_valid ), + .w_ready_i ( slaves_resp[i].w_ready ), + // B channel + .b_chan_i ( slaves_resp[i].b ), + .b_valid_i ( slaves_resp[i].b_valid ), + .b_ready_i ( slaves_req[i].b_ready ), + // AR channel + .ar_chan_i ( slaves_req[i].ar ), + .ar_valid_i ( slaves_req[i].ar_valid ), + .ar_ready_i ( slaves_resp[i].ar_ready ), + // R channel + .r_chan_i ( slaves_resp[i].r ), + .r_valid_i ( slaves_resp[i].r_valid ), + .r_ready_i ( slaves_req[i].r_ready ) + ); + end + + + for (genvar i = 0; i < TbNumMasters; i++) begin : gen_connect_master_monitor + assign master_monitor_dv[i].aw_id = master[i].aw_id ; + assign master_monitor_dv[i].aw_addr = master[i].aw_addr ; + assign master_monitor_dv[i].aw_len = master[i].aw_len ; + assign master_monitor_dv[i].aw_size = master[i].aw_size ; + assign master_monitor_dv[i].aw_burst = master[i].aw_burst ; + assign master_monitor_dv[i].aw_lock = master[i].aw_lock ; + assign master_monitor_dv[i].aw_cache = master[i].aw_cache ; + assign master_monitor_dv[i].aw_prot = master[i].aw_prot ; + assign master_monitor_dv[i].aw_qos = master[i].aw_qos ; + assign master_monitor_dv[i].aw_region = master[i].aw_region; + assign master_monitor_dv[i].aw_atop = master[i].aw_atop ; + assign master_monitor_dv[i].aw_user = master[i].aw_user ; + assign master_monitor_dv[i].aw_valid = master[i].aw_valid ; + assign master_monitor_dv[i].aw_ready = master[i].aw_ready ; + assign master_monitor_dv[i].w_data = master[i].w_data ; + assign master_monitor_dv[i].w_strb = master[i].w_strb ; + assign master_monitor_dv[i].w_last = master[i].w_last ; + assign master_monitor_dv[i].w_user = master[i].w_user ; + assign master_monitor_dv[i].w_valid = master[i].w_valid ; + assign master_monitor_dv[i].w_ready = master[i].w_ready ; + assign master_monitor_dv[i].b_id = master[i].b_id ; + assign master_monitor_dv[i].b_resp = master[i].b_resp ; + assign master_monitor_dv[i].b_user = master[i].b_user ; + assign master_monitor_dv[i].b_valid = master[i].b_valid ; + assign master_monitor_dv[i].b_ready = master[i].b_ready ; + assign master_monitor_dv[i].ar_id = master[i].ar_id ; + assign master_monitor_dv[i].ar_addr = master[i].ar_addr ; + assign master_monitor_dv[i].ar_len = master[i].ar_len ; + assign master_monitor_dv[i].ar_size = master[i].ar_size ; + assign master_monitor_dv[i].ar_burst = master[i].ar_burst ; + assign master_monitor_dv[i].ar_lock = master[i].ar_lock ; + assign master_monitor_dv[i].ar_cache = master[i].ar_cache ; + assign master_monitor_dv[i].ar_prot = master[i].ar_prot ; + assign master_monitor_dv[i].ar_qos = master[i].ar_qos ; + assign master_monitor_dv[i].ar_region = master[i].ar_region; + assign master_monitor_dv[i].ar_user = master[i].ar_user ; + assign master_monitor_dv[i].ar_valid = master[i].ar_valid ; + assign master_monitor_dv[i].ar_ready = master[i].ar_ready ; + assign master_monitor_dv[i].r_id = master[i].r_id ; + assign master_monitor_dv[i].r_data = master[i].r_data ; + assign master_monitor_dv[i].r_resp = master[i].r_resp ; + assign master_monitor_dv[i].r_last = master[i].r_last ; + assign master_monitor_dv[i].r_user = master[i].r_user ; + assign master_monitor_dv[i].r_valid = master[i].r_valid ; + assign master_monitor_dv[i].r_ready = master[i].r_ready ; + end + for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_connect_slave_monitor + assign slave_monitor_dv[i].aw_id = slave[i].aw_id ; + assign slave_monitor_dv[i].aw_addr = slave[i].aw_addr ; + assign slave_monitor_dv[i].aw_len = slave[i].aw_len ; + assign slave_monitor_dv[i].aw_size = slave[i].aw_size ; + assign slave_monitor_dv[i].aw_burst = slave[i].aw_burst ; + assign slave_monitor_dv[i].aw_lock = slave[i].aw_lock ; + assign slave_monitor_dv[i].aw_cache = slave[i].aw_cache ; + assign slave_monitor_dv[i].aw_prot = slave[i].aw_prot ; + assign slave_monitor_dv[i].aw_qos = slave[i].aw_qos ; + assign slave_monitor_dv[i].aw_region = slave[i].aw_region; + assign slave_monitor_dv[i].aw_atop = slave[i].aw_atop ; + assign slave_monitor_dv[i].aw_user = slave[i].aw_user ; + assign slave_monitor_dv[i].aw_valid = slave[i].aw_valid ; + assign slave_monitor_dv[i].aw_ready = slave[i].aw_ready ; + assign slave_monitor_dv[i].w_data = slave[i].w_data ; + assign slave_monitor_dv[i].w_strb = slave[i].w_strb ; + assign slave_monitor_dv[i].w_last = slave[i].w_last ; + assign slave_monitor_dv[i].w_user = slave[i].w_user ; + assign slave_monitor_dv[i].w_valid = slave[i].w_valid ; + assign slave_monitor_dv[i].w_ready = slave[i].w_ready ; + assign slave_monitor_dv[i].b_id = slave[i].b_id ; + assign slave_monitor_dv[i].b_resp = slave[i].b_resp ; + assign slave_monitor_dv[i].b_user = slave[i].b_user ; + assign slave_monitor_dv[i].b_valid = slave[i].b_valid ; + assign slave_monitor_dv[i].b_ready = slave[i].b_ready ; + assign slave_monitor_dv[i].ar_id = slave[i].ar_id ; + assign slave_monitor_dv[i].ar_addr = slave[i].ar_addr ; + assign slave_monitor_dv[i].ar_len = slave[i].ar_len ; + assign slave_monitor_dv[i].ar_size = slave[i].ar_size ; + assign slave_monitor_dv[i].ar_burst = slave[i].ar_burst ; + assign slave_monitor_dv[i].ar_lock = slave[i].ar_lock ; + assign slave_monitor_dv[i].ar_cache = slave[i].ar_cache ; + assign slave_monitor_dv[i].ar_prot = slave[i].ar_prot ; + assign slave_monitor_dv[i].ar_qos = slave[i].ar_qos ; + assign slave_monitor_dv[i].ar_region = slave[i].ar_region; + assign slave_monitor_dv[i].ar_user = slave[i].ar_user ; + assign slave_monitor_dv[i].ar_valid = slave[i].ar_valid ; + assign slave_monitor_dv[i].ar_ready = slave[i].ar_ready ; + assign slave_monitor_dv[i].r_id = slave[i].r_id ; + assign slave_monitor_dv[i].r_data = slave[i].r_data ; + assign slave_monitor_dv[i].r_resp = slave[i].r_resp ; + assign slave_monitor_dv[i].r_last = slave[i].r_last ; + assign slave_monitor_dv[i].r_user = slave[i].r_user ; + assign slave_monitor_dv[i].r_valid = slave[i].r_valid ; + assign slave_monitor_dv[i].r_ready = slave[i].r_ready ; + end +endmodule diff --git a/test/tb_axi_sim_mem.sv b/test/tb_axi_sim_mem.sv index 76ddb03f8..018923ebe 100644 --- a/test/tb_axi_sim_mem.sv +++ b/test/tb_axi_sim_mem.sv @@ -100,7 +100,7 @@ module tb_axi_sim_mem #( wait (rst_n); // AW forever begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(aw_beat); assert (rand_success); @@ -121,7 +121,7 @@ module tb_axi_sim_mem #( drv.send_aw(aw_beat); // W beats for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); diff --git a/test/tb_axi_slave_compare.sv b/test/tb_axi_slave_compare.sv index 2fa47bdc7..407a63af4 100644 --- a/test/tb_axi_slave_compare.sv +++ b/test/tb_axi_slave_compare.sv @@ -82,7 +82,6 @@ module tb_axi_slave_compare #( ) i_axi_bus_compare ( .clk_i ( clk ), .rst_ni ( rst_n ), - .testmode_i ( 1'b0 ), .axi_mst_req_i ( axi_req ), .axi_mst_rsp_o ( axi_rsp ), .axi_ref_req_o ( axi_req_a_out ), @@ -188,7 +187,7 @@ module tb_axi_slave_compare #( drv.reset_master(); wait (rst_n); // AW -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(aw_beat) may behave differently to aw_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(aw_beat); assert (rand_success); @@ -203,7 +202,7 @@ module tb_axi_slave_compare #( drv.send_aw(aw_beat); // W beats for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin -`ifdef XSIM +`ifdef XILINX_SIMULATOR // std::randomize(w_beat) may behave differently to w_beat.randomize() wrt. limited ranges // Keeping alternate implementation for XSIM only rand_success = std::randomize(w_beat); assert (rand_success); diff --git a/test/tb_axi_to_axi_lite.sv b/test/tb_axi_to_axi_lite.sv index 39589af19..09d41f0f1 100644 --- a/test/tb_axi_to_axi_lite.sv +++ b/test/tb_axi_to_axi_lite.sv @@ -74,7 +74,6 @@ module tb_axi_to_axi_lite; ) i_dut ( .clk_i ( clk ), .rst_ni ( rst ), - .testmode_i ( 1'b0 ), .slv ( axi ), .mst ( axi_lite ) ); diff --git a/test/tb_axi_to_mem_banked.sv b/test/tb_axi_to_mem_banked.sv index 64667998d..c5b31daaa 100644 --- a/test/tb_axi_to_mem_banked.sv +++ b/test/tb_axi_to_mem_banked.sv @@ -165,7 +165,7 @@ module tb_axi_to_mem_banked #( assign mem_rvalid[i] = mem_req[i]; end else begin : gen_mem_lat logic [TbMemLatency-1:0] mem_lat_q, mem_lat_d; - `FFARN(mem_lat_q, mem_lat_d, '0, clk, rst_n) + `FF(mem_lat_q, mem_lat_d, '0, clk, rst_n) assign mem_lat_d[TbMemLatency-1] = mem_req[i]; if (TbMemLatency > 1) begin for (genvar lat_i = 0; lat_i < TbMemLatency - 1; lat_i++) begin @@ -198,7 +198,6 @@ module tb_axi_to_mem_banked #( ) i_axi_to_mem_banked_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .axi_to_mem_busy_o ( dut_busy ), .slv ( mem_axi ), .mem_req_o ( mem_req ), diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index bb54e69a8..1daf39956 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -76,7 +76,9 @@ module tb_axi_xbar #( UniqueIds: TbUniqueIds, AxiAddrWidth: TbAxiAddrWidth, AxiDataWidth: TbAxiDataWidth, - NoAddrRules: TbNumSlaves + NoAddrRules: TbNumSlaves, + NoMulticastRules: 0, + NoMulticastPorts: 0 }; typedef logic [TbAxiIdWidthMasters-1:0] id_mst_t; typedef logic [TbAxiIdWidthSlaves-1:0] id_slv_t; @@ -316,7 +318,6 @@ module tb_axi_xbar #( ) i_xbar_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), - .test_i ( 1'b0 ), .slv_ports ( master ), .mst_ports ( slave ), .addr_map_i ( AddrMap ), diff --git a/test/tb_axi_xbar.wave.do b/test/tb_axi_xbar.wave.do index 23a9095a2..06cac658e 100644 --- a/test/tb_axi_xbar.wave.do +++ b/test/tb_axi_xbar.wave.do @@ -3,13 +3,12 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -label Clock /tb_axi_xbar/i_xbar_dut/clk_i add wave -noupdate -label Reset /tb_axi_xbar/i_xbar_dut/rst_ni -add wave -noupdate -label {Test Mode} /tb_axi_xbar/i_xbar_dut/test_i add wave -noupdate -divider {Slave Ports} -add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_ports_req_i -add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_ports_resp_o +add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_reqs +add wave -noupdate /tb_axi_xbar/i_xbar_dut/slv_resps add wave -noupdate -divider {Master Ports} -add wave -noupdate /tb_axi_xbar/i_xbar_dut/mst_ports_req_o -add wave -noupdate /tb_axi_xbar/i_xbar_dut/mst_ports_resp_i +add wave -noupdate /tb_axi_xbar/i_xbar_dut/mst_reqs +add wave -noupdate /tb_axi_xbar/i_xbar_dut/mst_resps add wave -noupdate -divider {Address Mapping} add wave -noupdate /tb_axi_xbar/i_xbar_dut/addr_map_i add wave -noupdate /tb_axi_xbar/i_xbar_dut/en_default_mst_port_i diff --git a/test/tb_axi_xbar_pkg.sv b/test/tb_axi_xbar_pkg.sv index 3c90fcca1..895ced8f1 100644 --- a/test/tb_axi_xbar_pkg.sv +++ b/test/tb_axi_xbar_pkg.sv @@ -11,9 +11,10 @@ // Authors: // - Florian Zaruba // - Wolfgang Roenninger +// - Luca Colagrande -// `axi_xbar_monitor` implements an AXI bus monitor that is tuned for the AXI crossbar. -// It snoops on each of the slaves and master ports of the crossbar and +// `axi_xbar_monitor` implements an AXI bus monitor that is tuned for the AXI multicast +// crossbar. It snoops on each of the slaves and master ports of the crossbar and // populates FIFOs and ID queues to validate that no AXI beats get // lost or sent to the wrong destination. @@ -27,6 +28,7 @@ package tb_axi_xbar_pkg; parameter int unsigned NoMasters, parameter int unsigned NoSlaves, parameter int unsigned NoAddrRules, + parameter int unsigned NoMulticastRules = 0, parameter type rule_t, parameter rule_t [NoAddrRules-1:0] AddrMap, // Stimuli application and test time @@ -46,6 +48,7 @@ package tb_axi_xbar_pkg; typedef struct packed { slv_axi_id_t slv_axi_id; axi_addr_t slv_axi_addr; + axi_addr_t slv_axi_mcast; axi_pkg::len_t slv_axi_len; } exp_ax_t; typedef struct packed { @@ -148,50 +151,135 @@ package tb_axi_xbar_pkg; @(posedge masters_axi[0].clk_i); endtask - // This task monitors a slave ports of the crossbar. Every time an AW beat is seen - // it populates an id queue at the right master port (if there is no expected decode error), - // populates the expected b response in its own id_queue and in case when the atomic bit [5] + // This task monitors a slave port of the crossbar. Every time an AW beat is seen + // it populates an id queue at the right master port(s) (if there is no expected decode error), + // populates the expected b response in its own id_queue and in case the atomic bit [5] // is set it also injects an expected response in the R channel. task automatic monitor_mst_aw(input int unsigned i); - idx_slv_t to_slave_idx; - exp_ax_t exp_aw; - slv_axi_id_t exp_aw_id; - bit decerr; + axi_addr_t aw_addr; + axi_addr_t aw_mcast; + axi_addr_t rule_addr; + axi_addr_t rule_mask; + axi_addr_t aw_addr_masked; + axi_addr_t addrmap_masked; + idx_slv_t to_slave_idx[$]; + axi_addr_t addr_to_slave[$]; + axi_addr_t mask_to_slave[$]; + bit [NoSlaves-1:0] matched_slaves; + int unsigned num_slaves_matched; + bit decerr; + exp_ax_t exp_aw; + slv_axi_id_t exp_aw_id; + string slaves_str; master_exp_t exp_b; if (masters_axi[i].aw_valid && masters_axi[i].aw_ready) begin - // check if it should go to a decerror - decerr = 1'b1; - for (int unsigned j = 0; j < NoAddrRules; j++) begin - if ((masters_axi[i].aw_addr >= AddrMap[j].start_addr) && - (masters_axi[i].aw_addr < AddrMap[j].end_addr)) begin - to_slave_idx = idx_slv_t'(AddrMap[j].idx); - decerr = 1'b0; + + // Check to which slaves the transaction is directed or if it should go to a decerror. + // Store the indices of the selected slaves (to_slave_idx) and the filtered address + // sets {addr, mask} to be forwarded to each slave (addr_queue, mask_queue). + + // Get address information from request + aw_addr = masters_axi[i].aw_addr; + aw_mcast = masters_axi[i].aw_user[AxiAddrWidth-1:0]; + + // Set decode error by default, reset if a rule is matched in the following + decerr = 1; + + // When a mask is present, multicast rules are used, otherwise the unicast rules are used. + if (aw_mcast != '0) begin + + // Log masked address + for (int k = 0; k < AxiAddrWidth; k++) + aw_addr_masked[k] = aw_mcast[k] ? 1'bx : aw_addr[k]; + + $display("Trying to match: %x", aw_addr_masked); + + // Compare request against each multicast rule. We look at the rules starting from the + // last ones. In case of multiple rules matching for the same slave, we want only + // the last rule to have effect + for (int j = (NoMulticastRules - 1); j >= 0; j--) begin + + // Convert address rule to mask (NAPOT) form + rule_mask = AddrMap[j].end_addr - AddrMap[j].start_addr - 1; + rule_addr = AddrMap[j].start_addr; + for (int k = 0; k < AxiAddrWidth; k++) + addrmap_masked[k] = rule_mask[k] ? 1'bx : rule_addr[k]; + $display("With slave %3d : %b", AddrMap[j].idx, addrmap_masked); + + // Request goes to the slave if all bits match, out of those which are neither masked + // in the request nor in the addrmap rule + if (&(~(aw_addr ^ rule_addr) | rule_mask | aw_mcast)) begin + int unsigned slave_idx = AddrMap[j].idx; + decerr = 0; + + // Only push the request if we haven't already matched it with a previous rule + // for the same slave + if (!matched_slaves[slave_idx]) begin + matched_slaves[slave_idx] = 1'b1; + to_slave_idx.push_back(slave_idx); + mask_to_slave.push_back(aw_mcast & rule_mask); + addr_to_slave.push_back((~aw_mcast & aw_addr) | (aw_mcast & rule_addr)); + $display(" Push mask : %32b", aw_mcast & rule_mask); + $display(" Push address : %32b", (~aw_mcast & aw_addr) | (aw_mcast & rule_addr)); + end + end end - end - // send the exp aw beat down into the queue of the slave when no decerror - if (!decerr) begin - exp_aw_id = {idx_mst_t'(i), masters_axi[i].aw_id}; - // $display("Test exp aw_id: %b",exp_aw_id); - exp_aw = '{slv_axi_id: exp_aw_id, - slv_axi_addr: masters_axi[i].aw_addr, - slv_axi_len: masters_axi[i].aw_len }; - this.exp_aw_queue[to_slave_idx].push(exp_aw_id, exp_aw); - incr_expected_tests(3); - $display("%0tns > Master %0d: AW to Slave %0d: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + end else begin + + // Compare request against each interval-form rule. We look at the rules starting from + // the last ones. We ignore the case of multiple rules matching for the same slave + $display("Trying to match: %x", aw_addr); + for (int j = (NoAddrRules - 1); j >= 0; j--) begin + if ((aw_addr >= AddrMap[j].start_addr) && + (aw_addr < AddrMap[j].end_addr)) begin + decerr = 0; + to_slave_idx.push_back(AddrMap[j].idx); + addr_to_slave.push_back(aw_addr); + mask_to_slave.push_back('0); + $display(" Push address : %x", aw_addr); + end + end + + end + + num_slaves_matched = to_slave_idx.size(); + + // send the exp aw beats down into the queues of the selected slaves + // when no decerror + if (decerr) begin $display("%0tns > Master %0d: AW to Decerror: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + $time, i, masters_axi[i].aw_id); + end else begin + exp_aw_id = {idx_mst_t'(i), masters_axi[i].aw_id}; + for (int j = 0; j < num_slaves_matched; j++) begin + automatic idx_slv_t slave_idx = to_slave_idx.pop_front(); + // $display("Test exp aw_id: %b",exp_aw_id); + exp_aw = '{slv_axi_id: exp_aw_id, + slv_axi_addr: addr_to_slave.pop_front(), + slv_axi_mcast: mask_to_slave.pop_front(), + slv_axi_len: masters_axi[i].aw_len}; + this.exp_aw_queue[slave_idx].push(exp_aw_id, exp_aw); + incr_expected_tests(4); + if (j == 0) slaves_str = $sformatf("%0d", slave_idx); + else slaves_str = $sformatf("%s, %0d", slaves_str, slave_idx); + end + $display("%0tns > Master %0d: AW to Slaves [%s]: Axi ID: %b", + $time, i, slaves_str, masters_axi[i].aw_id); end + // populate the expected b queue anyway exp_b = '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1}; this.exp_b_queue[i].push(masters_axi[i].aw_id, exp_b); incr_expected_tests(1); $display(" Expect B response."); + // inject expected r beats on this id, if it is an atop + // throw an error if a multicast atop is attempted (not supported) if(masters_axi[i].aw_atop[5]) begin + if (num_slaves_matched > 1) $fatal(0, "Multicast ATOPs are not supported"); // push the required r beats into the right fifo (reuse the exp_b variable) $display(" Expect R response, len: %0d.", masters_axi[i].aw_len); for (int unsigned j = 0; j <= masters_axi[i].aw_len; j++) begin @@ -205,7 +293,7 @@ package tb_axi_xbar_pkg; end endtask : monitor_mst_aw - // This task monitors a slave port of the crossbar. Every time there is an AW vector it + // This task monitors a master port of the crossbar. Every time there is an AW vector it // gets checked for its contents and if it was expected. The task then pushes an expected // amount of W beats in the respective fifo. Emphasis of the last flag. task automatic monitor_slv_aw(input int unsigned i); @@ -227,14 +315,21 @@ package tb_axi_xbar_pkg; $warning("Slave %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", i, slaves_axi[i].aw_id, slaves_axi[i].aw_addr, exp_aw.slv_axi_addr); end + if (exp_aw.slv_axi_mcast != slaves_axi[i].aw_user[AxiAddrWidth-1:0]) begin + incr_failed_tests(1); + $warning("Slave %0d: Unexpected AW with ID: %b and MCAST: %h, exp: %h", + i, slaves_axi[i].aw_id, slaves_axi[i].aw_user[AxiAddrWidth-1:0], + exp_aw.slv_axi_mcast); + end if (exp_aw.slv_axi_len != slaves_axi[i].aw_len) begin incr_failed_tests(1); $warning("Slave %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", i, slaves_axi[i].aw_id, slaves_axi[i].aw_len, exp_aw.slv_axi_len); end - incr_conducted_tests(3); + incr_conducted_tests(4); // push the required w beats into the right fifo + $display(" Expect %0d W beats.", slaves_axi[i].aw_len + 1); incr_expected_tests(slaves_axi[i].aw_len + 1); for (int unsigned j = 0; j <= slaves_axi[i].aw_len; j++) begin exp_slv_w = (j == slaves_axi[i].aw_len) ? @@ -334,13 +429,14 @@ package tb_axi_xbar_pkg; // push the expected vectors AW for exp_slv exp_slv_ar = '{slv_axi_id: exp_slv_axi_id, slv_axi_addr: mst_axi_addr, - slv_axi_len: mst_axi_len }; + slv_axi_mcast: '0, + slv_axi_len: mst_axi_len}; //$display("Expected Slv Axi Id is: %b", exp_slv_axi_id); this.exp_ar_queue[exp_slv_idx].push(exp_slv_axi_id, exp_slv_ar); incr_expected_tests(1); end // push the required r beats into the right fifo - $display(" Expect R response, len: %0d.", masters_axi[i].ar_len); + $display(" Expect R response, len: %0d.", mst_axi_len); for (int unsigned j = 0; j <= mst_axi_len; j++) begin exp_mst_r = (j == mst_axi_len) ? '{mst_axi_id: mst_axi_id, last: 1'b1} : '{mst_axi_id: mst_axi_id, last: 1'b0}; @@ -498,6 +594,12 @@ package tb_axi_xbar_pkg; if(tests_conducted == 0) begin $error("Simulation did not conduct any tests!"); end + if (tests_conducted < tests_expected) begin + $error("Some of the expected tests were not conducted!"); + end + if (tests_conducted > tests_expected) begin + $error("Conducted more than the expected tests!"); + end endtask : print_result endclass : axi_xbar_monitor endpackage