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Update Tutorials to support Agilex5 (#2313)
* Update Tutorials to support Agilex5 * Small changes * Attend to comments and merge conflicts * Update Shannonization tutorial * More addressing of merge conflicts
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‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/autorun/README.md‎

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|:--- |:---
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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/buffered_host_streaming/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/compute_units/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/double_buffering/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/explicit_data_movement/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/io_streaming/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/loop_carried_dependency/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/n_way_buffering/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/onchip_memory_cache/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
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| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ oneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

‎DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/optimize_inner_loop/README.md‎

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| OS | Ubuntu* 20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10 <br> Windows Server* 2019
22-
| Hardware | Intel® Agilex® 7, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Hardware | Intel® Agilex® 7, Agilex® 5, Arria® 10, Stratix® 10, and Cyclone® V FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel® oneAPI DPC++/C++ Compiler is enough to compile for emulation, generating reports, generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.

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