Document community-tested compatibility with PPU-ZW810E

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Motivation

AReno currently documents Linux with NVIDIA CUDA GPUs as its supported environment. However, PPU-ZW810E provides a CUDA-compatible software stack, including CUDA-enabled PyTorch, compiler/runtime interfaces, and PyTorch CUDA Extension support.

I completed a community validation of AReno 0.0.6 on PPU-ZW810E. The existing AReno CUDA backend worked without introducing a separate PPU backend or modifying the custom CUDA operators.

Documenting this result could help users understand that some non-NVIDIA accelerators with a sufficiently complete CUDA compatibility layer may be able to reuse AReno's existing CUDA backend, while clearly distinguishing community validation from official hardware support.

Validation environment

• AReno: 0.0.6
• Accelerator: PPU-ZW810E
• Visible devices: 16
• Validated configuration: single device (world_size=1, tp_size=1)
• OS: Ubuntu 24.04.2 LTS
• Python: 3.12.3
• PyTorch: 2.8.0
• torch.version.cuda: 12.9
• Triton: 3.4.0 with vendor adaptation
• FlashAttention: 2.7.4.post1
• flash-linear-attention: 0.5.2
• fla-core: 0.5.2
• End-to-end attention backend: native

The PPU image exposes the accelerator through standard PyTorch CUDA interfaces:

• torch.cuda.is_available() returns True
• torch.cuda.get_device_name(0) returns PPU-ZW810E
• CUDA capability is exposed as 8.0
• PyTorch CUDA Extension headers and runtime libraries are available
• A minimal CUDA Extension compiled and executed correctly

AReno installation

AReno was installed from source while preserving the vendor-adapted PyTorch and Triton packages:

python -m pip install \
  -e . \
  --no-deps \
  --no-build-isolation \
  -v

The complete AReno CUDA Extension compiled successfully:

areno/accel/_areno_accel.cpython-312-x86_64-linux-gnu.so

A total of 43 AReno custom operators were registered.

Operator validation

The following operators were compared against PyTorch reference implementations:

Test	Result
SiLU FP32/FP16/BF16	Passed
Linear FP32/FP16/BF16	Passed with documented numerical differences
RMSNorm forward/backward	Passed
Linear forward/backward	Passed
Causal Attention forward/backward	Passed
Output and gradient finiteness	Passed
Illegal memory access	Not observed

Representative numerical results:

• SiLU FP32 maximum absolute difference: approximately 4.77e-7
• Linear FP16 relative L2 error: approximately 3.84e-4
• Linear BF16 relative L2 error: approximately 2.85e-3
• Causal Attention FP16 output relative L2 error: approximately 7.89e-6
• Causal Attention BF16 Q/K gradient relative L2 error: below 2.1e-3
• All tested outputs and gradients remained finite

One FP32 behavior difference was observed: the AReno Linear kernel follows a Tensor Core/TF32-style calculation path. It matches PyTorch when TF32 is enabled, while disabling TF32 in PyTorch produces a relative L2 difference of approximately 2.92e-4.

End-to-end SFT validation

The following path was validated:

• Model: Qwen/Qwen3-0.6B
• Algorithm: SFT
• Dataset: AI-ModelScope/alpaca-gpt4-data-zh
• Single PPU
• Native Attention
• Forward pass, backward pass, and optimizer updates
• Continuous training on real Chinese instruction data

The training process remained stable without unsupported operator errors, illegal memory access, NaN/Inf loss, custom operator loading failures, or runtime crashes. Device utilization reached approximately 98% during training.

Proposed documentation and diagnostics improvements

Would the maintainers be open to:

1. Adding a community-tested hardware compatibility section or matrix.
2. Listing PPU-ZW810E as community validated for single-device Qwen3 SFT with Native Attention.
3. Clarifying that CUDA-compatible accelerators may reuse AReno's existing CUDA backend when they provide compatible PyTorch, compiler, and runtime layers.
4. Making diagnostic wording such as NVIDIA GPU visibility more vendor-neutral while keeping official support boundaries explicit.
5. Documenting that vendor-adapted PyTorch/Triton environments should install AReno with --no-deps to avoid replacing vendor packages.

I can prepare a small documentation and diagnostics PR if this direction is acceptable.

Alternatives considered

A separate PPU backend was considered, but the validation indicates that it is currently unnecessary. PPU exposes CUDA-compatible PyTorch, runtime, compiler, and Extension interfaces, allowing AReno to reuse the existing CUDA backend.

Maintaining these findings only in an external document is another option, but an upstream community-tested compatibility note would be easier for users to discover and would communicate the exact validation scope more clearly.

Current validation boundaries

This report does not claim complete AReno feature coverage. The following areas have not yet been validated:

• Multi-GPU training and collective communication
• Flash Attention backend in an end-to-end AReno training run
• GSPO, GRPO, PPO, and DPO
• Other model families
• Serving
• Checkpoint save and recovery
• Long-term convergence equivalence with NVIDIA GPUs

The currently confirmed scope is single-device Qwen3 SFT with Native Attention.