From 5e515641c8faf007fdb819175ef451b2435a24a5 Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Wed, 15 Jul 2026 10:05:01 +0000
Subject: [PATCH 1/8] add cri

Signed-off-by: jiqing-feng <jiqing.feng@intel.com>
---
 .../cutlass-gemm/torch-ext/registration.h     | 12 +++++
 .../templates/xpu/dep-sycl-tla.cmake          | 54 +++++++++++++++++--
 2 files changed, 61 insertions(+), 5 deletions(-)

diff --git a/examples/kernels/cutlass-gemm/torch-ext/registration.h b/examples/kernels/cutlass-gemm/torch-ext/registration.h
index 4d0ce1c57..096da4beb 100644
--- a/examples/kernels/cutlass-gemm/torch-ext/registration.h
+++ b/examples/kernels/cutlass-gemm/torch-ext/registration.h
@@ -1,3 +1,6 @@
+// Registration macros from vLLM:
+// https://github.com/vllm-project/vllm/blob/main/csrc/core/registration.h
+
 #pragma once
 
 #include <Python.h>
@@ -12,11 +15,20 @@
 // could be a macro instead of a literal token.
 #define TORCH_LIBRARY_EXPAND(NAME, MODULE) TORCH_LIBRARY(NAME, MODULE)
 
+// A version of the STABLE_TORCH_LIBRARY macro that expands the NAME, i.e. so NAME
+// could be a macro instead of a literal token.
+#define STABLE_TORCH_LIBRARY_EXPAND(NAME, MODULE) STABLE_TORCH_LIBRARY(NAME, MODULE)
+
 // A version of the TORCH_LIBRARY_IMPL macro that expands the NAME, i.e. so NAME
 // could be a macro instead of a literal token.
 #define TORCH_LIBRARY_IMPL_EXPAND(NAME, DEVICE, MODULE) \
   TORCH_LIBRARY_IMPL(NAME, DEVICE, MODULE)
 
+// A version of the STABLE_TORCH_LIBRARY_IMPL macro that expands the NAME, i.e. so NAME
+// could be a macro instead of a literal token.
+#define STABLE_TORCH_LIBRARY_IMPL_EXPAND(NAME, DEVICE, MODULE) \
+  STABLE_TORCH_LIBRARY_IMPL(NAME, DEVICE, MODULE)
+
 // REGISTER_EXTENSION allows the shared library to be loaded and initialized
 // via python's import statement.
 #define REGISTER_EXTENSION(NAME)                                               \
diff --git a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
index 200364780..f8129489f 100644
--- a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
+++ b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
@@ -68,12 +68,56 @@ if(SYCL_TLA_REVISION MATCHES "^v3\\.9")
   add_compile_definitions(OLD_API=1)
 endif()
 
-string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=spir64" sycl_link_flags "${sycl_link_flags}")
-string(REPLACE "-device pvc,xe-lpg,ats-m150" "-device bmg_g21,pvc" sycl_link_flags "${sycl_link_flags}")
-string(APPEND sycl_link_flags "-Xspirv-translator;-spirv-ext=+SPV_INTEL_split_barrier")
+# Select the XPU compilation target(s) via the KERNEL_XPU_TARGET environment
+# variable. This controls which Intel GPU targets are baked into the produced
+# extension .so:
+#   unset / "bmg" : BMG + PVC, JIT-compiled through spir64 (default, unchanged).
+#   "cri"         : CRI only, ahead-of-time compiled for intel_gpu_cri.
+#   "both"        : CRI (AOT, intel_gpu_cri) and BMG/PVC (JIT, spir64) fused
+#                   into a single fat binary that loads on both device families.
+if(DEFINED ENV{KERNEL_XPU_TARGET})
+  set(KERNEL_XPU_TARGET "$ENV{KERNEL_XPU_TARGET}")
+else()
+  set(KERNEL_XPU_TARGET "bmg")
+endif()
+message(STATUS "sycl-tla KERNEL_XPU_TARGET: ${KERNEL_XPU_TARGET}")
+
+# SPIR-V extensions required by sycl-tla. The extra block-IO / matrix-multiply
+# extensions are only available on newer DPCPP / sycl-tla combinations.
+set(SYCL_TLA_SPIRV_EXT "+SPV_INTEL_split_barrier")
 if(DPCPP_VERSION STREQUAL "2025.2" OR DPCPP_VERSION STREQUAL "2025.3" OR DPCPP_VERSION STREQUAL "2026.0" OR SYCL_TLA_REVISION STREQUAL "v0.5")
-  string(APPEND sycl_link_flags ",+SPV_INTEL_2d_block_io,+SPV_INTEL_subgroup_matrix_multiply_accumulate")
+  string(APPEND SYCL_TLA_SPIRV_EXT ",+SPV_INTEL_2d_block_io,+SPV_INTEL_subgroup_matrix_multiply_accumulate")
+endif()
+
+if(KERNEL_XPU_TARGET STREQUAL "cri")
+  # CRI: AOT-compile directly for the intel_gpu_cri target. The BMG/PVC
+  # ahead-of-time device options are not valid for intel_gpu_cri and are dropped.
+  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri" sycl_link_flags "${sycl_link_flags}")
+  string(REPLACE "-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';" "" sycl_link_flags "${sycl_link_flags}")
+  string(APPEND sycl_link_flags "-Xspirv-translator=intel_gpu_cri;-spirv-ext=${SYCL_TLA_SPIRV_EXT}")
+  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri" sycl_flags "${sycl_flags}")
+elseif(KERNEL_XPU_TARGET STREQUAL "both")
+  # CRI (AOT) + BMG/PVC (JIT) fused into a single fat binary. The two device
+  # targets are compiled from the same sources; the SYCL compiler emits
+  # per-target code based on the built-in __SYCL_TARGET_INTEL_GPU_CRI__ macro.
+  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri,spir64" sycl_link_flags "${sycl_link_flags}")
+  # Bind the BMG/PVC ahead-of-time device options to the spir64 target only, so
+  # they are not applied to the intel_gpu_cri target.
+  string(REPLACE "-Xs;-device pvc,xe-lpg,ats-m150" "-Xsycl-target-backend=spir64;-device bmg_g21,pvc" sycl_link_flags "${sycl_link_flags}")
+  # With multiple targets the SPIR-V translator options must name the triple
+  # explicitly. Both targets need the identical -spirv-ext list, so each
+  # -Xspirv-translator=<triple> -spirv-ext=... pair is wrapped in a SHELL:
+  # group. SHELL: keeps the two tokens together and prevents CMake from
+  # de-duplicating the identical -spirv-ext arguments (which would otherwise
+  # strip the second one and break the spir64 translator invocation).
+  string(APPEND sycl_link_flags "SHELL:-Xspirv-translator=intel_gpu_cri -spirv-ext=${SYCL_TLA_SPIRV_EXT};SHELL:-Xspirv-translator=spir64 -spirv-ext=${SYCL_TLA_SPIRV_EXT}")
+  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri,spir64" sycl_flags "${sycl_flags}")
+else()
+  # Default: BMG + PVC, JIT-compiled through spir64 (unchanged behaviour).
+  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=spir64" sycl_link_flags "${sycl_link_flags}")
+  string(REPLACE "-device pvc,xe-lpg,ats-m150" "-device bmg_g21,pvc" sycl_link_flags "${sycl_link_flags}")
+  string(APPEND sycl_link_flags "-Xspirv-translator;-spirv-ext=${SYCL_TLA_SPIRV_EXT}")
+  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=spir64" sycl_flags "${sycl_flags}")
 endif()
-string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=spir64" sycl_flags "${sycl_flags}")
 
 endif(GPU_LANG STREQUAL "SYCL")

From 18c964e52268d6c85bd69f63028585d9fa12e3cd Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Wed, 15 Jul 2026 15:47:18 +0000
Subject: [PATCH 2/8] update cri compile

Signed-off-by: jiqing-feng <jiqing.feng@intel.com>
---
 .../pyproject/templates/torch/preamble.cmake  | 33 +++++++-
 .../templates/tvm_ffi/preamble.cmake          | 33 +++++++-
 .../templates/xpu/dep-sycl-tla.cmake          | 77 ++++++++-----------
 3 files changed, 94 insertions(+), 49 deletions(-)

diff --git a/kernel-builder/src/pyproject/templates/torch/preamble.cmake b/kernel-builder/src/pyproject/templates/torch/preamble.cmake
index ba75b461b..fc21f083b 100644
--- a/kernel-builder/src/pyproject/templates/torch/preamble.cmake
+++ b/kernel-builder/src/pyproject/templates/torch/preamble.cmake
@@ -204,8 +204,37 @@ elseif(GPU_LANG STREQUAL "SYCL")
   endif()
 
 
-  set(sycl_link_flags "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=spir64_gen,spir64;-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';")
-  set(sycl_flags "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=spir64_gen,spir64;")
+  # --- SYCL fat-binary flags ------------------------------------------------
+  # One .so carries an AOT image per GPU in SYCL_AOT_DEVICES plus a spir64 JIT
+  # fallback; the runtime picks the matching image at load time.
+  # These variables are the single source of truth: a dependency may change them
+  # and call xpu_compose_sycl_flags() again to rebuild the flags.
+  set(SYCL_OFFLOAD_TARGETS "spir64_gen,spir64")
+  set(SYCL_AOT_DEVICES "pvc,xe-lpg,ats-m150")
+  set(SYCL_AOT_BACKEND_OPTIONS " -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required")
+  set(SYCL_SPIRV_EXT "")
+
+  # Rebuild sycl_flags (compile) and sycl_link_flags (link) from the variables
+  # above. A macro so it runs in the including scope and can be re-invoked.
+  macro(xpu_compose_sycl_flags)
+    set(sycl_flags
+      "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS}")
+
+    # spir64_gen bakes the per-device AOT images; -device selects the GPUs.
+    set(sycl_link_flags
+      "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS};-Xsycl-target-backend=spir64_gen;-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'")
+
+    # SYCL_SPIRV_EXT must be a COMPLETE list: the translator treats the last
+    # -spirv-ext as a replacement, so a short list drops defaults (e.g. bfloat16).
+    # Bare -Xspirv-translator (no triple) targets the single spir64_gen image;
+    # SHELL: keeps the option and value together.
+    if(SYCL_SPIRV_EXT)
+      string(APPEND sycl_link_flags
+        ";SHELL:-Xspirv-translator -spirv-ext=${SYCL_SPIRV_EXT}")
+    endif()
+  endmacro()
+
+  xpu_compose_sycl_flags()
   set(GPU_FLAGS "${sycl_flags}")
 
 
diff --git a/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake b/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
index 2eefe6549..1b30249da 100644
--- a/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
+++ b/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
@@ -135,8 +135,37 @@ elseif(GPU_LANG STREQUAL "SYCL")
     message(STATUS "Using Intel SYCL C++ compiler: ${ICPX_COMPILER} and C compiler: ${ICX_COMPILER} Version: ${DPCPP_VERSION}")
   endif()
 
-  set(sycl_link_flags "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=spir64_gen,spir64;-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';")
-  set(sycl_flags "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=spir64_gen,spir64;")
+  # --- SYCL fat-binary flags ------------------------------------------------
+  # One .so carries an AOT image per GPU in SYCL_AOT_DEVICES plus a spir64 JIT
+  # fallback; the runtime picks the matching image at load time.
+  # These variables are the single source of truth: a dependency may change them
+  # and call xpu_compose_sycl_flags() again to rebuild the flags.
+  set(SYCL_OFFLOAD_TARGETS "spir64_gen,spir64")
+  set(SYCL_AOT_DEVICES "pvc,xe-lpg,ats-m150")
+  set(SYCL_AOT_BACKEND_OPTIONS " -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required")
+  set(SYCL_SPIRV_EXT "")
+
+  # Rebuild sycl_flags (compile) and sycl_link_flags (link) from the variables
+  # above. A macro so it runs in the including scope and can be re-invoked.
+  macro(xpu_compose_sycl_flags)
+    set(sycl_flags
+      "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS}")
+
+    # spir64_gen bakes the per-device AOT images; -device selects the GPUs.
+    set(sycl_link_flags
+      "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS};-Xsycl-target-backend=spir64_gen;-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'")
+
+    # SYCL_SPIRV_EXT must be a COMPLETE list: the translator treats the last
+    # -spirv-ext as a replacement, so a short list drops defaults (e.g. bfloat16).
+    # Bare -Xspirv-translator (no triple) targets the single spir64_gen image;
+    # SHELL: keeps the option and value together.
+    if(SYCL_SPIRV_EXT)
+      string(APPEND sycl_link_flags
+        ";SHELL:-Xspirv-translator -spirv-ext=${SYCL_SPIRV_EXT}")
+    endif()
+  endmacro()
+
+  xpu_compose_sycl_flags()
   set(GPU_FLAGS "${sycl_flags}")
 
   add_compile_definitions(XPU_KERNEL)
diff --git a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
index f8129489f..cdababf08 100644
--- a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
+++ b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
@@ -68,56 +68,43 @@ if(SYCL_TLA_REVISION MATCHES "^v3\\.9")
   add_compile_definitions(OLD_API=1)
 endif()
 
-# Select the XPU compilation target(s) via the KERNEL_XPU_TARGET environment
-# variable. This controls which Intel GPU targets are baked into the produced
-# extension .so:
-#   unset / "bmg" : BMG + PVC, JIT-compiled through spir64 (default, unchanged).
-#   "cri"         : CRI only, ahead-of-time compiled for intel_gpu_cri.
-#   "both"        : CRI (AOT, intel_gpu_cri) and BMG/PVC (JIT, spir64) fused
-#                   into a single fat binary that loads on both device families.
-if(DEFINED ENV{KERNEL_XPU_TARGET})
-  set(KERNEL_XPU_TARGET "$ENV{KERNEL_XPU_TARGET}")
-else()
-  set(KERNEL_XPU_TARGET "bmg")
-endif()
-message(STATUS "sycl-tla KERNEL_XPU_TARGET: ${KERNEL_XPU_TARGET}")
+# --- Retarget the fat binary at the Xe2 GPUs for sycl-tla kernels -----------
+# sycl-tla (flash-attn2 etc.) needs Xe2 matrix features (DPAS, 2D block IO,
+# bfloat16) that xe-lpg and ats-m150 cannot compile, so REPLACE the device list
+# with the Xe2 discrete GPUs. Still one .so with one AOT image per device.
+set(SYCL_AOT_DEVICES "pvc,bmg,cri")
 
-# SPIR-V extensions required by sycl-tla. The extra block-IO / matrix-multiply
-# extensions are only available on newer DPCPP / sycl-tla combinations.
-set(SYCL_TLA_SPIRV_EXT "+SPV_INTEL_split_barrier")
+# AOT-only: a spir64 JIT fallback is unneeded (kernels build only for these GPUs)
+# and unsupported alongside a per-target -spirv-ext list.
+set(SYCL_OFFLOAD_TARGETS "spir64_gen")
+
+# sycl-tla needs extra extensions (split-barrier always; block-IO and
+# matrix-multiply on newer DPCPP). Since the translator replaces the whole
+# -spirv-ext list, we query the driver's defaults and append the extras.
+set(_sycl_tla_extra_ext "+SPV_INTEL_split_barrier")
 if(DPCPP_VERSION STREQUAL "2025.2" OR DPCPP_VERSION STREQUAL "2025.3" OR DPCPP_VERSION STREQUAL "2026.0" OR SYCL_TLA_REVISION STREQUAL "v0.5")
-  string(APPEND SYCL_TLA_SPIRV_EXT ",+SPV_INTEL_2d_block_io,+SPV_INTEL_subgroup_matrix_multiply_accumulate")
+  string(APPEND _sycl_tla_extra_ext ",+SPV_INTEL_2d_block_io,+SPV_INTEL_subgroup_matrix_multiply_accumulate")
 endif()
 
-if(KERNEL_XPU_TARGET STREQUAL "cri")
-  # CRI: AOT-compile directly for the intel_gpu_cri target. The BMG/PVC
-  # ahead-of-time device options are not valid for intel_gpu_cri and are dropped.
-  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri" sycl_link_flags "${sycl_link_flags}")
-  string(REPLACE "-Xs;-device pvc,xe-lpg,ats-m150 -options ' -cl-intel-enable-auto-large-GRF-mode -cl-poison-unsupported-fp64-kernels -cl-intel-greater-than-4GB-buffer-required';" "" sycl_link_flags "${sycl_link_flags}")
-  string(APPEND sycl_link_flags "-Xspirv-translator=intel_gpu_cri;-spirv-ext=${SYCL_TLA_SPIRV_EXT}")
-  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri" sycl_flags "${sycl_flags}")
-elseif(KERNEL_XPU_TARGET STREQUAL "both")
-  # CRI (AOT) + BMG/PVC (JIT) fused into a single fat binary. The two device
-  # targets are compiled from the same sources; the SYCL compiler emits
-  # per-target code based on the built-in __SYCL_TARGET_INTEL_GPU_CRI__ macro.
-  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri,spir64" sycl_link_flags "${sycl_link_flags}")
-  # Bind the BMG/PVC ahead-of-time device options to the spir64 target only, so
-  # they are not applied to the intel_gpu_cri target.
-  string(REPLACE "-Xs;-device pvc,xe-lpg,ats-m150" "-Xsycl-target-backend=spir64;-device bmg_g21,pvc" sycl_link_flags "${sycl_link_flags}")
-  # With multiple targets the SPIR-V translator options must name the triple
-  # explicitly. Both targets need the identical -spirv-ext list, so each
-  # -Xspirv-translator=<triple> -spirv-ext=... pair is wrapped in a SHELL:
-  # group. SHELL: keeps the two tokens together and prevents CMake from
-  # de-duplicating the identical -spirv-ext arguments (which would otherwise
-  # strip the second one and break the spir64 translator invocation).
-  string(APPEND sycl_link_flags "SHELL:-Xspirv-translator=intel_gpu_cri -spirv-ext=${SYCL_TLA_SPIRV_EXT};SHELL:-Xspirv-translator=spir64 -spirv-ext=${SYCL_TLA_SPIRV_EXT}")
-  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=intel_gpu_cri,spir64" sycl_flags "${sycl_flags}")
+set(_sycl_ext_probe "${CMAKE_CURRENT_BINARY_DIR}/_sycl_spirv_ext_probe.cpp")
+file(WRITE "${_sycl_ext_probe}" "int main() { return 0; }\n")
+# "-###" MUST be quoted: an unquoted # starts a CMake comment and would drop the
+# rest of the COMMAND, making icpx read from stdin instead of dumping its flags.
+execute_process(
+  COMMAND ${ICPX_COMPILER} -fsycl -fsycl-targets=spir64_gen "-###" "${_sycl_ext_probe}"
+  OUTPUT_VARIABLE _sycl_ext_probe_out
+  ERROR_VARIABLE _sycl_ext_probe_err)
+string(REGEX MATCH "-spirv-ext=[^\" ]+" _sycl_default_ext "${_sycl_ext_probe_out}${_sycl_ext_probe_err}")
+if(_sycl_default_ext)
+  # Strip the "-spirv-ext=-all," prefix, leaving the "+ext,+ext,..." default set.
+  string(REGEX REPLACE "^-spirv-ext=(-all,)?" "" _sycl_default_ext "${_sycl_default_ext}")
+  set(SYCL_SPIRV_EXT "${_sycl_default_ext},${_sycl_tla_extra_ext}")
 else()
-  # Default: BMG + PVC, JIT-compiled through spir64 (unchanged behaviour).
-  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=spir64" sycl_link_flags "${sycl_link_flags}")
-  string(REPLACE "-device pvc,xe-lpg,ats-m150" "-device bmg_g21,pvc" sycl_link_flags "${sycl_link_flags}")
-  string(APPEND sycl_link_flags "-Xspirv-translator;-spirv-ext=${SYCL_TLA_SPIRV_EXT}")
-  string(REPLACE "-fsycl-targets=spir64_gen,spir64" "-fsycl-targets=spir64" sycl_flags "${sycl_flags}")
+  message(WARNING "Could not determine default SPIR-V extensions from ${ICPX_COMPILER}; "
+                  "using sycl-tla extras only, which may disable compiler defaults.")
+  set(SYCL_SPIRV_EXT "${_sycl_tla_extra_ext}")
 endif()
 
+xpu_compose_sycl_flags()
+
 endif(GPU_LANG STREQUAL "SYCL")

From bdfd49cba672231b826dca35bc5dbb96c6a84068 Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Thu, 16 Jul 2026 00:01:09 -0700
Subject: [PATCH 3/8] nix-builder: bump ocloc to 26.22.38646.4 for Crescent
 Island (cri)

ocloc 25.35 rejects the 'cri' device (Failed to parse target: cri - invalid
device), which breaks the pvc,bmg,cri fat-binary link. Bump compute-runtime to
26.22.38646.4 (IGC v2.36.3, gmmlib 22.10.0) whose ocloc recognises cri.
---
 nix-builder/pkgs/xpu-packages/ocloc.nix | 26 ++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/nix-builder/pkgs/xpu-packages/ocloc.nix b/nix-builder/pkgs/xpu-packages/ocloc.nix
index 80c02e167..d39cada0e 100644
--- a/nix-builder/pkgs/xpu-packages/ocloc.nix
+++ b/nix-builder/pkgs/xpu-packages/ocloc.nix
@@ -11,32 +11,32 @@
 
 stdenv.mkDerivation (finalAttrs: {
   pname = "ocloc";
-  version = "25.35";
+  version = "26.22";
 
   srcs = [
     (fetchurl {
-      url = "https://github.com/intel/compute-runtime/releases/download/25.35.35096.9/intel-ocloc_25.35.35096.9-0_amd64.deb";
-      hash = "sha256-AjzPj9iRKVi7PwCXcFbC+o3bzvjstLvHK9357LDuxvs=";
+      url = "https://github.com/intel/compute-runtime/releases/download/26.22.38646.4/intel-ocloc_26.22.38646.4-0_amd64.deb";
+      hash = "sha256-JXRYQeZiecf/H/bC1NqeyRFoXBLhycVgnZnk1Uo2TcA=";
     })
     (fetchurl {
-      url = "https://github.com/intel/intel-graphics-compiler/releases/download/v2.18.5/intel-igc-core-2_2.18.5+19820_amd64.deb";
-      hash = "sha256-fDQPRcTylOyjqXgKGz7ObUtpn9xR59yf+MXWMjxdjWQ=";
+      url = "https://github.com/intel/intel-graphics-compiler/releases/download/v2.36.3/intel-igc-core-2_2.36.3+21719_amd64.deb";
+      hash = "sha256-ngl1rHUBW0Meuy2oGoArn9HiijwnAxOpdWnNHmpsYEg=";
     })
     (fetchurl {
-      url = "https://github.com/intel/intel-graphics-compiler/releases/download/v2.18.5/intel-igc-opencl-2_2.18.5+19820_amd64.deb";
-      hash = "sha256-vLFDVIYXVnPxSxgO+4/Dn/MbdsYl4JsSU6B6cF78+cM=";
+      url = "https://github.com/intel/intel-graphics-compiler/releases/download/v2.36.3/intel-igc-opencl-2_2.36.3+21719_amd64.deb";
+      hash = "sha256-NQpSMx54S7f7ntQumTtcRLfmVi/HTSzzECsptqV2+oU=";
     })
     (fetchurl {
-      url = "https://github.com/intel/compute-runtime/releases/download/25.35.35096.9/intel-opencl-icd_25.35.35096.9-0_amd64.deb";
-      hash = "sha256-ifJSVTyTeyRW7pkZhY/yq2Xcaw3L0hnHOVNUhGWt8yU=";
+      url = "https://github.com/intel/compute-runtime/releases/download/26.22.38646.4/intel-opencl-icd_26.22.38646.4-0_amd64.deb";
+      hash = "sha256-b9rC6KKqz4ROv9kFIb9xArPrtE9pwbztGpeFp86Wo8I=";
     })
     (fetchurl {
-      url = "https://github.com/intel/compute-runtime/releases/download/25.35.35096.9/libigdgmm12_22.8.1_amd64.deb";
-      hash = "sha256-gQEU7wX01ExchvvC8LNGiBAvQVlqQHcqH/ekj132ns0=";
+      url = "https://github.com/intel/compute-runtime/releases/download/26.22.38646.4/libigdgmm12_22.10.0_amd64.deb";
+      hash = "sha256-YDGmPW6KEs5hwU78FfLI5ycGEobjgguFlObQBhXgTVQ=";
     })
     (fetchurl {
-      url = "https://github.com/intel/compute-runtime/releases/download/25.35.35096.9/libze-intel-gpu1_25.35.35096.9-0_amd64.deb";
-      hash = "sha256-phfUqwNRqPJxdDi+QyXKARB1hFDhDrb6AtYUrtElIHo=";
+      url = "https://github.com/intel/compute-runtime/releases/download/26.22.38646.4/libze-intel-gpu1_26.22.38646.4-0_amd64.deb";
+      hash = "sha256-i++fJOA/gm+TwHYIG9oTxqw6+9nkK5+48pj6tlIzDi8=";
     })
   ];
   dontStrip = true;

From ab9017f347deeebe5a36cdd2e33d4961189ed0e8 Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Thu, 16 Jul 2026 00:01:09 -0700
Subject: [PATCH 4/8] nix-builder: pin sycl-tla 2026.0 to upstream cri commit
 d54352d

The v0.9.1 tag predates the Crescent Island (cri) reverse-kernel support; pin to
the upstream commit that landed it (sycl-tla d54352d, 'Upstream CRI code #833')
so the Nix build can compile the cri AOT images. Revert to a released tag once
one containing cri is available.
---
 nix-builder/pkgs/xpu-packages/sycl-tla.nix | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/nix-builder/pkgs/xpu-packages/sycl-tla.nix b/nix-builder/pkgs/xpu-packages/sycl-tla.nix
index fbd6fc9d4..0f86843f9 100644
--- a/nix-builder/pkgs/xpu-packages/sycl-tla.nix
+++ b/nix-builder/pkgs/xpu-packages/sycl-tla.nix
@@ -19,8 +19,9 @@ let
       hash = "sha256-xXAxIDBesjDDOIa6/YsGznyW+5+NpaO1L96lBuqRzrk=";
     };
     "2026.0" = {
-      version = "0.9.1";
-      hash = "sha256-c8ecf042tO9ChTiFav9vQvHhhVZyk1YH5govfWOxfF0=";
+      version = "0.9.1-main-d54352d";
+      rev = "d54352dffe8daab532abd88fc6ab0e9c9fbc6d62";
+      hash = "sha256-Hn51Ah1wEscOnrt9O/aXBW7IC6Mcl4gUWynAmDeAOlM=";
     };
   };
   syclTlaVersion =

From d1e72a13168e932f2de9ad3b5f9a13f7fb083ed4 Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Tue, 21 Jul 2026 00:57:02 -0700
Subject: [PATCH 5/8] kernel-builder: tri-target fat binary (pvc + bmg
 fp16/bf16 + cri MXFP)

Build one .so with three AOT images. fp16/bf16 kernels compile for
intel_gpu_pvc,intel_gpu_bmg_g21,spir64_gen; MXFP kernels are gated behind
__SYCL_TARGET_INTEL_GPU_CRI__ and compile spir64_gen-only, AOT-lowered to
cri via -device cri. Emit one -Xspirv-translator=<alias> per offload target
so the custom -spirv-ext reaches every image (translator replaces, not merges).
---
 .../pyproject/templates/torch/preamble.cmake   | 14 ++++++++------
 .../pyproject/templates/xpu/dep-sycl-tla.cmake | 18 ++++++++++--------
 2 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/kernel-builder/src/pyproject/templates/torch/preamble.cmake b/kernel-builder/src/pyproject/templates/torch/preamble.cmake
index fc21f083b..8c2fb0758 100644
--- a/kernel-builder/src/pyproject/templates/torch/preamble.cmake
+++ b/kernel-builder/src/pyproject/templates/torch/preamble.cmake
@@ -224,13 +224,15 @@ elseif(GPU_LANG STREQUAL "SYCL")
     set(sycl_link_flags
       "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS};-Xsycl-target-backend=spir64_gen;-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'")
 
-    # SYCL_SPIRV_EXT must be a COMPLETE list: the translator treats the last
-    # -spirv-ext as a replacement, so a short list drops defaults (e.g. bfloat16).
-    # Bare -Xspirv-translator (no triple) targets the single spir64_gen image;
-    # SHELL: keeps the option and value together.
+    # SYCL_SPIRV_EXT must be a COMPLETE list (translator replaces, not merges).
+    # A custom -spirv-ext only reaches an image whose triple matches the exact
+    # fsycl-targets alias, so emit one -Xspirv-translator=<alias> per target.
     if(SYCL_SPIRV_EXT)
-      string(APPEND sycl_link_flags
-        ";SHELL:-Xspirv-translator -spirv-ext=${SYCL_SPIRV_EXT}")
+      string(REPLACE "," ";" _sycl_ext_targets "${SYCL_OFFLOAD_TARGETS}")
+      foreach(_tgt IN LISTS _sycl_ext_targets)
+        string(APPEND sycl_link_flags
+          ";SHELL:-Xspirv-translator=${_tgt} -spirv-ext=${SYCL_SPIRV_EXT}")
+      endforeach()
     endif()
   endmacro()
 
diff --git a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
index cdababf08..bd21c73de 100644
--- a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
+++ b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
@@ -68,15 +68,17 @@ if(SYCL_TLA_REVISION MATCHES "^v3\\.9")
   add_compile_definitions(OLD_API=1)
 endif()
 
-# --- Retarget the fat binary at the Xe2 GPUs for sycl-tla kernels -----------
-# sycl-tla (flash-attn2 etc.) needs Xe2 matrix features (DPAS, 2D block IO,
-# bfloat16) that xe-lpg and ats-m150 cannot compile, so REPLACE the device list
-# with the Xe2 discrete GPUs. Still one .so with one AOT image per device.
-set(SYCL_AOT_DEVICES "pvc,bmg,cri")
+# --- Tri-target fat binary: pvc + bmg (fp16/bf16) + cri (fp16/bf16 + MXFP) ----
+# One .so, three AOT images. fp16/bf16 TUs compile multi-target below; the
+# block-scaled MXFP TUs are gated behind __SYCL_TARGET_INTEL_GPU_CRI__ and must
+# compile spir64_gen-only (that macro + -fsycl-targets=spir64_gen is set per
+# MXFP kernel component in build.toml, since MXFP BDPAS AOT works ONLY on cri --
+# ocloc aborts it for pvc/bmg). The generic spir64_gen image is AOT-lowered to
+# cri via `-device cri`; the pvc/bmg alias images self-target and carry no MXFP.
+set(SYCL_AOT_DEVICES "cri")
 
-# AOT-only: a spir64 JIT fallback is unneeded (kernels build only for these GPUs)
-# and unsupported alongside a per-target -spirv-ext list.
-set(SYCL_OFFLOAD_TARGETS "spir64_gen")
+# Compile fp16/bf16 for all three; MXFP components override to spir64_gen only.
+set(SYCL_OFFLOAD_TARGETS "intel_gpu_pvc,intel_gpu_bmg_g21,spir64_gen")
 
 # sycl-tla needs extra extensions (split-barrier always; block-IO and
 # matrix-multiply on newer DPCPP). Since the translator replaces the whole

From 482d6279ee5542e39fdb002e556a16672e0b2095 Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Wed, 29 Jul 2026 01:47:41 -0700
Subject: [PATCH 6/8] fix

Signed-off-by: jiqing-feng <jiqing.feng@intel.com>
---
 .../src/pyproject/templates/tvm_ffi/preamble.cmake | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake b/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
index 1b30249da..0e688b3f8 100644
--- a/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
+++ b/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
@@ -155,13 +155,15 @@ elseif(GPU_LANG STREQUAL "SYCL")
     set(sycl_link_flags
       "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS};-Xsycl-target-backend=spir64_gen;-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'")
 
-    # SYCL_SPIRV_EXT must be a COMPLETE list: the translator treats the last
-    # -spirv-ext as a replacement, so a short list drops defaults (e.g. bfloat16).
-    # Bare -Xspirv-translator (no triple) targets the single spir64_gen image;
-    # SHELL: keeps the option and value together.
+    # SYCL_SPIRV_EXT must be a COMPLETE list (translator replaces, not merges).
+    # A custom -spirv-ext only reaches an image whose triple matches the exact
+    # fsycl-targets alias, so emit one -Xspirv-translator=<alias> per target.
     if(SYCL_SPIRV_EXT)
-      string(APPEND sycl_link_flags
-        ";SHELL:-Xspirv-translator -spirv-ext=${SYCL_SPIRV_EXT}")
+      string(REPLACE "," ";" _sycl_ext_targets "${SYCL_OFFLOAD_TARGETS}")
+      foreach(_tgt IN LISTS _sycl_ext_targets)
+        string(APPEND sycl_link_flags
+          ";SHELL:-Xspirv-translator=${_tgt} -spirv-ext=${SYCL_SPIRV_EXT}")
+      endforeach()
     endif()
   endmacro()
 

From 3d4e9419c48bb6674a64c69e8e3da78d47300ab2 Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Mon, 3 Aug 2026 19:15:44 -0700
Subject: [PATCH 7/8] kernel-builder: add spir64 JIT fallback and bump sycl-tla
 to v0.9.2

The tri-target AOT-only build dropped the spir64 image, so sycl-tla
kernels only loaded on pvc/bmg/cri. Re-add spir64 alongside the AOT
targets to restore JIT coverage for other Intel GPUs. MXFP is absent
from the JIT image, which is harmless since its dispatch is gated on
device IP version >= 35 at runtime.

Also align the sycl-tla revision across both paths. The non-nix
FetchContent fallback pinned v0.9.1, which carries cri only as a
placeholder constant and none of the Xe35 block-scaled kernels.
nix-builder already pinned d54352d; v0.9.2 is exactly that commit, so
both now use the tag and the source hash is unchanged.
---
 .../pyproject/templates/xpu/dep-sycl-tla.cmake | 18 +++++++-----------
 nix-builder/pkgs/xpu-packages/sycl-tla.nix     |  3 +--
 2 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
index bd21c73de..efe620ece 100644
--- a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
+++ b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
@@ -5,7 +5,8 @@ find_package(SyclTla)
 if(DPCPP_VERSION STREQUAL "2025.3")
   set(SYCL_TLA_REVISION "v0.8" CACHE STRING "sycl-tla revision to use")
 elseif(DPCPP_VERSION STREQUAL "2026.0")
-  set(SYCL_TLA_REVISION "v0.9.1" CACHE STRING "sycl-tla revision to use")
+  # v0.9.2 == the rev pinned in nix-builder; v0.9.1 has no cri kernel support.
+  set(SYCL_TLA_REVISION "v0.9.2" CACHE STRING "sycl-tla revision to use")
 else()
   message(FATAL_ERROR "Unknown DPCPP_VERSION: ${DPCPP_VERSION}")
 endif()
@@ -68,17 +69,12 @@ if(SYCL_TLA_REVISION MATCHES "^v3\\.9")
   add_compile_definitions(OLD_API=1)
 endif()
 
-# --- Tri-target fat binary: pvc + bmg (fp16/bf16) + cri (fp16/bf16 + MXFP) ----
-# One .so, three AOT images. fp16/bf16 TUs compile multi-target below; the
-# block-scaled MXFP TUs are gated behind __SYCL_TARGET_INTEL_GPU_CRI__ and must
-# compile spir64_gen-only (that macro + -fsycl-targets=spir64_gen is set per
-# MXFP kernel component in build.toml, since MXFP BDPAS AOT works ONLY on cri --
-# ocloc aborts it for pvc/bmg). The generic spir64_gen image is AOT-lowered to
-# cri via `-device cri`; the pvc/bmg alias images self-target and carry no MXFP.
+# --- Fat binary: pvc + bmg + cri AOT images, plus a spir64 JIT fallback ------
+# `-device cri` lowers the generic spir64_gen image; pvc/bmg alias images
+# self-target. MXFP is cri-only (ocloc aborts it elsewhere), so build.toml
+# builds those TUs spir64_gen-only and dispatch gates them on IP version >= 35.
 set(SYCL_AOT_DEVICES "cri")
-
-# Compile fp16/bf16 for all three; MXFP components override to spir64_gen only.
-set(SYCL_OFFLOAD_TARGETS "intel_gpu_pvc,intel_gpu_bmg_g21,spir64_gen")
+set(SYCL_OFFLOAD_TARGETS "intel_gpu_pvc,intel_gpu_bmg_g21,spir64_gen,spir64")
 
 # sycl-tla needs extra extensions (split-barrier always; block-IO and
 # matrix-multiply on newer DPCPP). Since the translator replaces the whole
diff --git a/nix-builder/pkgs/xpu-packages/sycl-tla.nix b/nix-builder/pkgs/xpu-packages/sycl-tla.nix
index 0f86843f9..abfe74162 100644
--- a/nix-builder/pkgs/xpu-packages/sycl-tla.nix
+++ b/nix-builder/pkgs/xpu-packages/sycl-tla.nix
@@ -19,8 +19,7 @@ let
       hash = "sha256-xXAxIDBesjDDOIa6/YsGznyW+5+NpaO1L96lBuqRzrk=";
     };
     "2026.0" = {
-      version = "0.9.1-main-d54352d";
-      rev = "d54352dffe8daab532abd88fc6ab0e9c9fbc6d62";
+      version = "0.9.2";
       hash = "sha256-Hn51Ah1wEscOnrt9O/aXBW7IC6Mcl4gUWynAmDeAOlM=";
     };
   };

From f95802053ec819c44564f56f05b1e175639990cf Mon Sep 17 00:00:00 2001
From: jiqing-feng <jiqing.feng@intel.com>
Date: Tue, 4 Aug 2026 22:26:07 -0700
Subject: [PATCH 8/8] kernel-builder: fix per-target SYCL AOT backend options,
 gate cri on 2026.0

The previous cri work passed -Xsycl-target-backend=spir64_gen only, which
reaches the generic image alone, so the intel_gpu_pvc and intel_gpu_bmg_g21
alias images silently lost their backend options. Emitting one option per
target then hit CMake's link-option deduplication, which dropped every
repeated -options and made ocloc parse the next flag as its value, so use
SHELL: to keep each pair intact.

cri has no intel_gpu_* alias and is only reachable as a -device of the
generic image. Only a kernel with an Xe35-only TU needs alias targets to
keep MXFP code away from pvc/bmg; every other kernel can lower one generic
image to all three devices, halving the device compilations per TU.

Also gate the AOT device list on DPCPP 2026.0, since cri needs sycl-tla
v0.9.2 and ocloc 26.22, and fail the build when the SPIR-V extension probe
fails instead of silently dropping the compiler's default extensions.
---
 .../cutlass-gemm/torch-ext/registration.h     | 12 ----------
 kernel-builder/src/pyproject/deps.rs          | 21 ++++++++++++++++-
 .../pyproject/templates/torch/preamble.cmake  | 17 ++++++++++++--
 .../templates/tvm_ffi/preamble.cmake          | 19 ++++++++++++++-
 .../templates/xpu/dep-sycl-tla.cmake          | 23 +++++++++++--------
 kernels-data/src/config/mod.rs                |  7 ++++++
 6 files changed, 73 insertions(+), 26 deletions(-)

diff --git a/examples/kernels/cutlass-gemm/torch-ext/registration.h b/examples/kernels/cutlass-gemm/torch-ext/registration.h
index 096da4beb..4d0ce1c57 100644
--- a/examples/kernels/cutlass-gemm/torch-ext/registration.h
+++ b/examples/kernels/cutlass-gemm/torch-ext/registration.h
@@ -1,6 +1,3 @@
-// Registration macros from vLLM:
-// https://github.com/vllm-project/vllm/blob/main/csrc/core/registration.h
-
 #pragma once
 
 #include <Python.h>
@@ -15,20 +12,11 @@
 // could be a macro instead of a literal token.
 #define TORCH_LIBRARY_EXPAND(NAME, MODULE) TORCH_LIBRARY(NAME, MODULE)
 
-// A version of the STABLE_TORCH_LIBRARY macro that expands the NAME, i.e. so NAME
-// could be a macro instead of a literal token.
-#define STABLE_TORCH_LIBRARY_EXPAND(NAME, MODULE) STABLE_TORCH_LIBRARY(NAME, MODULE)
-
 // A version of the TORCH_LIBRARY_IMPL macro that expands the NAME, i.e. so NAME
 // could be a macro instead of a literal token.
 #define TORCH_LIBRARY_IMPL_EXPAND(NAME, DEVICE, MODULE) \
   TORCH_LIBRARY_IMPL(NAME, DEVICE, MODULE)
 
-// A version of the STABLE_TORCH_LIBRARY_IMPL macro that expands the NAME, i.e. so NAME
-// could be a macro instead of a literal token.
-#define STABLE_TORCH_LIBRARY_IMPL_EXPAND(NAME, DEVICE, MODULE) \
-  STABLE_TORCH_LIBRARY_IMPL(NAME, DEVICE, MODULE)
-
 // REGISTER_EXTENSION allows the shared library to be loaded and initialized
 // via python's import statement.
 #define REGISTER_EXTENSION(NAME)                                               \
diff --git a/kernel-builder/src/pyproject/deps.rs b/kernel-builder/src/pyproject/deps.rs
index 065651b4c..4707f695c 100644
--- a/kernel-builder/src/pyproject/deps.rs
+++ b/kernel-builder/src/pyproject/deps.rs
@@ -93,9 +93,28 @@ pub fn render_deps(env: &Environment, build: &Build, write: &mut impl Write) ->
                     .wrap_err("Cannot render CUTLASS dependency template")?;
             }
             Dependency::SyclTla => {
+                // An Xe35-only TU puts MXFP code that ocloc rejects elsewhere into the
+                // generic image, so that image can only lower to cri and pvc/bmg need
+                // alias targets. Otherwise one image serves all three, halving the
+                // device compilations per TU.
+                let cri_isolated_image = build.kernels.values().any(|kernel| {
+                    kernel.sycl_flags().is_some_and(|flags| {
+                        flags
+                            .iter()
+                            .any(|flag| flag.contains("__SYCL_TARGET_INTEL_GPU_CRI__"))
+                    })
+                });
+                let (sycl_aot_devices, sycl_offload_targets) = if cri_isolated_image {
+                    ("cri", "intel_gpu_pvc,intel_gpu_bmg_g21,spir64_gen,spir64")
+                } else {
+                    ("pvc,bmg-g21,cri", "spir64_gen,spir64")
+                };
                 env.get_template("xpu/dep-sycl-tla.cmake")
                     .wrap_err("Cannot get SYCL TLA dependency template")?
-                    .render_captured_to(context! {}, &mut *write)
+                    .render_captured_to(
+                        context! { sycl_aot_devices, sycl_offload_targets },
+                        &mut *write,
+                    )
                     .wrap_err("Cannot render SYCL TLA dependency template")?;
             }
             Dependency::MetalCpp => {
diff --git a/kernel-builder/src/pyproject/templates/torch/preamble.cmake b/kernel-builder/src/pyproject/templates/torch/preamble.cmake
index 8c2fb0758..11786211d 100644
--- a/kernel-builder/src/pyproject/templates/torch/preamble.cmake
+++ b/kernel-builder/src/pyproject/templates/torch/preamble.cmake
@@ -220,9 +220,22 @@ elseif(GPU_LANG STREQUAL "SYCL")
     set(sycl_flags
       "-fPIC;-fsycl;-fhonor-nans;-fhonor-infinities;-fno-associative-math;-fno-approx-func;-fno-sycl-instrument-device-code;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS}")
 
-    # spir64_gen bakes the per-device AOT images; -device selects the GPUs.
     set(sycl_link_flags
-      "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS};-Xsycl-target-backend=spir64_gen;-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'")
+      "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS}")
+
+    # Backend options reach one target each: spir64_gen takes -device, the
+    # intel_gpu_* aliases imply theirs. SHELL: stops CMake from deduplicating
+    # the identical -options and silently dropping all but the first target.
+    string(REPLACE "," ";" _sycl_aot_targets "${SYCL_OFFLOAD_TARGETS}")
+    foreach(_tgt IN LISTS _sycl_aot_targets)
+      if(_tgt STREQUAL "spir64_gen")
+        string(APPEND sycl_link_flags
+          ";SHELL:-Xsycl-target-backend=spir64_gen \"-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'\"")
+      elseif(_tgt MATCHES "^intel_gpu_")
+        string(APPEND sycl_link_flags
+          ";SHELL:-Xsycl-target-backend=${_tgt} \"-options '${SYCL_AOT_BACKEND_OPTIONS}'\"")
+      endif()
+    endforeach()
 
     # SYCL_SPIRV_EXT must be a COMPLETE list (translator replaces, not merges).
     # A custom -spirv-ext only reaches an image whose triple matches the exact
diff --git a/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake b/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
index 0e688b3f8..18639e411 100644
--- a/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
+++ b/kernel-builder/src/pyproject/templates/tvm_ffi/preamble.cmake
@@ -153,7 +153,24 @@ elseif(GPU_LANG STREQUAL "SYCL")
 
     # spir64_gen bakes the per-device AOT images; -device selects the GPUs.
     set(sycl_link_flags
-      "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS};-Xsycl-target-backend=spir64_gen;-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'")
+      "-Wl,-z,noexecstack;-fsycl;--offload-compress;-fsycl-targets=${SYCL_OFFLOAD_TARGETS}")
+
+    # Backend options reach exactly one target each, so emit them per target:
+    # spir64_gen takes -device (it bakes the generic AOT image), while every
+    # intel_gpu_* alias already implies its device.
+    # Backend options reach one target each: spir64_gen takes -device, the
+    # intel_gpu_* aliases imply theirs. SHELL: stops CMake from deduplicating
+    # the identical -options and silently dropping all but the first target.
+    string(REPLACE "," ";" _sycl_aot_targets "${SYCL_OFFLOAD_TARGETS}")
+    foreach(_tgt IN LISTS _sycl_aot_targets)
+      if(_tgt STREQUAL "spir64_gen")
+        string(APPEND sycl_link_flags
+          ";SHELL:-Xsycl-target-backend=spir64_gen \"-device ${SYCL_AOT_DEVICES} -options '${SYCL_AOT_BACKEND_OPTIONS}'\"")
+      elseif(_tgt MATCHES "^intel_gpu_")
+        string(APPEND sycl_link_flags
+          ";SHELL:-Xsycl-target-backend=${_tgt} \"-options '${SYCL_AOT_BACKEND_OPTIONS}'\"")
+      endif()
+    endforeach()
 
     # SYCL_SPIRV_EXT must be a COMPLETE list (translator replaces, not merges).
     # A custom -spirv-ext only reaches an image whose triple matches the exact
diff --git a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
index efe620ece..4dc8ff9e7 100644
--- a/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
+++ b/kernel-builder/src/pyproject/templates/xpu/dep-sycl-tla.cmake
@@ -69,12 +69,14 @@ if(SYCL_TLA_REVISION MATCHES "^v3\\.9")
   add_compile_definitions(OLD_API=1)
 endif()
 
-# --- Fat binary: pvc + bmg + cri AOT images, plus a spir64 JIT fallback ------
-# `-device cri` lowers the generic spir64_gen image; pvc/bmg alias images
-# self-target. MXFP is cri-only (ocloc aborts it elsewhere), so build.toml
-# builds those TUs spir64_gen-only and dispatch gates them on IP version >= 35.
-set(SYCL_AOT_DEVICES "cri")
-set(SYCL_OFFLOAD_TARGETS "intel_gpu_pvc,intel_gpu_bmg_g21,spir64_gen,spir64")
+# Fat binary: AOT images for SYCL_AOT_DEVICES plus a spir64 JIT fallback.
+# cri needs sycl-tla v0.9.2 and ocloc >= 26.22, so only 2026.0 gets AOT images.
+if(DPCPP_VERSION STREQUAL "2026.0")
+  set(SYCL_AOT_DEVICES "{{ sycl_aot_devices }}")
+  set(SYCL_OFFLOAD_TARGETS "{{ sycl_offload_targets }}")
+else()
+  set(SYCL_OFFLOAD_TARGETS "spir64")
+endif()
 
 # sycl-tla needs extra extensions (split-barrier always; block-IO and
 # matrix-multiply on newer DPCPP). Since the translator replaces the whole
@@ -90,17 +92,18 @@ file(WRITE "${_sycl_ext_probe}" "int main() { return 0; }\n")
 # rest of the COMMAND, making icpx read from stdin instead of dumping its flags.
 execute_process(
   COMMAND ${ICPX_COMPILER} -fsycl -fsycl-targets=spir64_gen "-###" "${_sycl_ext_probe}"
+  RESULT_VARIABLE _sycl_ext_probe_rc
   OUTPUT_VARIABLE _sycl_ext_probe_out
   ERROR_VARIABLE _sycl_ext_probe_err)
 string(REGEX MATCH "-spirv-ext=[^\" ]+" _sycl_default_ext "${_sycl_ext_probe_out}${_sycl_ext_probe_err}")
-if(_sycl_default_ext)
+if(_sycl_ext_probe_rc EQUAL 0 AND _sycl_default_ext)
   # Strip the "-spirv-ext=-all," prefix, leaving the "+ext,+ext,..." default set.
   string(REGEX REPLACE "^-spirv-ext=(-all,)?" "" _sycl_default_ext "${_sycl_default_ext}")
   set(SYCL_SPIRV_EXT "${_sycl_default_ext},${_sycl_tla_extra_ext}")
 else()
-  message(WARNING "Could not determine default SPIR-V extensions from ${ICPX_COMPILER}; "
-                  "using sycl-tla extras only, which may disable compiler defaults.")
-  set(SYCL_SPIRV_EXT "${_sycl_tla_extra_ext}")
+  # Silently dropping the compiler defaults would ship a miscompiled kernel.
+  message(FATAL_ERROR "Could not determine default SPIR-V extensions from ${ICPX_COMPILER} "
+                      "(exit ${_sycl_ext_probe_rc}): ${_sycl_ext_probe_err}")
 endif()
 
 xpu_compose_sycl_flags()
diff --git a/kernels-data/src/config/mod.rs b/kernels-data/src/config/mod.rs
index bc7855f71..638ffd08f 100644
--- a/kernels-data/src/config/mod.rs
+++ b/kernels-data/src/config/mod.rs
@@ -339,6 +339,13 @@ impl Kernel {
         }
     }
 
+    pub fn sycl_flags(&self) -> Option<&[String]> {
+        match self {
+            Kernel::Xpu { sycl_flags, .. } => sycl_flags.as_deref(),
+            _ => None,
+        }
+    }
+
     pub fn backend(&self) -> Backend {
         match self {
             Kernel::Cpu { .. } => Backend::Cpu,