- Power domains: UPF allow designers to define different power domains, they can be changed to 1 or 0. Depending on the value it helps to reduce power consumption during idle state.
Structure:
create_power_domain name_power_domain -elements {name_wrapper}
When declaring the top, we don't use the element we use the -include_scope.
Example:
create_power_domain pd_top -include_scope #top must always be included
create_power_domain pd_aon -elements {aon_wrapper}
- Level Shifters: These are utilized to manage voltage differences between various power domains.
set_level_shifter LtoH_sig_to_powerdomain \
-domain pd_gated_aon_powerdomain \
-applies_to inputs \
-rule low_to_high \
-location self
set_level_shifter HtoL_sig_from_powerdomain \
-domain pd_gated_aon_powerdomain \
-applies_to outputs \
-rule high_to_low \
-location self
- Isolation Cells: Speciall logic cells inserted on signals crossing from a power-gated domain to an always-on-domain. Their job is to force signals to a known value, when the source domain is OFF.
If the power is OFF, signals might become UNKNOWN which is dangerous, these can be propagated and break simulation. Isolation cells prevent X-propagation
Also known as clamp cell.
Structure:
set_isolation isol_clamp#_sig_from_powerdomain \
-domain which_domain \
-isolation_power_net what_rails_power_the_clamp_cell \
-isolation_ground_net what_rails_power_the_clamp_cell \
-clamp_value value_to_clamp \
-elements {which_signals}
set_isolation_control isol_clamp1_sig_from_pgd \
-domain which_domain \
-isolation_signal which_signal_constrols_it \
-isolation_sense polarity \
-location parent
Example:
set_isolation isol_clamp1_sig_from_pgd \
-domain pd_gated \
-isolation_power_net VCCL \
-isolation_ground_net GND \
-clamp_value 1 \
-elements {pgd_wrapper/sig2}
set_isolation_control isol_clamp1_sig_from_pgd \
-domain pd_gated \
-isolation_signal aon_wrapper/pmu/isol_pgd_en \
-isolation_sense low \ #isolation enabled when isol_pgd_en==0
-location parent #cell is placed in the parent (always-on) domain
We need both set_isolation_control and set_isolation. set_isolation defines what to isolate and how to clamp and set_isolation_control defines when it happens.
- Retention Strategy When the power domain is switched to OFF, the value of the flop is SAVED and later restored when power comes back ON. Preventing state loss.
Example:
set_retention pgd_retain \
-domain pd_gated \
-retention_power_net VCCL \
-retention_ground_net GND \
-elements {pgd_wrapper/regA}
- ** Supply ports and supply nets ** These ones define how power is physically delivered.
Supply port (external interface) These are top-level power pins, power enters the chip from outside.
Example:
create_supply_port VCCH -direction in -domain pd_top
create_supply_port GND -direction in -domain pd_top
Supply net (internal distribution)
create_supply_net VCCL -domain pd_top
create_supply_net VCCH -domain pd_top
create_supply_net GND -domain pd_top
These are internal rails that distribute power inside the chip.
You can use -reuse for shared rails.
Example using -reuse:
create_supply_net VCCL -domain pd_aon -reuse
create_supply_net GND -domain pd_aon -reuse
- ** Power State Table ** It tells the voltage in a given stage, and whether the power domain is on or off.
Example:
add_port_state VDDH \
-state {HighVoltage 1.1}
add_port_state VDDL \
-state {LowVoltage 0.9}
add_port_state sw_aon_pgd_wrapper/sw_VCCH_gated \
-state {HighVoltage 1.1} \
-state {aonpgd_off off}
add_port_state sw_pgd_wrapper/sw_VCCL_gated \
-state {LowVoltage 0.9} \
-state {pgd_off off}
create_pst pwr_state_table \
-supplies {VCCH VCCL VDDH_gated VDDL_gated}
add_pst_state PRE_BOOT \
-pst pwr_state_table \
-state { HighVoltage LowVoltage aonpgd_off pgd_off}
add_pst_state AONPGD_ON \
-pst pwr_state_table \
-state { HighVoltage LowVoltage HighVoltage pgd_off}
add_pst_state PGD_ON \
-pst pwr_state_table \
-state { HighVoltage LowVoltage aonpgd_off LowVoltage}
add_pst_state ALL_ON \
-pst pwr_state_table \
-state { HighVoltage LowVoltage HighVoltage LowVoltage}