Fix race condition and message loss in Cortex-M AC6 ports (#516)

fdesbiens · fdesbiens · commit 6c45adf75961 · 2026-04-14T17:49:09.000-04:00
- Added compiler memory barriers to BASEPRI management functions in tx_port.h.
- Added architectural barriers (DSB/ISB) to scheduler return paths in tx_port.h and tx_thread_system_return.S to prevent fall-through before context switch.
- These changes address spurious thread resumption and lost messages, especially when TX_NOT_INTERRUPTABLE is enabled.

Assisted-by: Gemini (Gemini 2.0 Flash)
diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,20 +541,20 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
+#endif
+
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
 }
-#endif
 
 __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture)
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +580,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -589,7 +592,6 @@ unsigned int interrupt_save;
         __restore_interrupt(interrupt_save);
     }
 }
-
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);
diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -541,7 +543,7 @@ UINT posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
 #else
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +556,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -579,6 +582,7 @@ UINT interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (_tx_ipsr_get() == 0)
     {
         interrupt_save = __get_interrupt_posture();
diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable
diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,20 +541,20 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
+#endif
+
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
 }
-#endif
 
 __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture)
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -574,6 +576,22 @@ unsigned int int_posture;
 
 __attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void)
 {
+unsigned int interrupt_save;
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
+    if (__get_ipsr_value() == 0)
+    {
+        interrupt_save = __get_interrupt_posture();
+#ifdef TX_PORT_USE_BASEPRI
+        __set_basepri_value(0);
+#else
+        __enable_interrupts();
+#endif
+        __restore_interrupt(interrupt_save);
+    }
+}
 unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S
@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     #0xF                                    // Ensure memory access is complete
+    ISB     #0xF                                    // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable

Original file line number	Diff line number	Diff line change
`@@ -9,6 +9,8 @@`
`9`	`9`	`* SPDX-License-Identifier: MIT`
`10`	`10`	`**************************************************************************/`
`11`	`11`
	`12`	`+// Some portions generated by Gemini (Gemini 2.0 Flash).`
	`13`	`+`
`12`	`14`
`13`	`15`	`/**************************************************************************/`
`14`	`16`	`/**************************************************************************/`
`@@ -539,20 +541,20 @@ unsigned int posture;`
`539`	`541`	`#ifdef TX_PORT_USE_BASEPRI`
`540`	`542`	`__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)`
`541`	`543`	`{`
`542`		`- __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));`
	`544`	`+ __asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");`
`543`	`545`	`}`
`544`		`-#else`
	`546`	`+#endif`
	`547`	`+`
`545`	`548`	`__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)`
`546`	`549`	`{`
`547`	`550`	`__asm__ volatile ("CPSIE i": : : "memory");`
`548`	`551`	`}`
`549`		`-#endif`
`550`	`552`
`551`	`553`	`__attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture)`
`552`	`554`	`{`
`553`	`555`	`#ifdef TX_PORT_USE_BASEPRI`
`554`	`556`	`__set_basepri_value(int_posture);`
`555`		`- //__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");`
	`557`	`+ __asm__ volatile ("" : : : "memory");`
`556`	`558`	`#else`
`557`	`559`	`__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");`
`558`	`560`	`#endif`
`@@ -578,6 +580,7 @@ unsigned int interrupt_save;`
`578`	`580`
`579`	`581`	`/* Set PendSV to invoke ThreadX scheduler. */`
`580`	`582`	`((volatile ULONG ) 0xE000ED04) = ((ULONG) 0x10000000);`
	`583`	`+ __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");`
`581`	`584`	`if (__get_ipsr_value() == 0)`
`582`	`585`	`{`
`583`	`586`	`interrupt_save = __get_interrupt_posture();`
`@@ -589,7 +592,6 @@ unsigned int interrupt_save;`
`589`	`592`	`__restore_interrupt(interrupt_save);`
`590`	`593`	`}`
`591`	`594`	`}`
`592`		`-`
`593`	`595`	`#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;`
`594`	`596`	`#define TX_DISABLE interrupt_save = __disable_interrupts();`
`595`	`597`	`#define TX_RESTORE __restore_interrupt(interrupt_save);`