Fix race condition and message loss in all remaining Cortex-M IAR ports (#516)

- Added compiler memory barriers to BASEPRI management functions in tx_port.h (M3, M4, M7, M55, M85).
- Added architectural barriers (DSB/ISB) to scheduler return paths in tx_port.h and tx_thread_system_return.s (all architectures) to prevent fall-through before context switch.
- Added Gemini attribution and updated headers to follow project mandates.
- These changes address spurious thread resumption and lost messages, especially when TX_NOT_INTERRUPTABLE is enabled.

Assisted-by: Gemini (Gemini 2.0 Flash)

Author: fdesbiens

ports/cortex_m0/iar/inc/tx_port.h

@@ -313,6 +313,7 @@ __istate_t interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_IPSR() == 0)
     {
         interrupt_save = __get_interrupt_state();

ports/cortex_m0/iar/src/tx_thread_system_return.s

@@ -1,12 +1,15 @@
-;/***************************************************************************
+;***************************************************************************
 ; * Copyright (c) 2024 Microsoft Corporation
+; * Copyright (c) 2026-present Eclipse ThreadX contributors
 ; *
 ; * This program and the accompanying materials are made available under the
 ; * terms of the MIT License which is available at
 ; * https://opensource.org/licenses/MIT.
 ; *
 ; * SPDX-License-Identifier: MIT
 ; **************************************************************************/
+
+; Some portions generated by Gemini (Gemini 2.0 Flash).
 ;
 ;
 ;/**************************************************************************/
@@ -68,6 +71,8 @@ _tx_thread_system_return:
     LDR     r0, =0x10000000                         ; Load PENDSVSET bit
     LDR     r1, =0xE000ED04                         ; Load NVIC base
     STR     r0, [r1]                                ; Set PENDSVBIT in ICSR
+    DSB     SY                                      ; Ensure memory access is complete
+    ISB     SY                                      ; Flush pipeline
     MRS     r0, IPSR                                ; Pickup IPSR
     CMP     r0, #0                                  ; Is it a thread returning?
     BNE     _isr_context                            ; If ISR, skip interrupt enable

ports/cortex_m23/iar/inc/tx_port.h

@@ -399,6 +399,7 @@ __istate_t interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_IPSR() == 0)
     {
         interrupt_save = __get_interrupt_state();

ports/cortex_m23/iar/src/tx_thread_system_return.s

@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -65,6 +68,8 @@ _tx_thread_system_return:
     LDR     r0, =0x10000000                         // Load PENDSVSET bit
     LDR     r1, =0xE000ED04                         // Load ICSR address
     STR     r0, [r1]                                // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable

ports/cortex_m3/iar/inc/tx_port.h

@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,20 +541,20 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
+#endif
+
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
 }
-#endif
 
 __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture)
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +580,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -589,7 +592,6 @@ unsigned int interrupt_save;
         __restore_interrupt(interrupt_save);
     }
 }
-
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);

ports/cortex_m3/iar/src/tx_thread_system_return.s

@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable

ports/cortex_m4/iar/inc/tx_port.h

@@ -9,6 +9,8 @@
  * SPDX-License-Identifier: MIT
  **************************************************************************/
 
+// Some portions generated by Gemini (Gemini 2.0 Flash).
+
 
 /**************************************************************************/
 /**************************************************************************/
@@ -539,20 +541,20 @@ unsigned int posture;
 #ifdef TX_PORT_USE_BASEPRI
 __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
 {
-    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value));
+    __asm__ volatile ("MSR  BASEPRI,%0 ": : "r" (basepri_value) : "memory");
 }
-#else
+#endif
+
 __attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
 {
     __asm__ volatile ("CPSIE  i": : : "memory");
 }
-#endif
 
 __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int int_posture)
 {
 #ifdef TX_PORT_USE_BASEPRI
     __set_basepri_value(int_posture);
-    //__asm__ volatile ("MSR  BASEPRI,%0": : "r" (int_posture): "memory");
+    __asm__ volatile ("" : : : "memory");
 #else
     __asm__ volatile ("MSR  PRIMASK,%0": : "r" (int_posture): "memory");
 #endif
@@ -578,6 +580,7 @@ unsigned int interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (__get_ipsr_value() == 0)
     {
         interrupt_save = __get_interrupt_posture();
@@ -589,7 +592,6 @@ unsigned int interrupt_save;
         __restore_interrupt(interrupt_save);
     }
 }
-
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 #define TX_DISABLE                              interrupt_save =  __disable_interrupts();
 #define TX_RESTORE                              __restore_interrupt(interrupt_save);

ports/cortex_m4/iar/src/tx_thread_system_return.s

@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable

ports/cortex_m55/iar/inc/tx_port.h

@@ -579,6 +579,7 @@ UINT interrupt_save;
 
     /* Set PendSV to invoke ThreadX scheduler.  */
     *((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    __asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
     if (_tx_ipsr_get() == 0)
     {
         interrupt_save = __get_interrupt_posture();

ports/cortex_m55/iar/src/tx_thread_system_return.s

@@ -1,16 +1,19 @@
-/***************************************************************************
- * Copyright (c) 2024 Microsoft Corporation
- * Copyright (c) 2026-present Eclipse ThreadX contributors
- *
- * This program and the accompanying materials are made available under the
- * terms of the MIT License which is available at
- * https://opensource.org/licenses/MIT.
- *
- * SPDX-License-Identifier: MIT
- **************************************************************************/
+;***************************************************************************
+;* Copyright (c) 2024 Microsoft Corporation
+;* Copyright (c) 2026-present Eclipse ThreadX contributors
+;*
+;* This program and the accompanying materials are made available under the
+;* terms of the MIT License which is available at
+;* https://opensource.org/licenses/MIT.
+;*
+;* SPDX-License-Identifier: MIT
+;**************************************************************************
 
+; Some portions generated by Gemini (Gemini 2.0 Flash).
+
+
+;**************************************************************************
 
-/**************************************************************************/
 /**************************************************************************/
 /**                                                                       */
 /** ThreadX Component                                                     */
@@ -69,6 +72,8 @@ _tx_thread_system_return:
     MOV     r0, #0x10000000                         // Load PENDSVSET bit
     MOV     r1, #0xE000E000                         // Load NVIC base
     STR     r0, [r1, #0xD04]                        // Set PENDSVBIT in ICSR
+    DSB     SY                                      // Ensure memory access is complete
+    ISB     SY                                      // Flush pipeline
     MRS     r0, IPSR                                // Pickup IPSR
     CMP     r0, #0                                  // Is it a thread returning?
     BNE     _isr_context                            // If ISR, skip interrupt enable