@@ -95,28 +95,21 @@ impl PReg {
9595 /// Create a new PReg. The `hw_enc` range is 6 bits.
9696 #[ inline( always) ]
9797 pub const fn new ( hw_enc : usize , class : RegClass ) -> Self {
98- // We don't have const panics yet (rust-lang/rust#85194) so we
99- // need to use a little indexing trick here. We unfortunately
100- // can't use the `static-assertions` crate because we need
101- // this to work both for const `hw_enc` and for runtime
102- // values.
103- const HW_ENC_MUST_BE_IN_BOUNDS : & [ bool ; PReg :: MAX + 1 ] = & [ true ; PReg :: MAX + 1 ] ;
104- let _ = HW_ENC_MUST_BE_IN_BOUNDS [ hw_enc] ;
105-
98+ debug_assert ! ( hw_enc <= PReg :: MAX ) ;
10699 PReg {
107100 bits : ( ( class as u8 ) << Self :: MAX_BITS ) | ( hw_enc as u8 ) ,
108101 }
109102 }
110103
111104 /// The physical register number, as encoded by the ISA for the particular register class.
112105 #[ inline( always) ]
113- pub fn hw_enc ( self ) -> usize {
106+ pub const fn hw_enc ( self ) -> usize {
114107 self . bits as usize & Self :: MAX
115108 }
116109
117110 /// The register class.
118111 #[ inline( always) ]
119- pub fn class ( self ) -> RegClass {
112+ pub const fn class ( self ) -> RegClass {
120113 if self . bits & ( 1 << Self :: MAX_BITS ) == 0 {
121114 RegClass :: Int
122115 } else {
@@ -143,7 +136,7 @@ impl PReg {
143136 /// Return the "invalid PReg", which can be used to initialize
144137 /// data structures.
145138 #[ inline( always) ]
146- pub fn invalid ( ) -> Self {
139+ pub const fn invalid ( ) -> Self {
147140 PReg :: new ( Self :: MAX , RegClass :: Int )
148141 }
149142}
@@ -264,11 +257,7 @@ impl VReg {
264257
265258 #[ inline( always) ]
266259 pub const fn new ( virt_reg : usize , class : RegClass ) -> Self {
267- // See comment in `PReg::new()`: we are emulating a const
268- // assert here until const panics are stable.
269- const VIRT_REG_MUST_BE_IN_BOUNDS : & [ bool ; VReg :: MAX + 1 ] = & [ true ; VReg :: MAX + 1 ] ;
270- let _ = VIRT_REG_MUST_BE_IN_BOUNDS [ virt_reg] ;
271-
260+ debug_assert ! ( virt_reg <= VReg :: MAX ) ;
272261 VReg {
273262 bits : ( ( virt_reg as u32 ) << 1 ) | ( class as u8 as u32 ) ,
274263 }
@@ -281,7 +270,7 @@ impl VReg {
281270 }
282271
283272 #[ inline( always) ]
284- pub fn class ( self ) -> RegClass {
273+ pub const fn class ( self ) -> RegClass {
285274 match self . bits & 1 {
286275 0 => RegClass :: Int ,
287276 1 => RegClass :: Float ,
@@ -290,7 +279,7 @@ impl VReg {
290279 }
291280
292281 #[ inline( always) ]
293- pub fn invalid ( ) -> Self {
282+ pub const fn invalid ( ) -> Self {
294283 VReg :: new ( Self :: MAX , RegClass :: Int )
295284 }
296285}
0 commit comments