diff --git a/example/src/main.ts b/example/src/main.ts
index 50e7b88..4d90e7a 100644
--- a/example/src/main.ts
+++ b/example/src/main.ts
@@ -9,7 +9,10 @@ import { tasks } from './tasks';
 /** Metrics tooltip lines shared by every task: `[token, description]` pairs. */
 const METRICS_TIP: readonly (readonly [token: string, description: string])[] = [
   ['FPS', 'live processing rate: video frames processed per second (camera-paced)'],
-  ['MS', 'per-frame inference time to GPU completion; 1000 / MS is the FPS ceiling'],
+  [
+    'MS',
+    'frame processing time including crop/upload, model, rendering and GPU completion notification',
+  ],
 ];
 
 const app = document.getElementById('app') as HTMLElement;
diff --git a/example/src/tasks/depth-estimation/loop.ts b/example/src/tasks/depth-estimation/loop.ts
index 266d48b..05e1923 100644
--- a/example/src/tasks/depth-estimation/loop.ts
+++ b/example/src/tasks/depth-estimation/loop.ts
@@ -31,7 +31,7 @@ function onNextVideoFrame(video: HTMLVideoElement, callback: (now: number) => vo
  *
  * @param video The playing camera video to source frames from.
  * @param canvas The canvas element to render the grayscale depth output to.
- * @param onMetrics Optional callback invoked with smoothed FPS and inference time in ms.
+ * @param onMetrics Optional callback invoked with smoothed FPS and frame processing time in ms.
  * @param precision Selected floating-point precision ('float32' or 'float16').
  * @returns A stop function that halts the frame loop and cleans up resources.
  */
@@ -88,8 +88,8 @@ export async function startFrameLoop(
   const vidTexture = device.createTexture({ size, format: 'rgba8unorm', usage: vidUsage });
   const resTexture = device.createTexture({ size, format: 'rgba8unorm', usage: resUsage });
 
-  // Frame-completion fence: a 16-byte copy whose mapAsync resolves exactly
-  // when the frame's GPU work has landed.
+  // Frame-completion fence: mapping this copy waits for the frame's GPU work.
+  // Promise delivery also includes browser scheduling latency.
   const fenceSrc = device.createBuffer({ size: 16, usage: GPUBufferUsage.COPY_SRC });
   const fenceDst = device.createBuffer({
     size: 16,
@@ -167,8 +167,8 @@ export async function startFrameLoop(
     encoder.copyBufferToBuffer(fenceSrc, 0, fenceDst, 0, 16);
     device.queue.submit([encoder.finish()]);
 
-    // Inference time runs to the fence: mapAsync resolves exactly when the
-    // copy lands, unlike onSubmittedWorkDone which can lag to a frame boundary.
+    // Frame time includes crop/upload, GPU work and completion notification.
+    // The fence wait alone is not a measurement of shader execution time.
     void fenceDst.mapAsync(GPUMapMode.READ).then(
       () => {
         if (!running) return;
diff --git a/example/src/tasks/yolo26-detection/loop.ts b/example/src/tasks/yolo26-detection/loop.ts
index db9d840..0a50878 100644
--- a/example/src/tasks/yolo26-detection/loop.ts
+++ b/example/src/tasks/yolo26-detection/loop.ts
@@ -31,7 +31,7 @@ function onNextVideoFrame(video: HTMLVideoElement, callback: (now: number) => vo
  *
  * @param video The playing camera video to source frames from.
  * @param canvas The canvas element to render the graded video output to.
- * @param onMetrics Optional callback invoked with smoothed FPS and inference time in ms.
+ * @param onMetrics Optional callback invoked with smoothed FPS and frame processing time in ms.
  * @param precision Selected floating-point precision ('float32' or 'float16').
  * @returns A stop function that halts the frame loop and cleans up resources.
  */
@@ -88,8 +88,8 @@ export async function startFrameLoop(
   const vidTexture = device.createTexture({ size, format: 'rgba8unorm', usage: vidUsage });
   const resTexture = device.createTexture({ size, format: 'rgba8unorm', usage: resUsage });
 
-  // Frame-completion fence: a 16-byte copy whose mapAsync resolves exactly
-  // when the frame's GPU work has landed.
+  // Frame-completion fence: mapping this copy waits for the frame's GPU work.
+  // Promise delivery also includes browser scheduling latency.
   const fenceSrc = device.createBuffer({ size: 16, usage: GPUBufferUsage.COPY_SRC });
   const fenceDst = device.createBuffer({
     size: 16,
@@ -171,8 +171,8 @@ export async function startFrameLoop(
     encoder.copyBufferToBuffer(fenceSrc, 0, fenceDst, 0, 16);
     device.queue.submit([encoder.finish()]);
 
-    // Inference time runs to the fence: mapAsync resolves exactly when the
-    // copy lands, unlike onSubmittedWorkDone which can lag to a frame boundary.
+    // Frame time includes crop/upload, GPU work and completion notification.
+    // The fence wait alone is not a measurement of shader execution time.
     void fenceDst.mapAsync(GPUMapMode.READ).then(
       () => {
         if (!running) return;
diff --git a/package.json b/package.json
index 17943e9..d55e610 100644
--- a/package.json
+++ b/package.json
@@ -9,6 +9,12 @@
     "example": "vite example",
     "build:example": "vite build example",
     "benchmark:web": "vite utils/benchmark",
+    "benchmark:live": "node utils/benchmark/profile-live.mjs",
+    "benchmark:stages": "node utils/benchmark/profile-live.mjs --controlled",
+    "benchmark:specialized": "node utils/benchmark/profile-live.mjs --specialized",
+    "benchmark:runntime": "node utils/benchmark/profile-live.mjs --runntime",
+    "benchmark:hf": "node utils/benchmark/profile-live.mjs --hf",
+    "benchmark:narrow": "node utils/benchmark/profile-live.mjs --narrow",
     "format": "prettier --write .",
     "lint": "eslint .",
     "lint:fix": "eslint . --fix",
diff --git a/src/shaders/conv-with-clamp/conv-with-clamp-tile32-f16.wgsl.ts b/src/shaders/conv-with-clamp/conv-with-clamp-tile32-f16.wgsl.ts
index 40e184c..e6449bf 100644
--- a/src/shaders/conv-with-clamp/conv-with-clamp-tile32-f16.wgsl.ts
+++ b/src/shaders/conv-with-clamp/conv-with-clamp-tile32-f16.wgsl.ts
@@ -41,6 +41,18 @@ struct Params {
 }
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.Kh, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.Kw, kernel_w, kernel_w != 0u);
+}
+
 var<workgroup> a_sub: array<array<vec4<f16>, 4>, 32>;
 var<workgroup> b_sub: array<array<vec4<f16>, 16>, 16>;
 
@@ -54,9 +66,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.N * params.H_out * params.W_out;
-  let K = params.IC * params.Kh * params.Kw;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.Kh * params.Kw;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.H_out * params.W_out;
 
   let in_hw = params.H_in * params.W_in;
@@ -108,6 +120,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.H_in) &&
+            col_iw_base0[col] + 2 * dW < i32(params.W_in)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.H_in) && ix >= 0 && ix < i32(params.W_in)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k4_start = t << 2u;
@@ -123,18 +162,17 @@ fn main(
     if (bk0 < K) {
       let ic0 = bk0 / khw;
       let rem0 = bk0 % khw;
-      let kh0 = i32(rem0 / params.Kw) * dH;
-      let kw0 = i32(rem0 % params.Kw) * dW;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
 
       var b_row0 = vec4<f16>(0.0h);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih0 = col_ih_base0[kk] + kh0;
-          let iw0 = col_iw_base0[kk] + kw0;
-          if (ih0 >= 0 && ih0 < i32(params.H_in) && iw0 >= 0 && iw0 < i32(params.W_in)) {
-            let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
-            b_row0[kk] = t_in[in_idx0];
-          }
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < i32(params.H_in) && iw0 >= 0 && iw0 < i32(params.W_in))) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_row0[kk] = t_in[in_idx0];
         }
       }
       b_sub[b_r0][b_c4_0] = b_row0;
@@ -146,18 +184,17 @@ fn main(
     if (bk1 < K) {
       let ic1 = bk1 / khw;
       let rem1 = bk1 % khw;
-      let kh1 = i32(rem1 / params.Kw) * dH;
-      let kw1 = i32(rem1 % params.Kw) * dW;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
 
       var b_row1 = vec4<f16>(0.0h);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih1 = col_ih_base0[kk] + kh1;
-          let iw1 = col_iw_base0[kk] + kw1;
-          if (ih1 >= 0 && ih1 < i32(params.H_in) && iw1 >= 0 && iw1 < i32(params.W_in)) {
-            let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
-            b_row1[kk] = t_in[in_idx1];
-          }
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < i32(params.H_in) && iw1 >= 0 && iw1 < i32(params.W_in))) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_row1[kk] = t_in[in_idx1];
         }
       }
       b_sub[b_r1][b_c4_1] = b_row1;
@@ -210,12 +247,10 @@ fn main(
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
         let n = out_c_base + kk;
         if (n < N) {
-          let b_val = n / ohw;
-          let sp = n % ohw;
-          let oh = sp / params.W_out;
-          let ow = sp % params.W_out;
+          // Reuse the batch decoded for input gathering instead of dividing again.
+          let out_base = col_b0[kk] * (M - 1u) * ohw + n;
           let val = clamp(acc_v[kk], min_v, max_v);
-          t_out[((b_val * params.OC + m) * params.H_out + oh) * params.W_out + ow] = val;
+          t_out[m * ohw + out_base] = val;
         }
       }
     }
diff --git a/src/shaders/conv-with-clamp/conv-with-clamp-tile32.wgsl.ts b/src/shaders/conv-with-clamp/conv-with-clamp-tile32.wgsl.ts
index 5283f4e..a4c3c16 100644
--- a/src/shaders/conv-with-clamp/conv-with-clamp-tile32.wgsl.ts
+++ b/src/shaders/conv-with-clamp/conv-with-clamp-tile32.wgsl.ts
@@ -39,6 +39,18 @@ struct Params {
 }
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.Kh, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.Kw, kernel_w, kernel_w != 0u);
+}
+
 // a_sub: 32 output channels x 16 K elements (4 vec4s) = 128 vec4s (2 KB)
 var<workgroup> a_sub: array<array<vec4<f32>, 4>, 32>;
 // b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (4 KB)
@@ -54,9 +66,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.N * params.H_out * params.W_out;
-  let K = params.IC * params.Kh * params.Kw;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.Kh * params.Kw;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.H_out * params.W_out;
 
   let in_hw = params.H_in * params.W_in;
@@ -108,6 +120,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.H_in) &&
+            col_iw_base0[col] + 2 * dW < i32(params.W_in)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.H_in) && ix >= 0 && ix < i32(params.W_in)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k4_start = t << 2u;
@@ -124,18 +163,17 @@ fn main(
     if (bk0 < K) {
       let ic0 = bk0 / khw;
       let rem0 = bk0 % khw;
-      let kh0 = i32(rem0 / params.Kw) * dH;
-      let kw0 = i32(rem0 % params.Kw) * dW;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
 
       var b_row0 = vec4<f32>(0.0);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih0 = col_ih_base0[kk] + kh0;
-          let iw0 = col_iw_base0[kk] + kw0;
-          if (ih0 >= 0 && ih0 < i32(params.H_in) && iw0 >= 0 && iw0 < i32(params.W_in)) {
-            let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
-            b_row0[kk] = t_in[in_idx0];
-          }
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < i32(params.H_in) && iw0 >= 0 && iw0 < i32(params.W_in))) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_row0[kk] = t_in[in_idx0];
         }
       }
       b_sub[b_r0][b_c4_0] = b_row0;
@@ -148,18 +186,17 @@ fn main(
     if (bk1 < K) {
       let ic1 = bk1 / khw;
       let rem1 = bk1 % khw;
-      let kh1 = i32(rem1 / params.Kw) * dH;
-      let kw1 = i32(rem1 % params.Kw) * dW;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
 
       var b_row1 = vec4<f32>(0.0);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih1 = col_ih_base0[kk] + kh1;
-          let iw1 = col_iw_base0[kk] + kw1;
-          if (ih1 >= 0 && ih1 < i32(params.H_in) && iw1 >= 0 && iw1 < i32(params.W_in)) {
-            let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
-            b_row1[kk] = t_in[in_idx1];
-          }
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < i32(params.H_in) && iw1 >= 0 && iw1 < i32(params.W_in))) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_row1[kk] = t_in[in_idx1];
         }
       }
       b_sub[b_r1][b_c4_1] = b_row1;
@@ -212,12 +249,10 @@ fn main(
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
         let n = out_c_base + kk;
         if (n < N) {
-          let b_val = n / ohw;
-          let sp = n % ohw;
-          let oh = sp / params.W_out;
-          let ow = sp % params.W_out;
+          // Reuse the batch decoded for input gathering instead of dividing again.
+          let out_base = col_b0[kk] * (M - 1u) * ohw + n;
           let val = clamp(acc_v[kk], min_v, max_v);
-          t_out[((b_val * params.OC + m) * params.H_out + oh) * params.W_out + ow] = val;
+          t_out[m * ohw + out_base] = val;
         }
       }
     }
diff --git a/src/shaders/conv-with-clamp/conv-with-clamp-tile64-f16.wgsl.ts b/src/shaders/conv-with-clamp/conv-with-clamp-tile64-f16.wgsl.ts
index a95957d..0def0a2 100644
--- a/src/shaders/conv-with-clamp/conv-with-clamp-tile64-f16.wgsl.ts
+++ b/src/shaders/conv-with-clamp/conv-with-clamp-tile64-f16.wgsl.ts
@@ -41,6 +41,18 @@ struct Params {
 }
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.Kh, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.Kw, kernel_w, kernel_w != 0u);
+}
+
 // a_sub: 64 output channels x 16 K elements (4 vec4s) = 256 vec4s (2 KB)
 var<workgroup> a_sub: array<array<vec4<f16>, 4>, 64>;
 // b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (2 KB)
@@ -56,9 +68,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.N * params.H_out * params.W_out;
-  let K = params.IC * params.Kh * params.Kw;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.Kh * params.Kw;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.H_out * params.W_out;
 
   let iH = i32(params.H_in);
@@ -111,6 +123,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid[col]) {
+        if (col_ih_base[col] >= 0 && col_iw_base[col] >= 0 &&
+            col_ih_base[col] + 2 * dH < i32(params.H_in) &&
+            col_iw_base[col] + 2 * dW < i32(params.W_in)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.H_in) && ix >= 0 && ix < i32(params.W_in)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k_start = t << 4u;
@@ -129,17 +168,16 @@ fn main(
     if (kk_idx < K) {
       let k_ic = kk_idx / khw;
       let rem = kk_idx % khw;
-      let kh = i32(rem / params.Kw) * dH;
-      let kw = i32(rem % params.Kw) * dW;
+      let kh = i32(rem / kernel_width()) * dH;
+      let kw = i32(rem % kernel_width()) * dW;
 
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid[kk]) {
-          let ih = col_ih_base[kk] + kh;
-          let iw = col_iw_base[kk] + kw;
-          if (ih >= 0 && ih < iH && iw >= 0 && iw < iW) {
-            let ch_idx = col_b[kk] * params.IC + k_ic;
-            b_row[kk] = t_x[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
-          }
+        let ih = col_ih_base[kk] + kh;
+        let iw = col_iw_base[kk] + kw;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid[kk] && ih >= 0 && ih < iH && iw >= 0 && iw < iW)) {
+          let ch_idx = col_b[kk] * params.IC + k_ic;
+          b_row[kk] = t_x[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
         }
       }
     }
@@ -191,12 +229,10 @@ fn main(
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
         let n = out_c_base + kk;
         if (n < N) {
-          let b_val = n / ohw;
-          let sp = n % ohw;
-          let oh = sp / params.W_out;
-          let ow = sp % params.W_out;
+          // Reuse the batch decoded for input gathering instead of dividing again.
+          let out_base = col_b[kk] * (M - 1u) * ohw + n;
           let val = clamp(acc_v[kk], min_v, max_v);
-          t_out[((b_val * params.OC + m) * params.H_out + oh) * params.W_out + ow] = val;
+          t_out[m * ohw + out_base] = val;
         }
       }
     }
diff --git a/src/shaders/conv-with-clamp/conv-with-clamp-tile64.wgsl.ts b/src/shaders/conv-with-clamp/conv-with-clamp-tile64.wgsl.ts
index c16abea..1d2262d 100644
--- a/src/shaders/conv-with-clamp/conv-with-clamp-tile64.wgsl.ts
+++ b/src/shaders/conv-with-clamp/conv-with-clamp-tile64.wgsl.ts
@@ -39,6 +39,18 @@ struct Params {
 }
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.Kh, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.Kw, kernel_w, kernel_w != 0u);
+}
+
 // a_sub: 64 output channels x 16 K elements (4 vec4s) = 256 vec4s (4 KB)
 var<workgroup> a_sub: array<array<vec4<f32>, 4>, 64>;
 // b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (4 KB)
@@ -54,9 +66,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.N * params.H_out * params.W_out;
-  let K = params.IC * params.Kh * params.Kw;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.Kh * params.Kw;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.H_out * params.W_out;
 
   let iH = i32(params.H_in);
@@ -109,6 +121,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid[col]) {
+        if (col_ih_base[col] >= 0 && col_iw_base[col] >= 0 &&
+            col_ih_base[col] + 2 * dH < i32(params.H_in) &&
+            col_iw_base[col] + 2 * dW < i32(params.W_in)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.H_in) && ix >= 0 && ix < i32(params.W_in)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k_start = t << 4u;
@@ -127,17 +166,16 @@ fn main(
     if (kk_idx < K) {
       let k_ic = kk_idx / khw;
       let rem = kk_idx % khw;
-      let kh = i32(rem / params.Kw) * dH;
-      let kw = i32(rem % params.Kw) * dW;
+      let kh = i32(rem / kernel_width()) * dH;
+      let kw = i32(rem % kernel_width()) * dW;
 
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid[kk]) {
-          let ih = col_ih_base[kk] + kh;
-          let iw = col_iw_base[kk] + kw;
-          if (ih >= 0 && ih < iH && iw >= 0 && iw < iW) {
-            let ch_idx = col_b[kk] * params.IC + k_ic;
-            b_row[kk] = t_x[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
-          }
+        let ih = col_ih_base[kk] + kh;
+        let iw = col_iw_base[kk] + kw;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid[kk] && ih >= 0 && ih < iH && iw >= 0 && iw < iW)) {
+          let ch_idx = col_b[kk] * params.IC + k_ic;
+          b_row[kk] = t_x[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
         }
       }
     }
@@ -189,12 +227,10 @@ fn main(
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
         let n = out_c_base + kk;
         if (n < N) {
-          let b_val = n / ohw;
-          let sp = n % ohw;
-          let oh = sp / params.W_out;
-          let ow = sp % params.W_out;
+          // Reuse the batch decoded for input gathering instead of dividing again.
+          let out_base = col_b[kk] * (M - 1u) * ohw + n;
           let val = clamp(acc_v[kk], min_v, max_v);
-          t_out[((b_val * params.OC + m) * params.H_out + oh) * params.W_out + ow] = val;
+          t_out[m * ohw + out_base] = val;
         }
       }
     }
diff --git a/src/shaders/conv-with-clamp/index.ts b/src/shaders/conv-with-clamp/index.ts
index c449ec2..c0bf5a9 100644
--- a/src/shaders/conv-with-clamp/index.ts
+++ b/src/shaders/conv-with-clamp/index.ts
@@ -278,12 +278,14 @@ function recordIn(ctx: WgpuExecutionContext, args: ConvWithClampArgs): void {
     // 32x64 register-tiled GEMM for general dense convolution with clamp
     workgroupCountX = Math.ceil((n * expectedHout * expectedWout) / 64);
     workgroupCountY = Math.ceil(oc / 32);
-    constants = {};
+    // eslint-disable-next-line camelcase, @typescript-eslint/naming-convention
+    constants = { kernel_h: kh, kernel_w: kw };
   } else if (isDenseTile64) {
     // 64x64 register-tiled GEMM for general dense convolution with clamp
     workgroupCountX = Math.ceil((n * expectedHout * expectedWout) / 64);
     workgroupCountY = Math.ceil(oc / 64);
-    constants = {};
+    // eslint-disable-next-line camelcase, @typescript-eslint/naming-convention
+    constants = { kernel_h: kh, kernel_w: kw };
   } else {
     // GEMM kernel: fixed 8x8 workgroup covering a 32x32 output tile;
     // grid over (N = batch*H_out*W_out cols, M = OC rows)
diff --git a/src/shaders/convolution/conv2d-direct-small-f16.wgsl.ts b/src/shaders/convolution/conv2d-direct-small-f16.wgsl.ts
new file mode 100644
index 0000000..1b50d56
--- /dev/null
+++ b/src/shaders/convolution/conv2d-direct-small-f16.wgsl.ts
@@ -0,0 +1,119 @@
+/**
+ * Direct small-channel 3x3 convolution: stage four filters once and reuse them across
+ * adjacent spatial outputs. Small reductions avoid implicit-GEMM input staging.
+ * Inspired by ruNNtime's small-channel direct convolution, adapted to NCHW.
+ * https://github.com/software-mansion/runntime (MIT)
+ * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)
+ * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)
+ */
+export const SHADER_CONV2D_DIRECT_SMALL_F16 = /* wgsl */ `
+enable f16;
+
+struct Params {
+  B: u32, IC: u32, IH: u32, IW: u32,
+  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,
+  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,
+  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,
+}
+@group(0) @binding(0) var<storage, read_write> out: array<f16>;
+@group(0) @binding(1) var<storage, read> input: array<f16>;
+@group(0) @binding(2) var<storage, read> weight: array<f16>;
+@group(0) @binding(3) var<storage, read> bias: array<f16>;
+@group(0) @binding(4) var<uniform> params: Params;
+
+const pixels: u32 = 2u;
+override input_h: u32 = 1u;
+override input_w: u32 = 1u;
+override output_h: u32 = 1u;
+override output_w: u32 = 1u;
+
+override channels: u32 = 3u;
+override filter_count: u32 = 27u;
+override stride_h: u32 = 2u;
+override stride_w: u32 = 2u;
+override pad_h: u32 = 1u;
+override pad_w: u32 = 1u;
+override dilation_h: u32 = 1u;
+override dilation_w: u32 = 1u;
+
+var<workgroup> filters: array<vec4<f16>, filter_count>;
+
+@compute @workgroup_size(64)
+fn main(@builtin(workgroup_id) wg: vec3<u32>,
+        @builtin(local_invocation_index) tid: u32) {
+  let channel = wg.y * 4u;
+  for (var k = tid; k < filter_count; k += 64u) {
+    var v = vec4<f16>(0.0h);
+    for (var c = 0u; c < 4u; c++) {
+      if (channel + c < params.OC) { v[c] = weight[(channel + c) * filter_count + k]; }
+    }
+    filters[k] = v;
+  }
+  workgroupBarrier();
+  let spatial = output_h * output_w;
+  let n0 = wg.x * (64u * pixels) + tid * pixels;
+  let source_base = wg.z * channels * input_h * input_w;
+  var acc: array<vec4<f16>, pixels>;
+  var row: array<i32, pixels>;
+  var col: array<i32, pixels>;
+  for (var p = 0u; p < pixels; p++) {
+    row[p] = i32((n0 + p) / output_w) * i32(stride_h) - i32(pad_h);
+    col[p] = i32((n0 + p) % output_w) * i32(stride_w) - i32(pad_w);
+    acc[p] = vec4<f16>(0.0h);
+  }
+  // Two neighboring stride-one stencils share two of their three columns.
+  // Keep that four-value row in registers; other geometries use guarded gathers.
+  if (channels != 3u && stride_w == 1u && (output_w & 1u) == 0u) {
+    for (var ic = 0u; ic < channels; ic++) {
+      for (var ky = 0u; ky < 3u; ky++) {
+        let iy = row[0] + i32(ky);
+        var line = vec4<f16>(0.0h);
+        for (var j = 0u; j < 4u; j++) {
+          let ix = col[0] + i32(j);
+          if (n0 < spatial && iy >= 0 && iy < i32(input_h) && ix >= 0 && ix < i32(input_w)) {
+            line[j] = input[source_base + ic * input_h * input_w + u32(iy) * input_w + u32(ix)];
+          }
+        }
+        for (var kx = 0u; kx < 3u; kx++) {
+          let w = filters[ic * 9u + ky * 3u + kx];
+          acc[0] = acc[0] + vec4<f16>(line[kx]) * w;
+          acc[1] = acc[1] + vec4<f16>(line[kx + 1u]) * w;
+        }
+      }
+    }
+  } else {
+    for (var ic = 0u; ic < channels; ic++) {
+      for (var ky = 0u; ky < 3u; ky++) {
+        for (var kx = 0u; kx < 3u; kx++) {
+          let w = filters[ic * 9u + ky * 3u + kx];
+          for (var p = 0u; p < pixels; p++) {
+            let iy = row[p] + i32(ky * dilation_h);
+            let ix = col[p] + i32(kx * dilation_w);
+            var x = 0.0h;
+            if (n0 + p < spatial && iy >= 0 && ix >= 0 && iy < i32(input_h) && ix < i32(input_w)) {
+              x = input[source_base + ic * input_h * input_w + u32(iy) * input_w + u32(ix)];
+            }
+            acc[p] = acc[p] + vec4<f16>(x) * w;
+          }
+        }
+      }
+    }
+  }
+  var bias_value = vec4<f16>(0.0h);
+  if (params.has_bias != 0u) {
+    for (var c = 0u; c < 4u; c++) {
+      if (channel + c < params.OC) { bias_value[c] = bias[channel + c]; }
+    }
+  }
+  for (var p = 0u; p < pixels; p++) {
+    if (n0 + p < spatial) {
+      let value = acc[p] + bias_value;
+      for (var c = 0u; c < 4u; c++) {
+        if (channel + c < params.OC) {
+          out[(wg.z * params.OC + channel + c) * spatial + n0 + p] = value[c];
+        }
+      }
+    }
+  }
+}
+`;
diff --git a/src/shaders/convolution/conv2d-direct-small.wgsl.ts b/src/shaders/convolution/conv2d-direct-small.wgsl.ts
new file mode 100644
index 0000000..0a7fcfd
--- /dev/null
+++ b/src/shaders/convolution/conv2d-direct-small.wgsl.ts
@@ -0,0 +1,117 @@
+/**
+ * Direct small-channel 3x3 convolution: stage four filters once and reuse them across
+ * adjacent spatial outputs. Small reductions avoid implicit-GEMM input staging.
+ * Inspired by ruNNtime's small-channel direct convolution, adapted to NCHW.
+ * https://github.com/software-mansion/runntime (MIT)
+ * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)
+ * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)
+ */
+export const SHADER_CONV2D_DIRECT_SMALL = /* wgsl */ `
+struct Params {
+  B: u32, IC: u32, IH: u32, IW: u32,
+  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,
+  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,
+  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,
+}
+@group(0) @binding(0) var<storage, read_write> out: array<f32>;
+@group(0) @binding(1) var<storage, read> input: array<f32>;
+@group(0) @binding(2) var<storage, read> weight: array<f32>;
+@group(0) @binding(3) var<storage, read> bias: array<f32>;
+@group(0) @binding(4) var<uniform> params: Params;
+
+const pixels: u32 = 2u;
+override input_h: u32 = 1u;
+override input_w: u32 = 1u;
+override output_h: u32 = 1u;
+override output_w: u32 = 1u;
+
+override channels: u32 = 3u;
+override filter_count: u32 = 27u;
+override stride_h: u32 = 2u;
+override stride_w: u32 = 2u;
+override pad_h: u32 = 1u;
+override pad_w: u32 = 1u;
+override dilation_h: u32 = 1u;
+override dilation_w: u32 = 1u;
+
+var<workgroup> filters: array<vec4<f32>, filter_count>;
+
+@compute @workgroup_size(64)
+fn main(@builtin(workgroup_id) wg: vec3<u32>,
+        @builtin(local_invocation_index) tid: u32) {
+  let channel = wg.y * 4u;
+  for (var k = tid; k < filter_count; k += 64u) {
+    var v = vec4<f32>(0.0);
+    for (var c = 0u; c < 4u; c++) {
+      if (channel + c < params.OC) { v[c] = weight[(channel + c) * filter_count + k]; }
+    }
+    filters[k] = v;
+  }
+  workgroupBarrier();
+  let spatial = output_h * output_w;
+  let n0 = wg.x * (64u * pixels) + tid * pixels;
+  let source_base = wg.z * channels * input_h * input_w;
+  var acc: array<vec4<f32>, pixels>;
+  var row: array<i32, pixels>;
+  var col: array<i32, pixels>;
+  for (var p = 0u; p < pixels; p++) {
+    row[p] = i32((n0 + p) / output_w) * i32(stride_h) - i32(pad_h);
+    col[p] = i32((n0 + p) % output_w) * i32(stride_w) - i32(pad_w);
+    acc[p] = vec4<f32>(0.0);
+  }
+  // Two neighboring stride-one stencils share two of their three columns.
+  // Keep that four-value row in registers; other geometries use guarded gathers.
+  if (channels != 3u && stride_w == 1u && (output_w & 1u) == 0u) {
+    for (var ic = 0u; ic < channels; ic++) {
+      for (var ky = 0u; ky < 3u; ky++) {
+        let iy = row[0] + i32(ky);
+        var line = vec4<f32>(0.0);
+        for (var j = 0u; j < 4u; j++) {
+          let ix = col[0] + i32(j);
+          if (n0 < spatial && iy >= 0 && iy < i32(input_h) && ix >= 0 && ix < i32(input_w)) {
+            line[j] = input[source_base + ic * input_h * input_w + u32(iy) * input_w + u32(ix)];
+          }
+        }
+        for (var kx = 0u; kx < 3u; kx++) {
+          let w = filters[ic * 9u + ky * 3u + kx];
+          acc[0] = acc[0] + vec4<f32>(line[kx]) * w;
+          acc[1] = acc[1] + vec4<f32>(line[kx + 1u]) * w;
+        }
+      }
+    }
+  } else {
+    for (var ic = 0u; ic < channels; ic++) {
+      for (var ky = 0u; ky < 3u; ky++) {
+        for (var kx = 0u; kx < 3u; kx++) {
+          let w = filters[ic * 9u + ky * 3u + kx];
+          for (var p = 0u; p < pixels; p++) {
+            let iy = row[p] + i32(ky * dilation_h);
+            let ix = col[p] + i32(kx * dilation_w);
+            var x = 0.0;
+            if (n0 + p < spatial && iy >= 0 && ix >= 0 && iy < i32(input_h) && ix < i32(input_w)) {
+              x = input[source_base + ic * input_h * input_w + u32(iy) * input_w + u32(ix)];
+            }
+            acc[p] = acc[p] + vec4<f32>(x) * w;
+          }
+        }
+      }
+    }
+  }
+  var bias_value = vec4<f32>(0.0);
+  if (params.has_bias != 0u) {
+    for (var c = 0u; c < 4u; c++) {
+      if (channel + c < params.OC) { bias_value[c] = bias[channel + c]; }
+    }
+  }
+  for (var p = 0u; p < pixels; p++) {
+    if (n0 + p < spatial) {
+      let value = acc[p] + bias_value;
+      for (var c = 0u; c < 4u; c++) {
+        if (channel + c < params.OC) {
+          out[(wg.z * params.OC + channel + c) * spatial + n0 + p] = value[c];
+        }
+      }
+    }
+  }
+}
+`;
diff --git a/src/shaders/convolution/conv2d-gemm.wgsl.ts b/src/shaders/convolution/conv2d-gemm.wgsl.ts
index e92699d..1b26ec8 100644
--- a/src/shaders/convolution/conv2d-gemm.wgsl.ts
+++ b/src/shaders/convolution/conv2d-gemm.wgsl.ts
@@ -132,7 +132,7 @@ fn main(
           let ih = col_ih_base[kk] + kh_dH;
           let iw = col_iw_base[kk] + kw_dW;
           if (ih >= 0 && ih < iH && iw >= 0 && iw < iW) {
-            let ch_idx = col_b[kk] + k_ic;
+            let ch_idx = col_b_ic[kk] + k_ic;
             b_row[kk] = input[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
           } else {
             b_row[kk] = 0.0;
diff --git a/src/shaders/convolution/conv2d-tile16-f16.wgsl.ts b/src/shaders/convolution/conv2d-tile16-f16.wgsl.ts
new file mode 100644
index 0000000..6bafef2
--- /dev/null
+++ b/src/shaders/convolution/conv2d-tile16-f16.wgsl.ts
@@ -0,0 +1,288 @@
+/**
+ * WGSL compute shader for 16x64 register-tiled 2D convolution GEMM in FP16 (4x4 per thread across 64 threads).
+ * Targets dense 3x3 layers with 8-16 output channels and large spatial grids.
+ *
+ * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)
+ * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)
+ */
+export const SHADER_CONV2D_TILE16_F16 = /* wgsl */ `
+enable f16;
+
+struct Params {
+  B: u32, IC: u32, IH: u32, IW: u32,
+  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,
+  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,
+  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,
+}
+@group(0) @binding(0) var<storage, read_write> out: array<f16>;
+@group(0) @binding(1) var<storage, read> input: array<f16>;
+@group(0) @binding(2) var<storage, read> weight: array<vec4<f16>>;
+@group(0) @binding(3) var<storage, read> bias: array<f16>;
+@group(0) @binding(4) var<uniform> params: Params;
+
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
+var<workgroup> a_sub: array<array<vec4<f16>, 4>, 16>;
+var<workgroup> b_sub: array<array<vec4<f16>, 16>, 16>;
+
+@compute @workgroup_size(16, 4, 1)
+fn main(
+  @builtin(workgroup_id) wg_id: vec3<u32>,
+  @builtin(local_invocation_id) local_id: vec3<u32>,
+  @builtin(local_invocation_index) tid: u32
+) {
+  let tile_row0 = wg_id.y * 16u;
+  let tile_col0 = wg_id.x * 64u;
+  let M = params.OC;
+  let N = params.B * params.OH * params.OW;
+  let K = params.IC * kernel_height() * kernel_width();
+  let K_vecs = K >> 2u;
+  let khw = kernel_height() * kernel_width();
+  let ohw = params.OH * params.OW;
+
+  let iH = i32(params.IH);
+  let iW = i32(params.IW);
+  let in_hw = params.IH * params.IW;
+  let in_w = params.IW;
+  let sH = i32(params.sH);
+  let sW = i32(params.sW);
+  let pH = i32(params.pH);
+  let pW = i32(params.pW);
+  let dH = i32(params.dH);
+  let dW = i32(params.dW);
+
+  var acc0 = vec4<f16>(0.0h);
+  var acc1 = vec4<f16>(0.0h);
+  var acc2 = vec4<f16>(0.0h);
+  var acc3 = vec4<f16>(0.0h);
+
+  let a_r = tid >> 2u;      // 0..15
+  let a_c = tid & 3u;       // 0..3
+  let a_m = tile_row0 + a_r;
+  let a_valid = a_m < M;
+
+  // Four cooperative input loads per thread cover the same 16x64 K tile.
+  let b_r0 = tid >> 4u;      // 0..3
+  let b_c4_0 = tid & 15u;
+  let b_r1 = b_r0 + 4u;
+  let b_c4_1 = b_c4_0;
+  let b_r2 = b_r0 + 8u;
+  let b_c4_2 = b_c4_0;
+  let b_r3 = b_r0 + 12u;
+  let b_c4_3 = b_c4_0;
+
+  let n_base0 = tile_col0 + (b_c4_0 << 2u);
+
+  var col_b0: array<u32, 4>;
+  var col_ih_base0: array<i32, 4>;
+  var col_iw_base0: array<i32, 4>;
+  var col_valid0: array<bool, 4>;
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let n = n_base0 + kk;
+    if (n < N) {
+      col_valid0[kk] = true;
+      let b_val = n / ohw;
+      let sp = n % ohw;
+      col_b0[kk] = b_val;
+      let oh = sp / params.OW;
+      let ow = sp % params.OW;
+      col_ih_base0[kk] = i32(oh) * sH - pH;
+      col_iw_base0[kk] = i32(ow) * sW - pW;
+    } else {
+      col_valid0[kk] = false;
+      col_b0[kk] = 0u;
+      col_ih_base0[kk] = 0;
+      col_iw_base0[kk] = 0;
+    }
+  }
+
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base0[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
+  let num_tiles = (K + 15u) >> 4u;
+  for (var t = 0u; t < num_tiles; t = t + 1u) {
+    let k4_start = t << 2u;
+    let k_start = t << 4u;
+
+    if (a_valid && (k4_start + a_c) < K_vecs) {
+      a_sub[a_r][a_c] = weight[a_m * K_vecs + k4_start + a_c];
+    } else {
+      a_sub[a_r][a_c] = vec4<f16>(0.0h);
+    }
+
+    let bk0 = k_start + b_r0;
+    if (bk0 < K) {
+      let ic0 = bk0 / khw;
+      let rem0 = bk0 % khw;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
+
+      var b_vec0 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW)) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_vec0[kk] = input[in_idx0];
+        }
+      }
+      b_sub[b_r0][b_c4_0] = b_vec0;
+    } else {
+      b_sub[b_r0][b_c4_0] = vec4<f16>(0.0h);
+    }
+
+    let bk1 = k_start + b_r1;
+    if (bk1 < K) {
+      let ic1 = bk1 / khw;
+      let rem1 = bk1 % khw;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
+
+      var b_vec1 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW)) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_vec1[kk] = input[in_idx1];
+        }
+      }
+      b_sub[b_r1][b_c4_1] = b_vec1;
+    } else {
+      b_sub[b_r1][b_c4_1] = vec4<f16>(0.0h);
+    }
+
+    let bk2 = k_start + b_r2;
+    if (bk2 < K) {
+      let ic2 = bk2 / khw;
+      let rem2 = bk2 % khw;
+      let kh2 = i32(rem2 / kernel_width()) * dH;
+      let kw2 = i32(rem2 % kernel_width()) * dW;
+
+      var b_vec2 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih2 = col_ih_base0[kk] + kh2;
+        let iw2 = col_iw_base0[kk] + kw2;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem2)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih2 >= 0 && ih2 < iH && iw2 >= 0 && iw2 < iW)) {
+          let in_idx2 = (col_b0[kk] * params.IC + ic2) * in_hw + u32(ih2) * in_w + u32(iw2);
+          b_vec2[kk] = input[in_idx2];
+        }
+      }
+      b_sub[b_r2][b_c4_2] = b_vec2;
+    } else {
+      b_sub[b_r2][b_c4_2] = vec4<f16>(0.0h);
+    }
+
+    let bk3 = k_start + b_r3;
+    if (bk3 < K) {
+      let ic3 = bk3 / khw;
+      let rem3 = bk3 % khw;
+      let kh3 = i32(rem3 / kernel_width()) * dH;
+      let kw3 = i32(rem3 % kernel_width()) * dW;
+
+      var b_vec3 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih3 = col_ih_base0[kk] + kh3;
+        let iw3 = col_iw_base0[kk] + kw3;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem3)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih3 >= 0 && ih3 < iH && iw3 >= 0 && iw3 < iW)) {
+          let in_idx3 = (col_b0[kk] * params.IC + ic3) * in_hw + u32(ih3) * in_w + u32(iw3);
+          b_vec3[kk] = input[in_idx3];
+        }
+      }
+      b_sub[b_r3][b_c4_3] = b_vec3;
+    } else {
+      b_sub[b_r3][b_c4_3] = vec4<f16>(0.0h);
+    }
+
+    workgroupBarrier();
+
+    let thread_r = local_id.y << 2u;
+    let thread_c4 = local_id.x;
+
+    for (var k4 = 0u; k4 < 4u; k4 = k4 + 1u) {
+      let b0 = b_sub[k4 * 4u + 0u][thread_c4];
+      let b1 = b_sub[k4 * 4u + 1u][thread_c4];
+      let b2 = b_sub[k4 * 4u + 2u][thread_c4];
+      let b3 = b_sub[k4 * 4u + 3u][thread_c4];
+
+      let a0 = a_sub[thread_r + 0u][k4];
+      let a1 = a_sub[thread_r + 1u][k4];
+      let a2 = a_sub[thread_r + 2u][k4];
+      let a3 = a_sub[thread_r + 3u][k4];
+
+      acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;
+      acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;
+      acc2 = acc2 + b0 * a2.x + b1 * a2.y + b2 * a2.z + b3 * a2.w;
+      acc3 = acc3 + b0 * a3.x + b1 * a3.y + b2 * a3.z + b3 * a3.w;
+    }
+    workgroupBarrier();
+  }
+
+  let thread_r = local_id.y << 2u;
+  let out_r0 = tile_row0 + thread_r;
+  let out_c_base = tile_col0 + (local_id.x << 2u);
+
+  var bias_val = vec4<f16>(0.0h);
+  if (params.has_bias != 0u) {
+    if (out_r0 + 0u < M) { bias_val.x = bias[out_r0 + 0u]; }
+    if (out_r0 + 1u < M) { bias_val.y = bias[out_r0 + 1u]; }
+    if (out_r0 + 2u < M) { bias_val.z = bias[out_r0 + 2u]; }
+    if (out_r0 + 3u < M) { bias_val.w = bias[out_r0 + 3u]; }
+  }
+
+  acc0 = acc0 + vec4<f16>(bias_val.x);
+  acc1 = acc1 + vec4<f16>(bias_val.y);
+  acc2 = acc2 + vec4<f16>(bias_val.z);
+  acc3 = acc3 + vec4<f16>(bias_val.w);
+
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let out_c = out_c_base + kk;
+    if (out_c < N) {
+      // Reuse the batch decoded for input gathering; output is NCHW.
+      let out_base = col_b0[kk] * (M - 1u) * ohw + out_c;
+      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * ohw + out_base] = acc0[kk]; }
+      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * ohw + out_base] = acc1[kk]; }
+      if (out_r0 + 2u < M) { out[(out_r0 + 2u) * ohw + out_base] = acc2[kk]; }
+      if (out_r0 + 3u < M) { out[(out_r0 + 3u) * ohw + out_base] = acc3[kk]; }
+    }
+  }
+}
+`;
diff --git a/src/shaders/convolution/conv2d-tile16.wgsl.ts b/src/shaders/convolution/conv2d-tile16.wgsl.ts
new file mode 100644
index 0000000..bb2834f
--- /dev/null
+++ b/src/shaders/convolution/conv2d-tile16.wgsl.ts
@@ -0,0 +1,295 @@
+/**
+ * WGSL compute shader for 16x64 register-tiled 2D convolution GEMM (4x4 per thread across 64 threads).
+ * Targets dense 3x3 layers with 8-16 output channels and large spatial grids.
+ *
+ * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)
+ * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)
+ */
+export const SHADER_CONV2D_TILE16 = /* wgsl */ `
+struct Params {
+  B: u32, IC: u32, IH: u32, IW: u32,
+  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,
+  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,
+  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,
+}
+@group(0) @binding(0) var<storage, read_write> out: array<f32>;
+@group(0) @binding(1) var<storage, read> input: array<f32>;
+@group(0) @binding(2) var<storage, read> weight: array<vec4<f32>>;
+@group(0) @binding(3) var<storage, read> bias: array<f32>;
+@group(0) @binding(4) var<uniform> params: Params;
+
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
+// a_sub: 32 output channels x 16 K elements (4 vec4s) = 128 vec4s (2 KB)
+var<workgroup> a_sub: array<array<vec4<f32>, 4>, 16>;
+// b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (4 KB)
+var<workgroup> b_sub: array<array<vec4<f32>, 16>, 16>;
+
+@compute @workgroup_size(16, 4, 1)
+fn main(
+  @builtin(workgroup_id) wg_id: vec3<u32>,
+  @builtin(local_invocation_id) local_id: vec3<u32>,
+  @builtin(local_invocation_index) tid: u32
+) {
+  let tile_row0 = wg_id.y * 16u;
+  let tile_col0 = wg_id.x * 64u;
+  let M = params.OC;
+  let N = params.B * params.OH * params.OW;
+  let K = params.IC * kernel_height() * kernel_width();
+  let K_vecs = K >> 2u;
+  let khw = kernel_height() * kernel_width();
+  let ohw = params.OH * params.OW;
+
+  let iH = i32(params.IH);
+  let iW = i32(params.IW);
+  let in_hw = params.IH * params.IW;
+  let in_w = params.IW;
+  let sH = i32(params.sH);
+  let sW = i32(params.sW);
+  let pH = i32(params.pH);
+  let pW = i32(params.pW);
+  let dH = i32(params.dH);
+  let dW = i32(params.dW);
+
+  var acc0 = vec4<f32>(0.0);
+  var acc1 = vec4<f32>(0.0);
+  var acc2 = vec4<f32>(0.0);
+  var acc3 = vec4<f32>(0.0);
+
+  // 64 threads cooperatively load 128 vec4s of A (32 rows x 4 vec4s)
+  let a_r = tid >> 2u;      // 0..15
+  let a_c = tid & 3u;       // 0..3
+  let a_m = tile_row0 + a_r;
+  let a_valid = a_m < M;
+
+  // 64 threads load 256 vec4s of B (16 rows x 16 vec4s) -> 2 passes per thread
+  // Four cooperative input loads per thread cover the same 16x64 K tile.
+  let b_r0 = tid >> 4u;      // 0..3
+  let b_c4_0 = tid & 15u;
+  let b_r1 = b_r0 + 4u;
+  let b_c4_1 = b_c4_0;
+  let b_r2 = b_r0 + 8u;
+  let b_c4_2 = b_c4_0;
+  let b_r3 = b_r0 + 12u;
+  let b_c4_3 = b_c4_0;
+
+  let n_base0 = tile_col0 + (b_c4_0 << 2u);
+
+  var col_b0: array<u32, 4>;
+  var col_ih_base0: array<i32, 4>;
+  var col_iw_base0: array<i32, 4>;
+  var col_valid0: array<bool, 4>;
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let n = n_base0 + kk;
+    if (n < N) {
+      col_valid0[kk] = true;
+      let b_val = n / ohw;
+      let sp = n % ohw;
+      col_b0[kk] = b_val;
+      let oh = sp / params.OW;
+      let ow = sp % params.OW;
+      col_ih_base0[kk] = i32(oh) * sH - pH;
+      col_iw_base0[kk] = i32(ow) * sW - pW;
+    } else {
+      col_valid0[kk] = false;
+      col_b0[kk] = 0u;
+      col_ih_base0[kk] = 0;
+      col_iw_base0[kk] = 0;
+    }
+  }
+
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base0[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
+  let num_tiles = (K + 15u) >> 4u;
+  for (var t = 0u; t < num_tiles; t = t + 1u) {
+    let k4_start = t << 2u;
+    let k_start = t << 4u;
+
+    if (a_valid && (k4_start + a_c) < K_vecs) {
+      a_sub[a_r][a_c] = weight[a_m * K_vecs + k4_start + a_c];
+    } else {
+      a_sub[a_r][a_c] = vec4<f32>(0.0);
+    }
+
+    // Load first B slice (rows 0..7)
+    let bk0 = k_start + b_r0;
+    if (bk0 < K) {
+      let ic0 = bk0 / khw;
+      let rem0 = bk0 % khw;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
+
+      var b_vec0 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW)) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_vec0[kk] = input[in_idx0];
+        }
+      }
+      b_sub[b_r0][b_c4_0] = b_vec0;
+    } else {
+      b_sub[b_r0][b_c4_0] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    let bk1 = k_start + b_r1;
+    if (bk1 < K) {
+      let ic1 = bk1 / khw;
+      let rem1 = bk1 % khw;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
+
+      var b_vec1 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW)) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_vec1[kk] = input[in_idx1];
+        }
+      }
+      b_sub[b_r1][b_c4_1] = b_vec1;
+    } else {
+      b_sub[b_r1][b_c4_1] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    let bk2 = k_start + b_r2;
+    if (bk2 < K) {
+      let ic2 = bk2 / khw;
+      let rem2 = bk2 % khw;
+      let kh2 = i32(rem2 / kernel_width()) * dH;
+      let kw2 = i32(rem2 % kernel_width()) * dW;
+
+      var b_vec2 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih2 = col_ih_base0[kk] + kh2;
+        let iw2 = col_iw_base0[kk] + kw2;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem2)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih2 >= 0 && ih2 < iH && iw2 >= 0 && iw2 < iW)) {
+          let in_idx2 = (col_b0[kk] * params.IC + ic2) * in_hw + u32(ih2) * in_w + u32(iw2);
+          b_vec2[kk] = input[in_idx2];
+        }
+      }
+      b_sub[b_r2][b_c4_2] = b_vec2;
+    } else {
+      b_sub[b_r2][b_c4_2] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    let bk3 = k_start + b_r3;
+    if (bk3 < K) {
+      let ic3 = bk3 / khw;
+      let rem3 = bk3 % khw;
+      let kh3 = i32(rem3 / kernel_width()) * dH;
+      let kw3 = i32(rem3 % kernel_width()) * dW;
+
+      var b_vec3 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih3 = col_ih_base0[kk] + kh3;
+        let iw3 = col_iw_base0[kk] + kw3;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem3)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih3 >= 0 && ih3 < iH && iw3 >= 0 && iw3 < iW)) {
+          let in_idx3 = (col_b0[kk] * params.IC + ic3) * in_hw + u32(ih3) * in_w + u32(iw3);
+          b_vec3[kk] = input[in_idx3];
+        }
+      }
+      b_sub[b_r3][b_c4_3] = b_vec3;
+    } else {
+      b_sub[b_r3][b_c4_3] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    workgroupBarrier();
+
+    let thread_r = local_id.y << 2u; // 0..28 (step 4)
+    let thread_c4 = local_id.x;      // 0..15
+
+    for (var k4 = 0u; k4 < 4u; k4 = k4 + 1u) {
+      let b0 = b_sub[k4 * 4u + 0u][thread_c4];
+      let b1 = b_sub[k4 * 4u + 1u][thread_c4];
+      let b2 = b_sub[k4 * 4u + 2u][thread_c4];
+      let b3 = b_sub[k4 * 4u + 3u][thread_c4];
+
+      let a0 = a_sub[thread_r + 0u][k4];
+      let a1 = a_sub[thread_r + 1u][k4];
+      let a2 = a_sub[thread_r + 2u][k4];
+      let a3 = a_sub[thread_r + 3u][k4];
+
+      acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;
+      acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;
+      acc2 = acc2 + b0 * a2.x + b1 * a2.y + b2 * a2.z + b3 * a2.w;
+      acc3 = acc3 + b0 * a3.x + b1 * a3.y + b2 * a3.z + b3 * a3.w;
+    }
+    workgroupBarrier();
+  }
+
+  let thread_r = local_id.y << 2u;
+  let out_r0 = tile_row0 + thread_r;
+  let out_c_base = tile_col0 + (local_id.x << 2u);
+
+  var bias_val = vec4<f32>(0.0);
+  if (params.has_bias != 0u) {
+    if (out_r0 + 0u < M) { bias_val.x = bias[out_r0 + 0u]; }
+    if (out_r0 + 1u < M) { bias_val.y = bias[out_r0 + 1u]; }
+    if (out_r0 + 2u < M) { bias_val.z = bias[out_r0 + 2u]; }
+    if (out_r0 + 3u < M) { bias_val.w = bias[out_r0 + 3u]; }
+  }
+
+  acc0 = acc0 + vec4<f32>(bias_val.x);
+  acc1 = acc1 + vec4<f32>(bias_val.y);
+  acc2 = acc2 + vec4<f32>(bias_val.z);
+  acc3 = acc3 + vec4<f32>(bias_val.w);
+
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let out_c = out_c_base + kk;
+    if (out_c < N) {
+      // Reuse the batch decoded for input gathering; output is NCHW.
+      let out_base = col_b0[kk] * (M - 1u) * ohw + out_c;
+      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * ohw + out_base] = acc0[kk]; }
+      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * ohw + out_base] = acc1[kk]; }
+      if (out_r0 + 2u < M) { out[(out_r0 + 2u) * ohw + out_base] = acc2[kk]; }
+      if (out_r0 + 3u < M) { out[(out_r0 + 3u) * ohw + out_base] = acc3[kk]; }
+    }
+  }
+}
+`;
diff --git a/src/shaders/convolution/conv2d-tile32-f16.wgsl.ts b/src/shaders/convolution/conv2d-tile32-f16.wgsl.ts
index 33e380a..9dc976a 100644
--- a/src/shaders/convolution/conv2d-tile32-f16.wgsl.ts
+++ b/src/shaders/convolution/conv2d-tile32-f16.wgsl.ts
@@ -20,6 +20,18 @@ struct Params {
 @group(0) @binding(3) var<storage, read> bias: array<f16>;
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
 var<workgroup> a_sub: array<array<vec4<f16>, 4>, 32>;
 var<workgroup> b_sub: array<array<vec4<f16>, 16>, 16>;
 
@@ -33,9 +45,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.B * params.OH * params.OW;
-  let K = params.IC * params.KH * params.KW;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.KH * params.KW;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.OH * params.OW;
 
   let iH = i32(params.IH);
@@ -89,6 +101,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base0[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k4_start = t << 2u;
@@ -104,18 +143,17 @@ fn main(
     if (bk0 < K) {
       let ic0 = bk0 / khw;
       let rem0 = bk0 % khw;
-      let kh0 = i32(rem0 / params.KW) * dH;
-      let kw0 = i32(rem0 % params.KW) * dW;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
 
       var b_vec0 = vec4<f16>(0.0h);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih0 = col_ih_base0[kk] + kh0;
-          let iw0 = col_iw_base0[kk] + kw0;
-          if (ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW) {
-            let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
-            b_vec0[kk] = input[in_idx0];
-          }
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW)) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_vec0[kk] = input[in_idx0];
         }
       }
       b_sub[b_r0][b_c4_0] = b_vec0;
@@ -127,18 +165,17 @@ fn main(
     if (bk1 < K) {
       let ic1 = bk1 / khw;
       let rem1 = bk1 % khw;
-      let kh1 = i32(rem1 / params.KW) * dH;
-      let kw1 = i32(rem1 % params.KW) * dW;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
 
       var b_vec1 = vec4<f16>(0.0h);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih1 = col_ih_base0[kk] + kh1;
-          let iw1 = col_iw_base0[kk] + kw1;
-          if (ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW) {
-            let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
-            b_vec1[kk] = input[in_idx1];
-          }
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW)) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_vec1[kk] = input[in_idx1];
         }
       }
       b_sub[b_r1][b_c4_1] = b_vec1;
@@ -190,10 +227,12 @@ fn main(
   for (var kk = 0u; kk < 4u; kk = kk + 1u) {
     let out_c = out_c_base + kk;
     if (out_c < N) {
-      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * N + out_c] = acc0[kk]; }
-      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * N + out_c] = acc1[kk]; }
-      if (out_r0 + 2u < M) { out[(out_r0 + 2u) * N + out_c] = acc2[kk]; }
-      if (out_r0 + 3u < M) { out[(out_r0 + 3u) * N + out_c] = acc3[kk]; }
+      // Reuse the batch decoded for input gathering; output is NCHW.
+      let out_base = col_b0[kk] * (M - 1u) * ohw + out_c;
+      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * ohw + out_base] = acc0[kk]; }
+      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * ohw + out_base] = acc1[kk]; }
+      if (out_r0 + 2u < M) { out[(out_r0 + 2u) * ohw + out_base] = acc2[kk]; }
+      if (out_r0 + 3u < M) { out[(out_r0 + 3u) * ohw + out_base] = acc3[kk]; }
     }
   }
 }
diff --git a/src/shaders/convolution/conv2d-tile32.wgsl.ts b/src/shaders/convolution/conv2d-tile32.wgsl.ts
index 79bb9da..90e1003 100644
--- a/src/shaders/convolution/conv2d-tile32.wgsl.ts
+++ b/src/shaders/convolution/conv2d-tile32.wgsl.ts
@@ -18,6 +18,18 @@ struct Params {
 @group(0) @binding(3) var<storage, read> bias: array<f32>;
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
 // a_sub: 32 output channels x 16 K elements (4 vec4s) = 128 vec4s (2 KB)
 var<workgroup> a_sub: array<array<vec4<f32>, 4>, 32>;
 // b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (4 KB)
@@ -33,9 +45,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.B * params.OH * params.OW;
-  let K = params.IC * params.KH * params.KW;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.KH * params.KW;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.OH * params.OW;
 
   let iH = i32(params.IH);
@@ -91,6 +103,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base0[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k4_start = t << 2u;
@@ -107,18 +146,17 @@ fn main(
     if (bk0 < K) {
       let ic0 = bk0 / khw;
       let rem0 = bk0 % khw;
-      let kh0 = i32(rem0 / params.KW) * dH;
-      let kw0 = i32(rem0 % params.KW) * dW;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
 
       var b_vec0 = vec4<f32>(0.0);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih0 = col_ih_base0[kk] + kh0;
-          let iw0 = col_iw_base0[kk] + kw0;
-          if (ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW) {
-            let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
-            b_vec0[kk] = input[in_idx0];
-          }
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW)) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_vec0[kk] = input[in_idx0];
         }
       }
       b_sub[b_r0][b_c4_0] = b_vec0;
@@ -131,18 +169,17 @@ fn main(
     if (bk1 < K) {
       let ic1 = bk1 / khw;
       let rem1 = bk1 % khw;
-      let kh1 = i32(rem1 / params.KW) * dH;
-      let kw1 = i32(rem1 % params.KW) * dW;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
 
       var b_vec1 = vec4<f32>(0.0);
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid0[kk]) {
-          let ih1 = col_ih_base0[kk] + kh1;
-          let iw1 = col_iw_base0[kk] + kw1;
-          if (ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW) {
-            let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
-            b_vec1[kk] = input[in_idx1];
-          }
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW)) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_vec1[kk] = input[in_idx1];
         }
       }
       b_sub[b_r1][b_c4_1] = b_vec1;
@@ -194,10 +231,12 @@ fn main(
   for (var kk = 0u; kk < 4u; kk = kk + 1u) {
     let out_c = out_c_base + kk;
     if (out_c < N) {
-      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * N + out_c] = acc0[kk]; }
-      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * N + out_c] = acc1[kk]; }
-      if (out_r0 + 2u < M) { out[(out_r0 + 2u) * N + out_c] = acc2[kk]; }
-      if (out_r0 + 3u < M) { out[(out_r0 + 3u) * N + out_c] = acc3[kk]; }
+      // Reuse the batch decoded for input gathering; output is NCHW.
+      let out_base = col_b0[kk] * (M - 1u) * ohw + out_c;
+      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * ohw + out_base] = acc0[kk]; }
+      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * ohw + out_base] = acc1[kk]; }
+      if (out_r0 + 2u < M) { out[(out_r0 + 2u) * ohw + out_base] = acc2[kk]; }
+      if (out_r0 + 3u < M) { out[(out_r0 + 3u) * ohw + out_base] = acc3[kk]; }
     }
   }
 }
diff --git a/src/shaders/convolution/conv2d-tile64-f16.wgsl.ts b/src/shaders/convolution/conv2d-tile64-f16.wgsl.ts
index 3a3c956..be01167 100644
--- a/src/shaders/convolution/conv2d-tile64-f16.wgsl.ts
+++ b/src/shaders/convolution/conv2d-tile64-f16.wgsl.ts
@@ -20,6 +20,18 @@ struct Params {
 @group(0) @binding(3) var<storage, read> bias: array<f16>;
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
 // a_sub: 64 output channels x 16 K elements (4 vec4s) = 256 vec4s (2 KB)
 var<workgroup> a_sub: array<array<vec4<f16>, 4>, 64>;
 // b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (2 KB)
@@ -35,9 +47,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.B * params.OH * params.OW;
-  let K = params.IC * params.KH * params.KW;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.KH * params.KW;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.OH * params.OW;
 
   let iH = i32(params.IH);
@@ -90,6 +102,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid[col]) {
+        if (col_ih_base[col] >= 0 && col_iw_base[col] >= 0 &&
+            col_ih_base[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k_start = t << 4u;
@@ -108,17 +147,16 @@ fn main(
     if (kk_idx < K) {
       let k_ic = kk_idx / khw;
       let rem = kk_idx % khw;
-      let kh = i32(rem / params.KW) * dH;
-      let kw = i32(rem % params.KW) * dW;
+      let kh = i32(rem / kernel_width()) * dH;
+      let kw = i32(rem % kernel_width()) * dW;
 
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid[kk]) {
-          let ih = col_ih_base[kk] + kh;
-          let iw = col_iw_base[kk] + kw;
-          if (ih >= 0 && ih < iH && iw >= 0 && iw < iW) {
-            let ch_idx = col_b[kk] * params.IC + k_ic;
-            b_row[kk] = input[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
-          }
+        let ih = col_ih_base[kk] + kh;
+        let iw = col_iw_base[kk] + kw;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid[kk] && ih >= 0 && ih < iH && iw >= 0 && iw < iW)) {
+          let ch_idx = col_b[kk] * params.IC + k_ic;
+          b_row[kk] = input[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
         }
       }
     }
@@ -168,11 +206,9 @@ fn main(
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
         let n = out_c_base + kk;
         if (n < N) {
-          let b_val = n / ohw;
-          let sp = n % ohw;
-          let oh = sp / params.OW;
-          let ow = sp % params.OW;
-          out[((b_val * params.OC + m) * params.OH + oh) * params.OW + ow] = acc_v[kk];
+          // Reuse the batch decoded for input gathering instead of dividing again.
+          let out_base = col_b[kk] * (M - 1u) * ohw + n;
+          out[m * ohw + out_base] = acc_v[kk];
         }
       }
     }
diff --git a/src/shaders/convolution/conv2d-tile64.wgsl.ts b/src/shaders/convolution/conv2d-tile64.wgsl.ts
index f8ac116..e12cfb9 100644
--- a/src/shaders/convolution/conv2d-tile64.wgsl.ts
+++ b/src/shaders/convolution/conv2d-tile64.wgsl.ts
@@ -18,6 +18,18 @@ struct Params {
 @group(0) @binding(3) var<storage, read> bias: array<f32>;
 @group(0) @binding(4) var<uniform> params: Params;
 
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
 // a_sub: 64 output channels x 16 K elements (4 vec4s) = 256 vec4s (4 KB)
 var<workgroup> a_sub: array<array<vec4<f32>, 4>, 64>;
 // b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (4 KB)
@@ -33,9 +45,9 @@ fn main(
   let tile_col0 = wg_id.x * 64u;
   let M = params.OC;
   let N = params.B * params.OH * params.OW;
-  let K = params.IC * params.KH * params.KW;
+  let K = params.IC * kernel_height() * kernel_width();
   let K_vecs = K >> 2u;
-  let khw = params.KH * params.KW;
+  let khw = kernel_height() * kernel_width();
   let ohw = params.OH * params.OW;
 
   let iH = i32(params.IH);
@@ -88,6 +100,33 @@ fn main(
     }
   }
 
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid[col]) {
+        if (col_ih_base[col] >= 0 && col_iw_base[col] >= 0 &&
+            col_ih_base[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
   let num_tiles = (K + 15u) >> 4u;
   for (var t = 0u; t < num_tiles; t = t + 1u) {
     let k_start = t << 4u;
@@ -106,17 +145,16 @@ fn main(
     if (kk_idx < K) {
       let k_ic = kk_idx / khw;
       let rem = kk_idx % khw;
-      let kh = i32(rem / params.KW) * dH;
-      let kw = i32(rem % params.KW) * dW;
+      let kh = i32(rem / kernel_width()) * dH;
+      let kw = i32(rem % kernel_width()) * dW;
 
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
-        if (col_valid[kk]) {
-          let ih = col_ih_base[kk] + kh;
-          let iw = col_iw_base[kk] + kw;
-          if (ih >= 0 && ih < iH && iw >= 0 && iw < iW) {
-            let ch_idx = col_b[kk] * params.IC + k_ic;
-            b_row[kk] = input[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
-          }
+        let ih = col_ih_base[kk] + kh;
+        let iw = col_iw_base[kk] + kw;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid[kk] && ih >= 0 && ih < iH && iw >= 0 && iw < iW)) {
+          let ch_idx = col_b[kk] * params.IC + k_ic;
+          b_row[kk] = input[ch_idx * in_hw + u32(ih) * in_w + u32(iw)];
         }
       }
     }
@@ -166,11 +204,9 @@ fn main(
       for (var kk = 0u; kk < 4u; kk = kk + 1u) {
         let n = out_c_base + kk;
         if (n < N) {
-          let b_val = n / ohw;
-          let sp = n % ohw;
-          let oh = sp / params.OW;
-          let ow = sp % params.OW;
-          out[((b_val * params.OC + m) * params.OH + oh) * params.OW + ow] = acc_v[kk];
+          // Reuse the batch decoded for input gathering instead of dividing again.
+          let out_base = col_b[kk] * (M - 1u) * ohw + n;
+          out[m * ohw + out_base] = acc_v[kk];
         }
       }
     }
diff --git a/src/shaders/convolution/conv2d-tile8-f16.wgsl.ts b/src/shaders/convolution/conv2d-tile8-f16.wgsl.ts
new file mode 100644
index 0000000..314e551
--- /dev/null
+++ b/src/shaders/convolution/conv2d-tile8-f16.wgsl.ts
@@ -0,0 +1,278 @@
+/**
+ * WGSL compute shader for 8x64 register-tiled 2D convolution GEMM in FP16 (2x4 per thread across 64 threads).
+ * Targets dense 3x3 layers with at most eight output channels and large spatial grids.
+ *
+ * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)
+ * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)
+ */
+export const SHADER_CONV2D_TILE8_F16 = /* wgsl */ `
+enable f16;
+
+struct Params {
+  B: u32, IC: u32, IH: u32, IW: u32,
+  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,
+  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,
+  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,
+}
+@group(0) @binding(0) var<storage, read_write> out: array<f16>;
+@group(0) @binding(1) var<storage, read> input: array<f16>;
+@group(0) @binding(2) var<storage, read> weight: array<vec4<f16>>;
+@group(0) @binding(3) var<storage, read> bias: array<f16>;
+@group(0) @binding(4) var<uniform> params: Params;
+
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
+var<workgroup> a_sub: array<array<vec4<f16>, 4>, 8>;
+var<workgroup> b_sub: array<array<vec4<f16>, 16>, 16>;
+
+@compute @workgroup_size(16, 4, 1)
+fn main(
+  @builtin(workgroup_id) wg_id: vec3<u32>,
+  @builtin(local_invocation_id) local_id: vec3<u32>,
+  @builtin(local_invocation_index) tid: u32
+) {
+  let tile_row0 = wg_id.y * 8u;
+  let tile_col0 = wg_id.x * 64u;
+  let M = params.OC;
+  let N = params.B * params.OH * params.OW;
+  let K = params.IC * kernel_height() * kernel_width();
+  let K_vecs = K >> 2u;
+  let khw = kernel_height() * kernel_width();
+  let ohw = params.OH * params.OW;
+
+  let iH = i32(params.IH);
+  let iW = i32(params.IW);
+  let in_hw = params.IH * params.IW;
+  let in_w = params.IW;
+  let sH = i32(params.sH);
+  let sW = i32(params.sW);
+  let pH = i32(params.pH);
+  let pW = i32(params.pW);
+  let dH = i32(params.dH);
+  let dW = i32(params.dW);
+
+  var acc0 = vec4<f16>(0.0h);
+  var acc1 = vec4<f16>(0.0h);
+
+  let a_r = tid >> 2u;      // 0..15
+  let a_c = tid & 3u;       // 0..3
+  let a_m = tile_row0 + a_r;
+  let a_valid = a_r < 8u && a_m < M;
+
+  // Four cooperative input loads per thread cover the same 8x64 K tile.
+  let b_r0 = tid >> 4u;      // 0..3
+  let b_c4_0 = tid & 15u;
+  let b_r1 = b_r0 + 4u;
+  let b_c4_1 = b_c4_0;
+  let b_r2 = b_r0 + 8u;
+  let b_c4_2 = b_c4_0;
+  let b_r3 = b_r0 + 12u;
+  let b_c4_3 = b_c4_0;
+
+  let n_base0 = tile_col0 + (b_c4_0 << 2u);
+
+  var col_b0: array<u32, 4>;
+  var col_ih_base0: array<i32, 4>;
+  var col_iw_base0: array<i32, 4>;
+  var col_valid0: array<bool, 4>;
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let n = n_base0 + kk;
+    if (n < N) {
+      col_valid0[kk] = true;
+      let b_val = n / ohw;
+      let sp = n % ohw;
+      col_b0[kk] = b_val;
+      let oh = sp / params.OW;
+      let ow = sp % params.OW;
+      col_ih_base0[kk] = i32(oh) * sH - pH;
+      col_iw_base0[kk] = i32(ow) * sW - pW;
+    } else {
+      col_valid0[kk] = false;
+      col_b0[kk] = 0u;
+      col_ih_base0[kk] = 0;
+      col_iw_base0[kk] = 0;
+    }
+  }
+
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base0[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
+  let num_tiles = (K + 15u) >> 4u;
+  for (var t = 0u; t < num_tiles; t = t + 1u) {
+    let k4_start = t << 2u;
+    let k_start = t << 4u;
+
+    if (a_r < 8u) {
+      if (a_valid && (k4_start + a_c) < K_vecs) {
+        a_sub[a_r][a_c] = weight[a_m * K_vecs + k4_start + a_c];
+      } else {
+        a_sub[a_r][a_c] = vec4<f16>(0.0h);
+      }
+    }
+
+    let bk0 = k_start + b_r0;
+    if (bk0 < K) {
+      let ic0 = bk0 / khw;
+      let rem0 = bk0 % khw;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
+
+      var b_vec0 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW)) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_vec0[kk] = input[in_idx0];
+        }
+      }
+      b_sub[b_r0][b_c4_0] = b_vec0;
+    } else {
+      b_sub[b_r0][b_c4_0] = vec4<f16>(0.0h);
+    }
+
+    let bk1 = k_start + b_r1;
+    if (bk1 < K) {
+      let ic1 = bk1 / khw;
+      let rem1 = bk1 % khw;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
+
+      var b_vec1 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW)) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_vec1[kk] = input[in_idx1];
+        }
+      }
+      b_sub[b_r1][b_c4_1] = b_vec1;
+    } else {
+      b_sub[b_r1][b_c4_1] = vec4<f16>(0.0h);
+    }
+
+    let bk2 = k_start + b_r2;
+    if (bk2 < K) {
+      let ic2 = bk2 / khw;
+      let rem2 = bk2 % khw;
+      let kh2 = i32(rem2 / kernel_width()) * dH;
+      let kw2 = i32(rem2 % kernel_width()) * dW;
+
+      var b_vec2 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih2 = col_ih_base0[kk] + kh2;
+        let iw2 = col_iw_base0[kk] + kw2;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem2)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih2 >= 0 && ih2 < iH && iw2 >= 0 && iw2 < iW)) {
+          let in_idx2 = (col_b0[kk] * params.IC + ic2) * in_hw + u32(ih2) * in_w + u32(iw2);
+          b_vec2[kk] = input[in_idx2];
+        }
+      }
+      b_sub[b_r2][b_c4_2] = b_vec2;
+    } else {
+      b_sub[b_r2][b_c4_2] = vec4<f16>(0.0h);
+    }
+
+    let bk3 = k_start + b_r3;
+    if (bk3 < K) {
+      let ic3 = bk3 / khw;
+      let rem3 = bk3 % khw;
+      let kh3 = i32(rem3 / kernel_width()) * dH;
+      let kw3 = i32(rem3 % kernel_width()) * dW;
+
+      var b_vec3 = vec4<f16>(0.0h);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih3 = col_ih_base0[kk] + kh3;
+        let iw3 = col_iw_base0[kk] + kw3;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem3)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih3 >= 0 && ih3 < iH && iw3 >= 0 && iw3 < iW)) {
+          let in_idx3 = (col_b0[kk] * params.IC + ic3) * in_hw + u32(ih3) * in_w + u32(iw3);
+          b_vec3[kk] = input[in_idx3];
+        }
+      }
+      b_sub[b_r3][b_c4_3] = b_vec3;
+    } else {
+      b_sub[b_r3][b_c4_3] = vec4<f16>(0.0h);
+    }
+
+    workgroupBarrier();
+
+    let thread_r = local_id.y << 1u;
+    let thread_c4 = local_id.x;
+
+    for (var k4 = 0u; k4 < 4u; k4 = k4 + 1u) {
+      let b0 = b_sub[k4 * 4u + 0u][thread_c4];
+      let b1 = b_sub[k4 * 4u + 1u][thread_c4];
+      let b2 = b_sub[k4 * 4u + 2u][thread_c4];
+      let b3 = b_sub[k4 * 4u + 3u][thread_c4];
+
+      let a0 = a_sub[thread_r + 0u][k4];
+      let a1 = a_sub[thread_r + 1u][k4];
+
+      acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;
+      acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;
+    }
+    workgroupBarrier();
+  }
+
+  let thread_r = local_id.y << 1u;
+  let out_r0 = tile_row0 + thread_r;
+  let out_c_base = tile_col0 + (local_id.x << 2u);
+
+  var bias_val = vec4<f16>(0.0h);
+  if (params.has_bias != 0u) {
+    if (out_r0 + 0u < M) { bias_val.x = bias[out_r0 + 0u]; }
+    if (out_r0 + 1u < M) { bias_val.y = bias[out_r0 + 1u]; }
+  }
+
+  acc0 = acc0 + vec4<f16>(bias_val.x);
+  acc1 = acc1 + vec4<f16>(bias_val.y);
+
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let out_c = out_c_base + kk;
+    if (out_c < N) {
+      // Reuse the batch decoded for input gathering; output is NCHW.
+      let out_base = col_b0[kk] * (M - 1u) * ohw + out_c;
+      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * ohw + out_base] = acc0[kk]; }
+      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * ohw + out_base] = acc1[kk]; }
+    }
+  }
+}
+`;
diff --git a/src/shaders/convolution/conv2d-tile8.wgsl.ts b/src/shaders/convolution/conv2d-tile8.wgsl.ts
new file mode 100644
index 0000000..c82154d
--- /dev/null
+++ b/src/shaders/convolution/conv2d-tile8.wgsl.ts
@@ -0,0 +1,285 @@
+/**
+ * WGSL compute shader for 8x64 register-tiled 2D convolution GEMM (2x4 per thread across 64 threads).
+ * Targets dense 3x3 layers with at most eight output channels and large spatial grids.
+ *
+ * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)
+ * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)
+ */
+export const SHADER_CONV2D_TILE8 = /* wgsl */ `
+struct Params {
+  B: u32, IC: u32, IH: u32, IW: u32,
+  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,
+  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,
+  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,
+}
+@group(0) @binding(0) var<storage, read_write> out: array<f32>;
+@group(0) @binding(1) var<storage, read> input: array<f32>;
+@group(0) @binding(2) var<storage, read> weight: array<vec4<f32>>;
+@group(0) @binding(3) var<storage, read> bias: array<f32>;
+@group(0) @binding(4) var<uniform> params: Params;
+
+// Geometry constants let every backend simplify division in the gather loop.
+override kernel_h: u32 = 0u;
+override kernel_w: u32 = 0u;
+
+// Zero preserves uniform-driven execution for callers using the raw template.
+fn kernel_height() -> u32 {
+  return select(params.KH, kernel_h, kernel_h != 0u);
+}
+fn kernel_width() -> u32 {
+  return select(params.KW, kernel_w, kernel_w != 0u);
+}
+
+// a_sub: 32 output channels x 16 K elements (4 vec4s) = 128 vec4s (2 KB)
+var<workgroup> a_sub: array<array<vec4<f32>, 4>, 8>;
+// b_sub: 16 K elements x 64 spatial elements (16 vec4s) = 256 vec4s (4 KB)
+var<workgroup> b_sub: array<array<vec4<f32>, 16>, 16>;
+
+@compute @workgroup_size(16, 4, 1)
+fn main(
+  @builtin(workgroup_id) wg_id: vec3<u32>,
+  @builtin(local_invocation_id) local_id: vec3<u32>,
+  @builtin(local_invocation_index) tid: u32
+) {
+  let tile_row0 = wg_id.y * 8u;
+  let tile_col0 = wg_id.x * 64u;
+  let M = params.OC;
+  let N = params.B * params.OH * params.OW;
+  let K = params.IC * kernel_height() * kernel_width();
+  let K_vecs = K >> 2u;
+  let khw = kernel_height() * kernel_width();
+  let ohw = params.OH * params.OW;
+
+  let iH = i32(params.IH);
+  let iW = i32(params.IW);
+  let in_hw = params.IH * params.IW;
+  let in_w = params.IW;
+  let sH = i32(params.sH);
+  let sW = i32(params.sW);
+  let pH = i32(params.pH);
+  let pW = i32(params.pW);
+  let dH = i32(params.dH);
+  let dW = i32(params.dW);
+
+  var acc0 = vec4<f32>(0.0);
+  var acc1 = vec4<f32>(0.0);
+
+  // 64 threads cooperatively load 128 vec4s of A (32 rows x 4 vec4s)
+  let a_r = tid >> 2u;      // 0..15
+  let a_c = tid & 3u;       // 0..3
+  let a_m = tile_row0 + a_r;
+  let a_valid = a_r < 8u && a_m < M;
+
+  // 64 threads load 256 vec4s of B (16 rows x 16 vec4s) -> 2 passes per thread
+  // Four cooperative input loads per thread cover the same 8x64 K tile.
+  let b_r0 = tid >> 4u;      // 0..3
+  let b_c4_0 = tid & 15u;
+  let b_r1 = b_r0 + 4u;
+  let b_c4_1 = b_c4_0;
+  let b_r2 = b_r0 + 8u;
+  let b_c4_2 = b_c4_0;
+  let b_r3 = b_r0 + 12u;
+  let b_c4_3 = b_c4_0;
+
+  let n_base0 = tile_col0 + (b_c4_0 << 2u);
+
+  var col_b0: array<u32, 4>;
+  var col_ih_base0: array<i32, 4>;
+  var col_iw_base0: array<i32, 4>;
+  var col_valid0: array<bool, 4>;
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let n = n_base0 + kk;
+    if (n < N) {
+      col_valid0[kk] = true;
+      let b_val = n / ohw;
+      let sp = n % ohw;
+      col_b0[kk] = b_val;
+      let oh = sp / params.OW;
+      let ow = sp % params.OW;
+      col_ih_base0[kk] = i32(oh) * sH - pH;
+      col_iw_base0[kk] = i32(ow) * sW - pW;
+    } else {
+      col_valid0[kk] = false;
+      col_b0[kk] = 0u;
+      col_ih_base0[kk] = 0;
+      col_iw_base0[kk] = 0;
+    }
+  }
+
+  // For 3x3 kernels, validity is invariant across input channels. Interior
+  // columns get all nine bits; borders and spatial tails get only valid taps.
+  var tap_mask: array<u32, 4>;
+  if (kernel_height() == 3u && kernel_width() == 3u) {
+    for (var col = 0u; col < 4u; col++) {
+      var mask = 0u;
+      if (col_valid0[col]) {
+        if (col_ih_base0[col] >= 0 && col_iw_base0[col] >= 0 &&
+            col_ih_base0[col] + 2 * dH < i32(params.IH) &&
+            col_iw_base0[col] + 2 * dW < i32(params.IW)) {
+          mask = 0x1ffu;
+        } else {
+          for (var ky = 0u; ky < 3u; ky++) {
+            let iy = col_ih_base0[col] + i32(ky) * dH;
+            for (var kx = 0u; kx < 3u; kx++) {
+              let ix = col_iw_base0[col] + i32(kx) * dW;
+              if (iy >= 0 && iy < i32(params.IH) && ix >= 0 && ix < i32(params.IW)) {
+                mask = mask | (1u << (ky * 3u + kx));
+              }
+            }
+          }
+        }
+      }
+      tap_mask[col] = mask;
+    }
+  }
+
+  let num_tiles = (K + 15u) >> 4u;
+  for (var t = 0u; t < num_tiles; t = t + 1u) {
+    let k4_start = t << 2u;
+    let k_start = t << 4u;
+
+    if (a_r < 8u) {
+      if (a_valid && (k4_start + a_c) < K_vecs) {
+        a_sub[a_r][a_c] = weight[a_m * K_vecs + k4_start + a_c];
+      } else {
+        a_sub[a_r][a_c] = vec4<f32>(0.0);
+      }
+    }
+
+    // Load first B slice (rows 0..7)
+    let bk0 = k_start + b_r0;
+    if (bk0 < K) {
+      let ic0 = bk0 / khw;
+      let rem0 = bk0 % khw;
+      let kh0 = i32(rem0 / kernel_width()) * dH;
+      let kw0 = i32(rem0 % kernel_width()) * dW;
+
+      var b_vec0 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih0 = col_ih_base0[kk] + kh0;
+        let iw0 = col_iw_base0[kk] + kw0;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem0)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih0 >= 0 && ih0 < iH && iw0 >= 0 && iw0 < iW)) {
+          let in_idx0 = (col_b0[kk] * params.IC + ic0) * in_hw + u32(ih0) * in_w + u32(iw0);
+          b_vec0[kk] = input[in_idx0];
+        }
+      }
+      b_sub[b_r0][b_c4_0] = b_vec0;
+    } else {
+      b_sub[b_r0][b_c4_0] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    let bk1 = k_start + b_r1;
+    if (bk1 < K) {
+      let ic1 = bk1 / khw;
+      let rem1 = bk1 % khw;
+      let kh1 = i32(rem1 / kernel_width()) * dH;
+      let kw1 = i32(rem1 % kernel_width()) * dW;
+
+      var b_vec1 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih1 = col_ih_base0[kk] + kh1;
+        let iw1 = col_iw_base0[kk] + kw1;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem1)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih1 >= 0 && ih1 < iH && iw1 >= 0 && iw1 < iW)) {
+          let in_idx1 = (col_b0[kk] * params.IC + ic1) * in_hw + u32(ih1) * in_w + u32(iw1);
+          b_vec1[kk] = input[in_idx1];
+        }
+      }
+      b_sub[b_r1][b_c4_1] = b_vec1;
+    } else {
+      b_sub[b_r1][b_c4_1] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    let bk2 = k_start + b_r2;
+    if (bk2 < K) {
+      let ic2 = bk2 / khw;
+      let rem2 = bk2 % khw;
+      let kh2 = i32(rem2 / kernel_width()) * dH;
+      let kw2 = i32(rem2 % kernel_width()) * dW;
+
+      var b_vec2 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih2 = col_ih_base0[kk] + kh2;
+        let iw2 = col_iw_base0[kk] + kw2;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem2)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih2 >= 0 && ih2 < iH && iw2 >= 0 && iw2 < iW)) {
+          let in_idx2 = (col_b0[kk] * params.IC + ic2) * in_hw + u32(ih2) * in_w + u32(iw2);
+          b_vec2[kk] = input[in_idx2];
+        }
+      }
+      b_sub[b_r2][b_c4_2] = b_vec2;
+    } else {
+      b_sub[b_r2][b_c4_2] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    let bk3 = k_start + b_r3;
+    if (bk3 < K) {
+      let ic3 = bk3 / khw;
+      let rem3 = bk3 % khw;
+      let kh3 = i32(rem3 / kernel_width()) * dH;
+      let kw3 = i32(rem3 % kernel_width()) * dW;
+
+      var b_vec3 = vec4<f32>(0.0);
+      for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+        let ih3 = col_ih_base0[kk] + kh3;
+        let iw3 = col_iw_base0[kk] + kw3;
+        if ((kernel_height() == 3u && kernel_width() == 3u && (tap_mask[kk] & (1u << rem3)) != 0u) ||
+            ((kernel_height() != 3u || kernel_width() != 3u) && col_valid0[kk] && ih3 >= 0 && ih3 < iH && iw3 >= 0 && iw3 < iW)) {
+          let in_idx3 = (col_b0[kk] * params.IC + ic3) * in_hw + u32(ih3) * in_w + u32(iw3);
+          b_vec3[kk] = input[in_idx3];
+        }
+      }
+      b_sub[b_r3][b_c4_3] = b_vec3;
+    } else {
+      b_sub[b_r3][b_c4_3] = vec4<f32>(0.0);
+    }
+
+    // Load second B slice (rows 8..15)
+    workgroupBarrier();
+
+    let thread_r = local_id.y << 1u; // 0..28 (step 4)
+    let thread_c4 = local_id.x;      // 0..15
+
+    for (var k4 = 0u; k4 < 4u; k4 = k4 + 1u) {
+      let b0 = b_sub[k4 * 4u + 0u][thread_c4];
+      let b1 = b_sub[k4 * 4u + 1u][thread_c4];
+      let b2 = b_sub[k4 * 4u + 2u][thread_c4];
+      let b3 = b_sub[k4 * 4u + 3u][thread_c4];
+
+      let a0 = a_sub[thread_r + 0u][k4];
+      let a1 = a_sub[thread_r + 1u][k4];
+
+      acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;
+      acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;
+    }
+    workgroupBarrier();
+  }
+
+  let thread_r = local_id.y << 1u;
+  let out_r0 = tile_row0 + thread_r;
+  let out_c_base = tile_col0 + (local_id.x << 2u);
+
+  var bias_val = vec4<f32>(0.0);
+  if (params.has_bias != 0u) {
+    if (out_r0 + 0u < M) { bias_val.x = bias[out_r0 + 0u]; }
+    if (out_r0 + 1u < M) { bias_val.y = bias[out_r0 + 1u]; }
+  }
+
+  acc0 = acc0 + vec4<f32>(bias_val.x);
+  acc1 = acc1 + vec4<f32>(bias_val.y);
+
+  for (var kk = 0u; kk < 4u; kk = kk + 1u) {
+    let out_c = out_c_base + kk;
+    if (out_c < N) {
+      // Reuse the batch decoded for input gathering; output is NCHW.
+      let out_base = col_b0[kk] * (M - 1u) * ohw + out_c;
+      if (out_r0 + 0u < M) { out[(out_r0 + 0u) * ohw + out_base] = acc0[kk]; }
+      if (out_r0 + 1u < M) { out[(out_r0 + 1u) * ohw + out_base] = acc1[kk]; }
+    }
+  }
+}
+`;
diff --git a/src/shaders/convolution/index.ts b/src/shaders/convolution/index.ts
index f4e75a5..e60aa85 100644
--- a/src/shaders/convolution/index.ts
+++ b/src/shaders/convolution/index.ts
@@ -11,6 +11,12 @@ import { SHADER_CONV2D_1X1_64X64 } from './conv2d-1x1-tile64.wgsl';
 import { SHADER_CONV2D_1X1_64X64_F16 } from './conv2d-1x1-tile64-f16.wgsl';
 import { SHADER_CONV2D_TILE64 } from './conv2d-tile64.wgsl';
 import { SHADER_CONV2D_TILE32 } from './conv2d-tile32.wgsl';
+import { SHADER_CONV2D_DIRECT_SMALL } from './conv2d-direct-small.wgsl';
+import { SHADER_CONV2D_DIRECT_SMALL_F16 } from './conv2d-direct-small-f16.wgsl';
+import { SHADER_CONV2D_TILE8 } from './conv2d-tile8.wgsl';
+import { SHADER_CONV2D_TILE8_F16 } from './conv2d-tile8-f16.wgsl';
+import { SHADER_CONV2D_TILE16 } from './conv2d-tile16.wgsl';
+import { SHADER_CONV2D_TILE16_F16 } from './conv2d-tile16-f16.wgsl';
 import { SHADER_CONV2D_1X1_TILE32 } from './conv2d-1x1-tile32.wgsl';
 import { SHADER_CONV2D_1X1_TILE32_F16 } from './conv2d-1x1-tile32-f16.wgsl';
 import { SHADER_CONV2D_DEPTHWISE } from './conv2d-depthwise.wgsl';
@@ -166,7 +172,8 @@ function recordIn(ctx: WgpuExecutionContext, args: ConvolutionArgs): void {
 
   // Variant selection: 1x1 convolutions use the pointwise GEMM kernel (no im2col),
   // with 128-bit vec4 memory optimization when dimensions are divisible by 4.
-  // General dense convolutions use implicit-im2col tiled GEMM, grouped/depthwise
+  // Short 3x3 filters have a shape-qualified direct path. Other dense convolutions
+  // use implicit-im2col tiled GEMM, grouped/depthwise
   // convs through the direct kernel, and transposed convs through the gather kernel.
   const is1x1 =
     !transposed &&
@@ -181,6 +188,54 @@ function recordIn(ctx: WgpuExecutionContext, args: ConvolutionArgs): void {
   const is1x1Vec4 = is1x1 && ic % 4 === 0 && (oh * ow) % 4 === 0 && oc % 4 === 0;
   const is1x1Tile32 = is1x1Vec4 && b === 1 && oc <= 32 && oh * ow >= 64 && ic >= 16;
   const is1x1Tile64 = is1x1Vec4 && b === 1 && oc > 32 && oh * ow >= 64 && ic >= 16;
+  // Stage short RGB filters once instead of expanding them into GEMM input tiles.
+  const isRgb =
+    !transposed &&
+    groups === 1 &&
+    ic === 3 &&
+    kh === 3 &&
+    kw === 3 &&
+    sH === 2 &&
+    sW === 2 &&
+    pH === 1 &&
+    pW === 1 &&
+    dH === 1 &&
+    dW === 1 &&
+    oc >= 8 &&
+    oc <= 16 &&
+    oh * ow >= 4096;
+  // Narrow tiles are limited to the same-padding stride/dilation families
+  // covered by the regression mesh. Other geometries retain their old route.
+  const isNarrowGeometry =
+    sH === sW &&
+    (sH === 1 || sH === 2) &&
+    dH === dW &&
+    (dH === 1 || dH === 2) &&
+    pH === dH &&
+    pW === dW;
+  const isDenseTile8 =
+    !transposed &&
+    groups === 1 &&
+    kh === 3 &&
+    kw === 3 &&
+    isNarrowGeometry &&
+    oc >= 4 &&
+    oc <= 8 &&
+    b * oh * ow >= 4096 &&
+    ic % 4 === 0;
+  const isDirectSmall =
+    (isRgb || (isDenseTile8 && ic <= 16 && dH === 1)) &&
+    b <= device.limits.maxComputeWorkgroupsPerDimension &&
+    Math.ceil((oh * ow) / 128) <= device.limits.maxComputeWorkgroupsPerDimension;
+  const isDenseTile16 =
+    !transposed &&
+    groups === 1 &&
+    kh === 3 &&
+    kw === 3 &&
+    oc >= 8 &&
+    oc <= 16 &&
+    b * oh * ow >= 4096 &&
+    ic % 4 === 0;
   const isDenseTile32 =
     !transposed &&
     groups === 1 &&
@@ -224,6 +279,12 @@ function recordIn(ctx: WgpuExecutionContext, args: ConvolutionArgs): void {
       code = isF16 ? SHADER_CONV2D_1X1_TILE32_F16 : SHADER_CONV2D_1X1_TILE32;
     } else if (is1x1Tile64) {
       code = isF16 ? SHADER_CONV2D_1X1_64X64_F16 : SHADER_CONV2D_1X1_64X64;
+    } else if (isDirectSmall) {
+      code = isF16 ? SHADER_CONV2D_DIRECT_SMALL_F16 : SHADER_CONV2D_DIRECT_SMALL;
+    } else if (isDenseTile8) {
+      code = isF16 ? SHADER_CONV2D_TILE8_F16 : SHADER_CONV2D_TILE8;
+    } else if (isDenseTile16) {
+      code = isF16 ? SHADER_CONV2D_TILE16_F16 : SHADER_CONV2D_TILE16;
     } else if (isDenseTile32) {
       code = isF16 ? SHADER_CONV2D_TILE32_F16 : SHADER_CONV2D_TILE32;
     } else if (isDenseTile64) {
@@ -265,16 +326,49 @@ function recordIn(ctx: WgpuExecutionContext, args: ConvolutionArgs): void {
     workgroupCountX = Math.ceil((oh * ow) / 64);
     workgroupCountY = Math.ceil(oc / 64);
     constants = {};
+  } else if (isDirectSmall) {
+    workgroupCountX = Math.ceil((oh * ow) / 128);
+    workgroupCountY = Math.ceil(oc / 4);
+    workgroupCountZ = b;
+    /* eslint-disable camelcase, @typescript-eslint/naming-convention -- WGSL override names */
+    constants = {
+      input_h: ih,
+      input_w: iw,
+      output_h: oh,
+      output_w: ow,
+      channels: ic,
+      filter_count: ic * 9,
+      stride_h: sH,
+      stride_w: sW,
+      pad_h: pH,
+      pad_w: pW,
+      dilation_h: dH,
+      dilation_w: dW,
+    };
+    /* eslint-enable camelcase, @typescript-eslint/naming-convention */
+  } else if (isDenseTile8) {
+    workgroupCountX = Math.ceil((b * oh * ow) / 64);
+    workgroupCountY = Math.ceil(oc / 8);
+    // eslint-disable-next-line camelcase, @typescript-eslint/naming-convention
+    constants = { kernel_h: kh, kernel_w: kw };
+  } else if (isDenseTile16) {
+    // 16x64 register-tiled GEMM for narrow dense 3x3 convolution.
+    workgroupCountX = Math.ceil((b * oh * ow) / 64);
+    workgroupCountY = Math.ceil(oc / 16);
+    // eslint-disable-next-line camelcase, @typescript-eslint/naming-convention
+    constants = { kernel_h: kh, kernel_w: kw };
   } else if (isDenseTile32) {
     // 32x64 register-tiled GEMM for general dense convolution
     workgroupCountX = Math.ceil((b * oh * ow) / 64);
     workgroupCountY = Math.ceil(oc / 32);
-    constants = {};
+    // eslint-disable-next-line camelcase, @typescript-eslint/naming-convention
+    constants = { kernel_h: kh, kernel_w: kw };
   } else if (isDenseTile64) {
     // 64x64 register-tiled GEMM for general dense convolution
     workgroupCountX = Math.ceil((b * oh * ow) / 64);
     workgroupCountY = Math.ceil(oc / 64);
-    constants = {};
+    // eslint-disable-next-line camelcase, @typescript-eslint/naming-convention
+    constants = { kernel_h: kh, kernel_w: kw };
   } else {
     // GEMM kernel: fixed 8x8 workgroup covering a 32x32 output tile;
     // grid over (N = B*OH*OW cols, M = OC rows)
diff --git a/tests/bench-kernels.test.ts b/tests/bench-kernels.test.ts
new file mode 100644
index 0000000..cb9f3bc
--- /dev/null
+++ b/tests/bench-kernels.test.ts
@@ -0,0 +1,280 @@
+import { readFileSync, writeFileSync } from 'node:fs';
+import { execFileSync } from 'node:child_process';
+import { tmpdir } from 'node:os';
+import { resolve } from 'node:path';
+import { it, expect } from 'vitest';
+import { WgpuExecutionContext, createComputeBundle } from '../src';
+import { KernelTimingContext } from './helpers/kernel-timing';
+
+// Opt-in comparison against any commit, e.g.:
+// WGPU_KERNEL_BASELINE=224da79 npx vitest run tests/bench-kernels.test.ts --disableConsoleIntercept
+// Both versions use the same device, inputs and dispatch counts, with alternating
+// measurement order. Raw samples are saved for inspecting variance.
+it.skipIf(!process.env.WGPU_KERNEL_BASELINE)(
+  'compares convolution and GEMM with a git baseline',
+  async () => {
+    const adapter = await navigator.gpu.requestAdapter();
+    if (!adapter) throw new Error('No suitable GPU adapter found');
+    const requiredFeatures = (['shader-f16', 'timestamp-query'] as GPUFeatureName[]).filter(
+      (feature) => adapter.features.has(feature)
+    );
+    const device = await adapter.requestDevice({ requiredFeatures });
+    const gpuTiming = device.features.has('timestamp-query');
+    device.pushErrorScope('validation');
+    const baseline = process.env.WGPU_KERNEL_BASELINE!;
+    const report: unknown[] = [];
+    const matrixCases = [
+      [1, 64, 64, 64],
+      [1, 256, 256, 256],
+      [1, 1024, 1024, 1024],
+      [1, 128, 256, 512],
+      [1, 65, 68, 100],
+      [1, 33, 36, 44],
+      [2, 400, 32, 400],
+      [2, 64, 400, 400],
+    ];
+    const narrowCases = [
+      [16, 8, 160, 3, 1, 1],
+      [8, 16, 160, 3, 1, 1],
+      [32, 16, 80, 3, 1, 1],
+      [64, 16, 80, 3, 1, 1],
+      [16, 16, 64, 3, 1, 1],
+      [16, 16, 80, 3, 1, 1],
+      [32, 16, 40, 3, 1, 1],
+      [8, 16, 80, 3, 1, 1],
+      [16, 8, 80, 3, 1, 1],
+      [16, 16, 160, 3, 2, 1],
+      [32, 16, 20, 3, 1, 1],
+      [4, 13, 17, 3, 1, 1],
+      [24, 16, 448, 3, 1, 1],
+    ];
+    const narrowOnly = process.env.WGPU_KERNEL_CASES === 'narrow';
+    const convCases = narrowOnly
+      ? narrowCases
+      : [
+          [64, 64, 56, 3, 1, 1],
+          [960, 48, 14, 3, 1, 1],
+          [64, 64, 80, 3, 2, 1],
+          [32, 32, 40, 3, 1, 1],
+          [24, 16, 448, 3, 1, 1],
+          [48, 48, 112, 3, 1, 1],
+          [48, 24, 224, 3, 1, 1],
+          [8, 12, 17, 2, 1, 0],
+          ...narrowCases.slice(0, 4),
+        ];
+    for (const dtype of ['float32', 'float16'] as const) {
+      if (dtype === 'float16' && !device.features.has('shader-f16')) continue;
+      const array = dtype === 'float16' ? Float16Array : Float32Array;
+      const suffix = dtype === 'float16' ? '-f16' : '';
+      const fill = (length: number) => {
+        const data = new array(length);
+        for (let i = 0; i < length; i++) data[i] = (((i * 17 + 11) % 61) - 30) / 64;
+        return data;
+      };
+      for (const category of narrowOnly ? ['convolution'] : ['matrix', 'convolution', 'clamp']) {
+        for (const shape of category === 'matrix' ? matrixCases : convCases) {
+          const ctx = new WgpuExecutionContext(device);
+          let path: string;
+          let counts: number[];
+          let params: GPUBuffer;
+          let tensors;
+          let constants: Record<string, number> = {};
+          let out;
+          if (category === 'matrix') {
+            const [batch, m, k, n] = shape;
+            const group = batch === 1 ? 'mm' : 'bmm';
+            const variant = m >= 64 && n >= 64 && k >= 16 ? '64x64' : 'vec4';
+            path = `src/shaders/${group}/${group}-${variant}${suffix}.wgsl.ts`;
+            const a = ctx.tensor(dtype, [batch, m, k]).setData(fill(batch * m * k));
+            const b = ctx.tensor(dtype, [batch, k, n]).setData(fill(batch * k * n));
+            out = ctx.tensor(dtype, [batch, m, n]);
+            params = ctx.uniformBuffer(
+              new Uint32Array(batch === 1 ? [m, n, k, 0] : [batch, m, n, k])
+            );
+            tensors = [a, b, out];
+            counts = [
+              Math.ceil(n / (variant === '64x64' ? 64 : 32)),
+              Math.ceil(m / (variant === '64x64' ? 64 : 32)),
+              batch,
+            ];
+          } else {
+            const [ic, oc, h, kernel, stride, pad] = shape;
+            const oh = Math.floor((h + 2 * pad - kernel) / stride) + 1;
+            const group = category === 'clamp' ? 'conv-with-clamp' : 'convolution';
+            const prefix = category === 'clamp' ? 'conv-with-clamp' : 'conv2d';
+            path = `src/shaders/${group}/${prefix}-tile${oc <= 32 ? '32' : '64'}${suffix}.wgsl.ts`;
+            const input = ctx.tensor(dtype, [1, ic, h, h]).setData(fill(ic * h * h));
+            const weight = ctx
+              .tensor(dtype, [oc, ic, kernel, kernel])
+              .setData(fill(oc * ic * kernel * kernel));
+            const bias = ctx.tensor(dtype, [oc]).setData(fill(oc));
+            out = ctx.tensor(dtype, [1, oc, oh, oh]);
+            const data = new ArrayBuffer(category === 'clamp' ? 96 : 84);
+            new Uint32Array(data).set(
+              category === 'clamp'
+                ? [
+                    1,
+                    ic,
+                    h,
+                    h,
+                    oc,
+                    oh,
+                    oh,
+                    kernel,
+                    kernel,
+                    stride,
+                    stride,
+                    pad,
+                    pad,
+                    1,
+                    1,
+                    1,
+                    oc * oh * oh,
+                    1,
+                    ic,
+                    0,
+                    0,
+                    0,
+                  ]
+                : [
+                    1,
+                    ic,
+                    h,
+                    h,
+                    oc,
+                    oh,
+                    oh,
+                    kernel,
+                    kernel,
+                    stride,
+                    stride,
+                    pad,
+                    pad,
+                    1,
+                    1,
+                    1,
+                    1,
+                    0,
+                    0,
+                    0,
+                    0,
+                  ]
+            );
+            if (category === 'clamp') {
+              new Float32Array(data)[22] = 0;
+              new Float32Array(data)[23] = Infinity;
+            }
+            params = ctx.uniformBuffer(data);
+            tensors = [out, input, weight, bias];
+            // eslint-disable-next-line camelcase, @typescript-eslint/naming-convention
+            constants = { kernel_h: kernel, kernel_w: kernel };
+            counts = [Math.ceil((oh * oh) / 64), Math.ceil(oc / (oc <= 32 ? 32 : 64)), 1];
+          }
+          const bindings = tensors.map((t, binding) => ({ binding, buffer: t.buffer }));
+          bindings.push({ binding: bindings.length, buffer: params });
+          const useNarrow =
+            category === 'convolution' &&
+            shape[1] >= 8 &&
+            shape[1] <= 16 &&
+            shape[3] === 3 &&
+            shape[0] % 4 === 0;
+          const candidatePath = useNarrow ? path.replace('-tile32', '-tile16') : path;
+          const candidate = readFileSync(candidatePath, 'utf8').split('`')[1];
+          device.pushErrorScope('validation');
+          const original = execFileSync('git', ['show', `${baseline}:${path}`], {
+            encoding: 'utf8',
+          }).split('`')[1];
+          // Apply the same geometry specialization when the baseline supports it;
+          // otherwise this comparison would also measure an already-landed change.
+          const beforeConstants = original.includes('override kernel_h') ? constants : {};
+          const before = createComputeBundle(device, original, bindings, beforeConstants);
+          const after = createComputeBundle(device, candidate, bindings, constants);
+          const compileError = await device.popErrorScope();
+          if (compileError) throw compileError;
+          const contexts = [new KernelTimingContext(device), new KernelTimingContext(device)];
+          // Amortize submission overhead and timestamp quantization on short kernels.
+          // Scale by mathematical work, independently of GPU vendor or model.
+          const work =
+            category === 'matrix'
+              ? shape.reduce((product, dimension) => product * dimension, 1)
+              : out.numel * shape[0] * shape[3] * shape[3];
+          const repeats = Math.min(512, Math.max(8, Math.ceil(2e9 / work)));
+          for (let version = 0; version < 2; version++) {
+            const bundle = version === 0 ? before : after;
+            for (let i = 0; i < repeats; i++)
+              contexts[version].addDispatch({
+                pipeline: bundle.pipeline,
+                bindGroup: bundle.bindGroup,
+                workgroupCountX: counts[0],
+                workgroupCountY: counts[1],
+                workgroupCountZ: counts[2],
+              });
+            for (let i = 0; i < 3; i++) {
+              contexts[version].submit();
+              await contexts[version].sync();
+            }
+          }
+          const samples: number[][] = [[], []];
+          for (let i = 0; i < 11; i++)
+            for (const version of i % 2 ? [1, 0] : [0, 1]) {
+              const start = performance.now();
+              contexts[version].submit();
+              await contexts[version].sync();
+              samples[version].push(
+                (gpuTiming ? contexts[version].gpuMs : performance.now() - start) / repeats
+              );
+            }
+          const median = samples.map((s) => [...s].sort((a, b) => a - b)[5]);
+          // Check output equivalence outside timing, including FP16 accumulation order.
+          const values = [];
+          const arrayType = dtype === 'float16' ? Float16Array : Float32Array;
+          for (const context of contexts) {
+            context.submit();
+            await context.sync();
+            values.push(new arrayType(await out.getData()));
+          }
+          let maxDelta = 0;
+          for (let i = 0; i < values[0].length; i++) {
+            if (!Number.isFinite(values[0][i]) || !Number.isFinite(values[1][i]))
+              throw new Error('Nonfinite convolution/matrix output');
+            maxDelta = Math.max(maxDelta, Math.abs(values[0][i] - values[1][i]));
+          }
+          expect(maxDelta).toBe(0);
+          const entry = {
+            maxDelta,
+            category,
+            dtype,
+            shape,
+            repeats,
+            beforeMs: median[0],
+            afterMs: median[1],
+            speedup: median[0] / median[1],
+            samples,
+          };
+          report.push(entry);
+          // eslint-disable-next-line no-console
+          console.log(JSON.stringify({ ...entry, samples: undefined }));
+          ctx.destroy();
+          contexts.forEach((c) => c.destroy());
+        }
+      }
+    }
+    const error = await device.popErrorScope();
+    if (error) throw error;
+    writeFileSync(
+      process.env.WGPU_KERNEL_RESULTS ?? resolve(tmpdir(), 'wgpu-conv-mm-bench.json'),
+      JSON.stringify(
+        {
+          baseline,
+          gpu: { vendor: adapter.info.vendor, architecture: adapter.info.architecture },
+          method: `8–512 recorded dispatches per submit, scaled by operation count; submit + await sync; 3 warmups, 11 alternating samples per version; median milliseconds per dispatch; ${gpuTiming ? 'GPU timestamps' : 'wall clock fallback'}`,
+          results: report,
+        },
+        null,
+        2
+      )
+    );
+    device.destroy();
+  },
+  600_000
+);
diff --git a/tests/bench-models.test.ts b/tests/bench-models.test.ts
new file mode 100644
index 0000000..4f7c382
--- /dev/null
+++ b/tests/bench-models.test.ts
@@ -0,0 +1,89 @@
+import { readFileSync, writeFileSync, mkdtempSync, rmSync } from 'node:fs';
+import { execFileSync } from 'node:child_process';
+import { tmpdir } from 'node:os';
+import { join } from 'node:path';
+import { it, expect } from 'vitest';
+import { WgpuExecutionContext, type Program, type ProgramTensor } from '../src';
+import { setupGPU } from './helpers';
+
+// WGPU_MODEL_BASELINE=<commit> WGPU_MODEL_RESULTS=/tmp/model-results.json npx vitest run tests/bench-models.test.ts
+// Archives source into a temporary directory; both contexts use identical graphs and inputs.
+it.skipIf(!process.env.WGPU_MODEL_BASELINE)(
+  'compares unchanged model graphs with a git kernel baseline',
+  { timeout: 600_000 },
+  async () => {
+    const baseline = process.env.WGPU_MODEL_BASELINE!;
+    const dir = mkdtempSync(join(tmpdir(), 'wgpu-model-baseline-'));
+    try {
+      const archive = execFileSync('git', ['archive', baseline, 'src']);
+      execFileSync('tar', ['-x', '-C', dir], { input: archive });
+      const baselinePath = join(dir, 'src/index.ts');
+      const { WgpuExecutionContext: baselineContext } = (await import(
+        baselinePath
+      )) as typeof import('../src');
+      const device = await setupGPU();
+      const results = [];
+      const median = (a: number[]) => [...a].sort((a, b) => a - b)[a.length >> 1];
+      for (const model of ['depthart', 'yolo26n'])
+        for (const dtype of ['float32', 'float16'] as const) {
+          const suffix = dtype === 'float16' ? '-fp16' : '';
+          const root = `example/public/assets/${model}`;
+          const program = JSON.parse(
+            readFileSync(`${root}/program${suffix}.json`, 'utf8')
+          ) as Program;
+          const weights = new Uint8Array(readFileSync(`${root}/weights${suffix}.bin`)).buffer;
+          const array = dtype === 'float16' ? Float16Array : Float32Array;
+          const runs = [baselineContext, WgpuExecutionContext].map((contextType) => {
+            const ctx = new contextType(device),
+              input = ctx.tensor(
+                dtype,
+                (program.values[program.inputIds[0]] as ProgramTensor).shape
+              ),
+              out = ctx.tensor(
+                dtype,
+                (program.values[program.outputIds[0]] as ProgramTensor).shape
+              );
+            input.setData(
+              new array(Array.from({ length: input.numel }, (value, i) => (i % 251) / 250 - 0.5))
+            );
+            ctx.recordProgram(program, weights, [input, out]);
+            return { ctx, out };
+          });
+          const samples: number[][] = [[], []];
+          for (let i = -10; i < 51; i++)
+            for (const version of i & 1 ? [1, 0] : [0, 1]) {
+              const start = performance.now();
+              runs[version].ctx.submit();
+              await runs[version].ctx.sync();
+              if (i >= 0) samples[version].push(performance.now() - start);
+            }
+          const output = await Promise.all(runs.map(async (r) => new array(await r.out.getData())));
+          let maxDelta = 0;
+          for (let i = 0; i < output[0].length; i++) {
+            if (!Number.isFinite(output[1][i])) throw Error('nonfinite');
+            maxDelta = Math.max(maxDelta, Math.abs(output[0][i] - output[1][i]));
+          }
+          expect(maxDelta).toBe(0);
+          const result = {
+            model,
+            dtype,
+            beforeMs: median(samples[0]),
+            afterMs: median(samples[1]),
+            speedup: median(samples[0]) / median(samples[1]),
+            maxDelta,
+            samples,
+          };
+          results.push(result);
+          // eslint-disable-next-line no-console
+          console.log(JSON.stringify({ ...result, samples: undefined }));
+          runs.forEach((r) => r.ctx.destroy());
+        }
+      writeFileSync(
+        process.env.WGPU_MODEL_RESULTS ?? join(tmpdir(), 'wgpu-model-results.json'),
+        JSON.stringify({ baseline, warmups: 10, samples: 51, results }, null, 2) + '\n'
+      );
+    } finally {
+      rmSync(dir, { recursive: true, force: true });
+    }
+  }
+);
diff --git a/tests/helpers/kernel-timing.ts b/tests/helpers/kernel-timing.ts
new file mode 100644
index 0000000..3dff9ab
--- /dev/null
+++ b/tests/helpers/kernel-timing.ts
@@ -0,0 +1,81 @@
+import { WgpuExecutionContext } from '../../src';
+import type { WgpuDispatch } from '../../src/command';
+
+/** Operator-only benchmark context with optional GPU timestamps per submission. */
+export class KernelTimingContext extends WgpuExecutionContext {
+  readonly #dispatches: WgpuDispatch[] = [];
+  readonly #queries?: GPUQuerySet;
+  readonly #resolve?: GPUBuffer;
+  readonly #readback?: GPUBuffer;
+  gpuMs = 0;
+
+  /**
+   * @param device Device with optional timestamp-query support enabled.
+   */
+  constructor(device: GPUDevice) {
+    super(device);
+    if (device.features.has('timestamp-query')) {
+      this.#queries = device.createQuerySet({ type: 'timestamp', count: 2 });
+      this.#resolve = device.createBuffer({
+        size: 16,
+        usage: GPUBufferUsage.QUERY_RESOLVE | GPUBufferUsage.COPY_SRC,
+      });
+      this.#readback = device.createBuffer({
+        size: 16,
+        usage: GPUBufferUsage.COPY_DST | GPUBufferUsage.MAP_READ,
+      });
+    }
+  }
+
+  /**
+   * @param dispatch Dispatch recorded once before warmup and measurement.
+   */
+  override addDispatch(dispatch: WgpuDispatch): void {
+    super.addDispatch(dispatch);
+    this.#dispatches.push(dispatch);
+  }
+
+  /** Submit the fixed operator sequence, measuring only its compute pass. */
+  override submit(): void {
+    if (!this.#queries) return super.submit();
+    const encoder = this.device.createCommandEncoder();
+    const pass = encoder.beginComputePass({
+      timestampWrites: {
+        querySet: this.#queries,
+        beginningOfPassWriteIndex: 0,
+        endOfPassWriteIndex: 1,
+      },
+    });
+    for (const dispatch of this.#dispatches) {
+      pass.setPipeline(dispatch.pipeline);
+      pass.setBindGroup(0, dispatch.bindGroup);
+      pass.dispatchWorkgroups(
+        dispatch.workgroupCountX,
+        dispatch.workgroupCountY,
+        dispatch.workgroupCountZ ?? 1
+      );
+    }
+    pass.end();
+    encoder.resolveQuerySet(this.#queries, 0, 2, this.#resolve!, 0);
+    encoder.copyBufferToBuffer(this.#resolve!, 0, this.#readback!, 0, 16);
+    this.device.queue.submit([encoder.finish()]);
+  }
+
+  /** Wait for completion and read the GPU duration, in milliseconds. */
+  override async sync(): Promise<void> {
+    await super.sync();
+    if (!this.#readback) return;
+    await this.#readback.mapAsync(GPUMapMode.READ);
+    const times = new BigUint64Array(this.#readback.getMappedRange());
+    this.gpuMs = Number(times[1] - times[0]) / 1e6;
+    this.#readback.unmap();
+  }
+
+  /** Release the timestamp resources and context buffers. */
+  override destroy(): void {
+    this.#queries?.destroy();
+    this.#resolve?.destroy();
+    this.#readback?.destroy();
+    super.destroy();
+  }
+}
diff --git a/tests/shaders/convolution-specializations.test.ts b/tests/shaders/convolution-specializations.test.ts
new file mode 100644
index 0000000..6918733
--- /dev/null
+++ b/tests/shaders/convolution-specializations.test.ts
@@ -0,0 +1,85 @@
+import { describe, it } from 'vitest';
+import { WgpuExecutionContext, shaders } from '../../src';
+import { setupGPU, expectTensorClose } from '../helpers';
+
+const cases = [
+  { ic: 3, oc: 13, h: 131, w: 137, batch: 2, stride: 2, dilation: 1, bias: true },
+  { ic: 3, oc: 8, h: 129, w: 129, batch: 1, stride: 2, dilation: 1, bias: false },
+  { ic: 3, oc: 16, h: 128, w: 128, batch: 1, stride: 2, dilation: 1, bias: true },
+  { ic: 4, oc: 8, h: 65, w: 67, batch: 2, stride: 1, dilation: 1, bias: false },
+  { ic: 8, oc: 7, h: 64, w: 66, batch: 1, stride: 1, dilation: 1, bias: true },
+  { ic: 16, oc: 4, h: 64, w: 66, batch: 1, stride: 1, dilation: 1, bias: false },
+  { ic: 16, oc: 8, h: 65, w: 66, batch: 2, stride: 1, dilation: 1, bias: true },
+  { ic: 16, oc: 8, h: 128, w: 130, batch: 1, stride: 2, dilation: 1, bias: true },
+  { ic: 4, oc: 8, h: 64, w: 67, batch: 1, stride: 1, dilation: 2, bias: true },
+  // Generic FP32 fallback must multiply the batch offset by the input channels.
+  { ic: 3, oc: 17, h: 17, w: 19, batch: 2, stride: 2, dilation: 1, bias: false },
+  // Neighbors of the specialization boundaries keep using the existing kernels.
+  { ic: 3, oc: 17, h: 128, w: 128, batch: 1, stride: 2, dilation: 1, bias: false },
+  { ic: 12, oc: 8, h: 63, w: 65, batch: 1, stride: 1, dilation: 1, bias: true },
+];
+
+describe('convolution specialization boundaries', () => {
+  for (const dtype of ['float32', 'float16'] as const)
+    for (const c of cases)
+      it(`${dtype} ${JSON.stringify(c)}`, async () => {
+        const device = await setupGPU();
+        const ctx = new WgpuExecutionContext(device);
+        device.pushErrorScope('validation');
+        const array = dtype === 'float16' ? Float16Array : Float32Array;
+        // Exact dyadic products and bounded sums separate indexing errors from
+        // accumulation rounding, including on Node's Float16Array polyfill.
+        const fill = (length: number) =>
+          Float32Array.from({ length }, (unused, i) => (((i * 17 + (i >> 3)) % 3) - 1) / 8);
+        const input = fill(c.batch * c.ic * c.h * c.w);
+        const weight = fill(c.oc * c.ic * 9),
+          bias = fill(c.oc);
+        const oh = Math.floor((c.h - 1) / c.stride) + 1;
+        const ow = Math.floor((c.w - 1) / c.stride) + 1;
+        const expected = new Float32Array(c.batch * c.oc * oh * ow);
+        for (let b = 0; b < c.batch; b++)
+          for (let oc = 0; oc < c.oc; oc++)
+            for (let y = 0; y < oh; y++)
+              for (let x = 0; x < ow; x++) {
+                let sum = c.bias ? bias[oc] : 0;
+                for (let ic = 0; ic < c.ic; ic++)
+                  for (let ky = 0; ky < 3; ky++)
+                    for (let kx = 0; kx < 3; kx++) {
+                      const iy = y * c.stride - c.dilation + ky * c.dilation;
+                      const ix = x * c.stride - c.dilation + kx * c.dilation;
+                      if (iy >= 0 && iy < c.h && ix >= 0 && ix < c.w)
+                        sum +=
+                          input[((b * c.ic + ic) * c.h + iy) * c.w + ix] *
+                          weight[((oc * c.ic + ic) * 3 + ky) * 3 + kx];
+                    }
+                expected[((b * c.oc + oc) * oh + y) * ow + x] = sum;
+              }
+        try {
+          const x = ctx.tensor(dtype, [c.batch, c.ic, c.h, c.w]).setData(new array(input));
+          const w = ctx.tensor(dtype, [c.oc, c.ic, 3, 3]).setData(new array(weight));
+          const b = c.bias ? ctx.tensor(dtype, [c.oc]).setData(new array(bias)) : undefined;
+          const out = ctx
+            .tensor(dtype, [c.batch, c.oc, oh, ow])
+            .setData(new array(expected.length).fill(NaN));
+          ctx.recordShader(shaders.convolution, [
+            x,
+            w,
+            b,
+            [c.stride, c.stride],
+            [c.dilation, c.dilation],
+            [c.dilation, c.dilation],
+            false,
+            [0, 0],
+            1,
+            out,
+          ]);
+          ctx.submit();
+          await ctx.sync();
+          await expectTensorClose(out, Array.from(expected), 1e-5);
+          const error = await device.popErrorScope();
+          if (error) throw new Error(error.message);
+        } finally {
+          ctx.destroy();
+        }
+      });
+});
diff --git a/tests/shaders/hf-convolution.test.ts b/tests/shaders/hf-convolution.test.ts
new file mode 100644
index 0000000..25b0f85
--- /dev/null
+++ b/tests/shaders/hf-convolution.test.ts
@@ -0,0 +1,110 @@
+import { describe, it, expect } from 'vitest';
+import { WgpuExecutionContext } from '../../src';
+import { recordHfMatrix } from '../../utils/benchmark/hf-matrix';
+import { recordHfConvolution } from '../../utils/benchmark/hf-convolution';
+import { setupGPU, expectTensorClose } from '../helpers';
+
+const cases = [
+  { batch: 2, ic: 5, oc: 13, h: 3, w: 23, kernel: 1, stride: 1, pad: 0, dilation: 1, bias: true },
+  { batch: 1, ic: 32, oc: 68, h: 4, w: 17, kernel: 1, stride: 1, pad: 0, dilation: 1, bias: false },
+  { batch: 1, ic: 64, oc: 80, h: 3, w: 23, kernel: 1, stride: 1, pad: 0, dilation: 1, bias: true },
+  { batch: 2, ic: 3, oc: 13, h: 9, w: 11, kernel: 3, stride: 2, pad: 1, dilation: 1, bias: true },
+  { batch: 2, ic: 4, oc: 68, h: 11, w: 17, kernel: 3, stride: 1, pad: 2, dilation: 2, bias: false },
+  { batch: 1, ic: 32, oc: 16, h: 5, w: 19, kernel: 3, stride: 1, pad: 0, dilation: 1, bias: true },
+  { batch: 1, ic: 4, oc: 16, h: 1, w: 69, kernel: 3, stride: 1, pad: 1, dilation: 1, bias: false },
+];
+
+describe('pinned Hugging Face convolution adapters', () => {
+  it('falls back when experimental matrix features are not enabled', async () => {
+    const ctx = new WgpuExecutionContext(await setupGPU());
+    try {
+      const input = ctx.tensor('float32', [1, 32, 8, 8]);
+      const weight = ctx.tensor('float32', [32, 32, 1, 1]);
+      const output = ctx.tensor('float32', [1, 32, 8, 8]);
+      expect(
+        recordHfMatrix(ctx, [
+          input,
+          weight,
+          undefined,
+          [1, 1],
+          [0, 0],
+          [1, 1],
+          false,
+          [0, 0],
+          1,
+          output,
+        ])
+      ).toBe(false);
+    } finally {
+      ctx.destroy();
+    }
+  });
+  for (const dtype of ['float32', 'float16'] as const)
+    for (const rows of [64, 32] as const)
+      for (const c of cases.filter((c) => rows === 64 || c.kernel === 3))
+        it(`${dtype} m${rows} ${JSON.stringify(c)}`, async () => {
+          const device = await setupGPU();
+          device.pushErrorScope('validation');
+          const ctx = new WgpuExecutionContext(device);
+          const array = dtype === 'float16' ? Float16Array : Float32Array;
+          const fill = (length: number) =>
+            new array(Array.from({ length }, (unused, i) => (((i * 7) % 13) - 6) / 16));
+          const oh = Math.floor((c.h + 2 * c.pad - c.dilation * (c.kernel - 1) - 1) / c.stride) + 1;
+          const ow = Math.floor((c.w + 2 * c.pad - c.dilation * (c.kernel - 1) - 1) / c.stride) + 1;
+          const input = fill(c.batch * c.ic * c.h * c.w);
+          const weight = fill(c.oc * c.ic * c.kernel * c.kernel);
+          const bias = fill(c.oc);
+          const expected: number[] = [];
+          for (let b = 0; b < c.batch; b++)
+            for (let oc = 0; oc < c.oc; oc++)
+              for (let y = 0; y < oh; y++)
+                for (let x = 0; x < ow; x++) {
+                  let sum = c.bias ? bias[oc] : 0;
+                  for (let ic = 0; ic < c.ic; ic++)
+                    for (let ky = 0; ky < c.kernel; ky++)
+                      for (let kx = 0; kx < c.kernel; kx++) {
+                        const iy = y * c.stride - c.pad + ky * c.dilation;
+                        const ix = x * c.stride - c.pad + kx * c.dilation;
+                        if (iy >= 0 && iy < c.h && ix >= 0 && ix < c.w)
+                          sum +=
+                            input[((b * c.ic + ic) * c.h + iy) * c.w + ix] *
+                            weight[((oc * c.ic + ic) * c.kernel + ky) * c.kernel + kx];
+                      }
+                  expected.push(sum);
+                }
+          try {
+            const x = ctx.tensor(dtype, [c.batch, c.ic, c.h, c.w]).setData(input);
+            const w = ctx.tensor(dtype, [c.oc, c.ic, c.kernel, c.kernel]).setData(weight);
+            const b = c.bias ? ctx.tensor(dtype, [c.oc]).setData(bias) : undefined;
+            const out = ctx
+              .tensor(dtype, [c.batch, c.oc, oh, ow])
+              .setData(new array(c.batch * c.oc * oh * ow).fill(NaN));
+            expect(
+              recordHfConvolution(
+                ctx,
+                [
+                  x,
+                  w,
+                  b,
+                  [c.stride, c.stride],
+                  [c.pad, c.pad],
+                  [c.dilation, c.dilation],
+                  false,
+                  [0, 0],
+                  1,
+                  out,
+                ],
+                'both',
+                rows
+              )
+            ).toBe(true);
+            ctx.submit();
+            await ctx.sync();
+            await expectTensorClose(out, Array.from(new array(expected)), 1e-5);
+            const error = await device.popErrorScope();
+            if (error) throw new Error(error.message);
+          } finally {
+            ctx.destroy();
+          }
+        });
+});
diff --git a/tests/shaders/tiled-convolution.test.ts b/tests/shaders/tiled-convolution.test.ts
new file mode 100644
index 0000000..18b53b1
--- /dev/null
+++ b/tests/shaders/tiled-convolution.test.ts
@@ -0,0 +1,289 @@
+import { describe, it } from 'vitest';
+import { WgpuExecutionContext, shaders } from '../../src';
+import { expectTensorClose, setupGPU } from '../helpers';
+
+// Exercise all tile heights, NCHW batches, spatial/channel tails, rectangular
+// kernels, stride and dilation. Small dyadic values make a precise CPU oracle.
+const cases = [
+  {
+    batch: 2,
+    ic: 4,
+    oc: 12,
+    h: 9,
+    w: 11,
+    kh: 2,
+    kw: 3,
+    stride: [1, 1],
+    pad: [1, 1],
+    dilation: [1, 1],
+    bias: true,
+  },
+  {
+    batch: 2,
+    ic: 4,
+    oc: 48,
+    h: 11,
+    w: 13,
+    kh: 3,
+    kw: 2,
+    stride: [2, 1],
+    pad: [1, 0],
+    dilation: [2, 2],
+    bias: false,
+  },
+  {
+    batch: 1,
+    ic: 8,
+    oc: 16,
+    h: 9,
+    w: 9,
+    kh: 1,
+    kw: 3,
+    stride: [1, 1],
+    pad: [0, 1],
+    dilation: [1, 1],
+    bias: true,
+  },
+  // Large enough spatial grids select the narrow tile, including tails,
+  // multiple NCHW batches, stride/dilation and an all-border input.
+  {
+    batch: 2,
+    ic: 4,
+    oc: 13,
+    h: 67,
+    w: 131,
+    kh: 3,
+    kw: 3,
+    stride: [2, 2],
+    pad: [2, 2],
+    dilation: [2, 2],
+    bias: true,
+  },
+  {
+    batch: 1,
+    ic: 4,
+    oc: 8,
+    h: 65,
+    w: 65,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [1, 1],
+    dilation: [1, 1],
+    bias: false,
+  },
+  {
+    batch: 1,
+    ic: 4,
+    oc: 16,
+    h: 1,
+    w: 4097,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [1, 1],
+    dilation: [1, 1],
+    bias: false,
+  },
+  // Small-grid fallbacks: channel tails, dilation, stride and batch crossings.
+  {
+    batch: 2,
+    ic: 4,
+    oc: 13,
+    h: 11,
+    w: 17,
+    kh: 3,
+    kw: 3,
+    stride: [2, 1],
+    pad: [2, 2],
+    dilation: [2, 2],
+    bias: true,
+  },
+  {
+    batch: 1,
+    ic: 8,
+    oc: 8,
+    h: 9,
+    w: 11,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [1, 1],
+    dilation: [1, 1],
+    bias: false,
+  },
+  // Just above the narrow range must keep the 32-row fallback.
+  {
+    batch: 1,
+    ic: 4,
+    oc: 17,
+    h: 9,
+    w: 11,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [1, 1],
+    dilation: [1, 1],
+    bias: true,
+  },
+  // 3x3: interior and border gathers, row/batch crossings, dilation/stride,
+  // channel/spatial tails, and an image with no full-height interior footprint.
+  {
+    batch: 2,
+    ic: 4,
+    oc: 12,
+    h: 9,
+    w: 11,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [1, 1],
+    dilation: [1, 1],
+    bias: true,
+  },
+  {
+    batch: 2,
+    ic: 4,
+    oc: 48,
+    h: 11,
+    w: 13,
+    kh: 3,
+    kw: 3,
+    stride: [2, 1],
+    pad: [1, 1],
+    dilation: [1, 2],
+    bias: false,
+  },
+  {
+    batch: 1,
+    ic: 4,
+    oc: 16,
+    h: 10,
+    w: 11,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [0, 0],
+    dilation: [1, 1],
+    bias: true,
+  },
+  {
+    batch: 1,
+    ic: 4,
+    oc: 48,
+    h: 5,
+    w: 16,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [2, 2],
+    dilation: [1, 1],
+    bias: true,
+  },
+  {
+    batch: 1,
+    ic: 4,
+    oc: 16,
+    h: 1,
+    w: 64,
+    kh: 3,
+    kw: 3,
+    stride: [1, 1],
+    pad: [1, 1],
+    dilation: [1, 1],
+    bias: false,
+  },
+];
+
+describe('dense convolution geometry and output indexing', () => {
+  for (const dtype of ['float32', 'float16'] as const) {
+    for (const fused of [false, true]) {
+      for (const c of cases) {
+        it(`${dtype}, clamp=${fused}, ${c.batch}x${c.ic}x${c.h}x${c.w}, kernel ${c.oc}x${c.kh}x${c.kw}`, async () => {
+          const device = await setupGPU();
+          device.pushErrorScope('validation');
+          const ctx = new WgpuExecutionContext(device);
+          const array = dtype === 'float16' ? Float16Array : Float32Array;
+          const oh =
+            Math.floor((c.h + 2 * c.pad[0] - c.dilation[0] * (c.kh - 1) - 1) / c.stride[0]) + 1;
+          const ow =
+            Math.floor((c.w + 2 * c.pad[1] - c.dilation[1] * (c.kw - 1) - 1) / c.stride[1]) + 1;
+          const input = new array(
+            Array.from(
+              { length: c.batch * c.ic * c.h * c.w },
+              (value, i) => (((i * 7) % 17) - 8) / 8
+            )
+          );
+          const weight = new array(
+            Array.from(
+              { length: c.oc * c.ic * c.kh * c.kw },
+              (value, i) => (((i * 3) % 11) - 5) / 8
+            )
+          );
+          const bias = new array(Array.from({ length: c.oc }, (value, i) => ((i % 5) - 2) / 4));
+          const expected: number[] = [];
+          for (let b = 0; b < c.batch; b++)
+            for (let oc = 0; oc < c.oc; oc++) {
+              for (let y = 0; y < oh; y++)
+                for (let x = 0; x < ow; x++) {
+                  let sum = c.bias ? bias[oc] : 0;
+                  for (let ic = 0; ic < c.ic; ic++)
+                    for (let ky = 0; ky < c.kh; ky++)
+                      for (let kx = 0; kx < c.kw; kx++) {
+                        const iy = y * c.stride[0] - c.pad[0] + ky * c.dilation[0];
+                        const ix = x * c.stride[1] - c.pad[1] + kx * c.dilation[1];
+                        if (iy >= 0 && iy < c.h && ix >= 0 && ix < c.w) {
+                          sum +=
+                            input[((b * c.ic + ic) * c.h + iy) * c.w + ix] *
+                            weight[((oc * c.ic + ic) * c.kh + ky) * c.kw + kx];
+                        }
+                      }
+                  expected.push(fused ? Math.min(1.5, Math.max(-0.5, sum)) : sum);
+                }
+            }
+          try {
+            const x = ctx.tensor(dtype, [c.batch, c.ic, c.h, c.w]).setData(input);
+            const w = ctx.tensor(dtype, [c.oc, c.ic, c.kh, c.kw]).setData(weight);
+            const b = c.bias ? ctx.tensor(dtype, [c.oc]).setData(bias) : undefined;
+            const out = ctx.tensor(dtype, [c.batch, c.oc, oh, ow]);
+            if (fused)
+              ctx.recordShader(shaders.convWithClamp, [
+                x,
+                w,
+                b,
+                c.stride,
+                c.pad,
+                c.dilation,
+                false,
+                [0, 0],
+                1,
+                -0.5,
+                1.5,
+                out,
+              ]);
+            else
+              ctx.recordShader(shaders.convolution, [
+                x,
+                w,
+                b,
+                c.stride,
+                c.pad,
+                c.dilation,
+                false,
+                [0, 0],
+                1,
+                out,
+              ]);
+            ctx.submit();
+            await ctx.sync();
+            await expectTensorClose(out, expected, dtype === 'float16' ? 0.02 : 1e-5);
+            const error = await device.popErrorScope();
+            if (error) throw error;
+          } finally {
+            ctx.destroy();
+          }
+        });
+      }
+    }
+  }
+});
diff --git a/tests/shaders/tiled-matrix.test.ts b/tests/shaders/tiled-matrix.test.ts
new file mode 100644
index 0000000..6411287
--- /dev/null
+++ b/tests/shaders/tiled-matrix.test.ts
@@ -0,0 +1,51 @@
+import { describe, it } from 'vitest';
+import { WgpuExecutionContext, shaders } from '../../src';
+import { expectTensorClose, setupGPU } from '../helpers';
+
+describe('rectangular and batched matrix multiplication', () => {
+  for (const dtype of ['float32', 'float16'] as const) {
+    for (const [batch, m, k, n] of [
+      [1, 65, 68, 100],
+      [2, 67, 400, 76],
+      [2, 33, 36, 44],
+      [1, 64, 16, 64],
+      [2, 400, 32, 400],
+      [2, 64, 400, 400],
+    ]) {
+      it(`${dtype}: [${batch},${m},${k}] x [${batch},${k},${n}]`, async () => {
+        const device = await setupGPU();
+        device.pushErrorScope('validation');
+        const ctx = new WgpuExecutionContext(device);
+        const array = dtype === 'float16' ? Float16Array : Float32Array;
+        const a = new array(
+          Array.from({ length: batch * m * k }, (value, i) => (((i * 3) % 7) - 3) / 8)
+        );
+        const b = new array(
+          Array.from({ length: batch * k * n }, (value, i) => (((i * 7) % 5) - 2) / 8)
+        );
+        const expected: number[] = [];
+        for (let z = 0; z < batch; z++)
+          for (let row = 0; row < m; row++)
+            for (let col = 0; col < n; col++) {
+              let sum = 0;
+              for (let inner = 0; inner < k; inner++)
+                sum += a[(z * m + row) * k + inner] * b[(z * k + inner) * n + col];
+              expected.push(sum);
+            }
+        try {
+          const x = ctx.tensor(dtype, batch === 1 ? [m, k] : [batch, m, k]).setData(a);
+          const y = ctx.tensor(dtype, batch === 1 ? [k, n] : [batch, k, n]).setData(b);
+          const out = ctx.tensor(dtype, batch === 1 ? [m, n] : [batch, m, n]);
+          ctx.recordShader(batch === 1 ? shaders.mm : shaders.bmm, [x, y, out]);
+          ctx.submit();
+          await ctx.sync();
+          await expectTensorClose(out, expected, dtype === 'float16' ? 0.02 : 1e-5);
+          const error = await device.popErrorScope();
+          if (error) throw error;
+        } finally {
+          ctx.destroy();
+        }
+      });
+    }
+  }
+});
diff --git a/utils/benchmark/adapt-hf-conv.py b/utils/benchmark/adapt-hf-conv.py
new file mode 100644
index 0000000..1ec0ccd
--- /dev/null
+++ b/utils/benchmark/adapt-hf-conv.py
@@ -0,0 +1,76 @@
+"""Render pinned Hugging Face Conv templates for the opt-in comparison.
+
+Requires Jinja2 (generation only). Run: python utils/benchmark/adapt-hf-conv.py
+The original WGSL arithmetic, staging loops and FP32 accumulation are retained.
+Only resource declarations, optional-bias guarding and geometry constants adapt
+it to this runtime's existing NCHW buffers. No HF loader or per-frame downloads.
+"""
+from pathlib import Path
+import hashlib
+import json
+import re
+import urllib.request
+import jinja2
+
+ROOT = Path(__file__).resolve().parent / 'huggingface'
+REVISION = '7b19a1ea4fd2abef3203991ca933405f12cfcc62'
+FILE = 'conv-1x1-gemm-tiled-reg.wgsl.jinja'
+URL = f'https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/{REVISION}/build/webgpu/{FILE}'
+ROOT.mkdir(exist_ok=True)
+source = urllib.request.urlopen(URL).read()
+assert hashlib.sha256(source).hexdigest() == '7eacb50256ee91107af84b0fe0d4fc22c05b880616b7113ba3ccfced037b9c72'
+(ROOT / FILE).write_bytes(source)
+(ROOT / 'metadata.json').write_bytes(urllib.request.urlopen(URL.rsplit('/', 1)[0] + '/metadata.json').read())
+(ROOT / 'LICENSE').write_bytes(urllib.request.urlopen('https://www.apache.org/licenses/LICENSE-2.0.txt').read())
+(ROOT / 'NOTICE').write_text(f'''Hugging Face WebGPU Conv adaptation
+Upstream: webgpu-kernels/ai.onnx.Conv
+Revision: {REVISION}
+Source: {URL}
+Upstream shader: Apache-2.0 (see LICENSE and upstream metadata.json).
+Integration code: MIT, https://github.com/barhanc/wgpu-executorch
+Changes: bind existing buffers; guard optional bias via uniform; expose shape
+geometry as pipeline constants. Shader load/compute/store loops are retained.
+Generated variants use published 64x64/32x64, 8x4-per-thread register layouts,
+K=16/32 and carried implicit gathering (IMPLICIT_TILED_GATHER_MODE=1), no split-K or activation/residual fusion. This is not the entire HF
+loader or route-selection policy. The separately rendered subgroup-matrix
+adaptation is from conv-1x1-subgroup-matrix.wgsl.jinja at the same revision:
+aligned 1x1 and implicit 3x3, f32 accumulation, 8x8 hardware matrices,
+32/64-row output tiles, 32-lane subgroups; no split-K or fused activation.
+Original WGSL templates are included unmodified; metadata JSON is reformatted. Generated derivatives
+change bindings, optional-bias guarding and literal shapes into pipeline constants.
+Manifest: https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/{REVISION}/build/webgpu/manifest.json
+''')
+template = jinja2.Environment(undefined=jinja2.StrictUndefined).from_string(source.decode())
+variants = {}
+for half in [False, True]:
+    scalar = 'f16' if half else 'f32'
+    declarations = ('enable f16;\n' if half else '') + f'''
+@group(0) @binding(0) var<storage, read_write> y: array<{scalar}>;
+@group(0) @binding(1) var<storage, read> xm: array<{scalar}>;
+@group(0) @binding(2) var<storage, read> w: array<{scalar}>;
+@group(0) @binding(3) var<storage, read> bias: array<{scalar}>;
+struct Params {{ M: u32, K: u32, N: u32, has_bias: u32 }}
+@group(0) @binding(4) var<uniform> params: Params;
+'''
+    for implicit in [False, True]:
+        for rows in ([64, 32] if implicit else [64]):
+            for reduction in [16, 32]:
+                code = template.render(env={'wgsl': {'resourceDeclarations': declarations}},
+                    T=scalar, usesF16=half, hasBias=True, implicitIm2col=implicit,
+                    tunables={'IMPLICIT_TILED_GATHER_MODE': 1}, gemmKTile=reduction, gemmMTile=rows, gemmThreadRows=8,
+                    convKernelH=3, convKernelW=3, convStrideH=1, convStrideW=1,
+                    convDilationH=1, convDilationW=1, convPadTop=1, convPadLeft=1,
+                    convInH=1, convInW=1, convOutW=1, convInChannels=1)
+                assert code.count('v = v + f32(bias[m]);') == 1
+                code = code.replace('v = v + f32(bias[m]);',
+                    'if (params.has_bias != 0u) { v = v + f32(bias[m]); }')
+                if implicit:
+                    for name in ['STRIDE_H', 'STRIDE_W', 'DILATION_H', 'DILATION_W',
+                                 'PAD_TOP', 'PAD_LEFT', 'IN_H', 'IN_W', 'OUT_W', 'IN_CHANNELS']:
+                        code, count = re.subn(rf'const CONV_{name}:', f'override CONV_{name}:', code)
+                        assert count == 1
+                header = f'// Adapted from {URL}\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n'
+                variants[f'{"3x3" if implicit else "1x1"}-{scalar}-k{reduction}-m{rows}'] = header + code
+(ROOT / 'conv-variants.json').write_text(json.dumps({'upstream': URL, 'revision': REVISION,
+    'sha256': hashlib.sha256(source).hexdigest(), 'variants': variants}, indent=2) + '\n')
+print(f'Rendered {len(variants)} variants from {REVISION}')
diff --git a/utils/benchmark/adapt-hf-matrix.py b/utils/benchmark/adapt-hf-matrix.py
new file mode 100644
index 0000000..eedb70a
--- /dev/null
+++ b/utils/benchmark/adapt-hf-matrix.py
@@ -0,0 +1,57 @@
+"""Render HF's aligned 1x1 and implicit 3x3 subgroup-matrix route. Requires Jinja2 for generation."""
+from pathlib import Path
+import hashlib
+import json
+import re
+import urllib.request
+import jinja2
+
+ROOT = Path(__file__).resolve().parent / 'huggingface'
+REVISION = '7b19a1ea4fd2abef3203991ca933405f12cfcc62'
+FILE = 'conv-1x1-subgroup-matrix.wgsl.jinja'
+URL = f'https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/{REVISION}/build/webgpu/{FILE}'
+source = urllib.request.urlopen(URL).read()
+assert hashlib.sha256(source).hexdigest() == 'fccfc351a2c3936ac10a88cbc62798431421a4c7a2efd9afe22334b21c096e5f'
+(ROOT / FILE).write_bytes(source)
+template = jinja2.Environment(undefined=jinja2.StrictUndefined).from_string(source.decode())
+variants = {}
+for half in [False, True]:
+    scalar = 'f16' if half else 'f32'
+    for implicit in [False, True]:
+        for direct in [False, True]:
+            rows = 64 if not half and direct else 32
+            declarations = ('enable f16;\n' if half else '') + f'''
+    @group(0) @binding(0) var<storage, read_write> y: array<{scalar}>;
+    @group(0) @binding(1) var<storage, read> xm: array<{scalar}>;
+    @group(0) @binding(2) var<storage, read> w: array<{scalar}>;
+    @group(0) @binding(3) var<storage, read> bias: array<{scalar}>;
+    struct Params {{ has_bias: u32 }}
+    @group(0) @binding(4) var<uniform> params: Params;
+    '''
+            code = template.render(env={'wgsl': {'resourceDeclarations': declarations}},
+                T=scalar, usesF16=half, fScalar=scalar, hasBias=True, padded=implicit, implicitIm2col=implicit, kPadded=32,
+                convKernelH=3, convKernelW=3, convStrideH=1, convStrideW=1,
+                convDilationH=1, convDilationW=1, convPadTop=1, convPadLeft=1,
+                convInH=1, convInW=1, convOutW=1, convInChannels=1,
+                pinSubgroupSize32=True, directMatrixInputs=direct and not implicit,
+                directMatrixStore=not half and direct, tileRows=rows,
+                workgroupThreads=256 if rows == 64 else 128,
+                subgroupRows=4 if rows == 64 else 2, M=1, K=32, N=64)
+            code = code.replace('let bv = f32(bias[row_base + row]);',
+                'var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }')
+            code = code.replace('raw += f32(bias[global_row]);',
+                'if (params.has_bias != 0u) { raw += f32(bias[global_row]); }')
+            for name in ['M', 'K', 'N', 'B_BATCH_STRIDE', 'C_BATCH_STRIDE']:
+                code, count = re.subn(rf'const {name}:', f'override {name}:', code)
+                assert count == 1
+            if implicit:
+                for name in ['K_LOOP', 'CONV_STRIDE_H', 'CONV_STRIDE_W', 'CONV_DILATION_H', 'CONV_DILATION_W', 'CONV_PAD_TOP', 'CONV_PAD_LEFT', 'CONV_IN_H', 'CONV_IN_W', 'CONV_OUT_W']:
+                    code, count = re.subn(rf'const {name}:', f'override {name}:', code)
+                    assert count == 1
+                code = code.replace('1u * u32(CONV_IN_H)', 'CONV_IN_CHANNELS * u32(CONV_IN_H)')
+                code = code.replace('override M:', 'override CONV_IN_CHANNELS: u32 = 1u;\noverride M:')
+            header = f'// Adapted from {URL}\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n'
+            variants[f'{"3x3" if implicit else "1x1"}-{scalar}-{"direct" if direct else "shared"}'] = header + code
+(ROOT / 'matrix-variants.json').write_text(json.dumps({'upstream': URL, 'revision': REVISION,
+    'sha256': hashlib.sha256(source).hexdigest(), 'variants': variants}, indent=2) + '\n')
+print(f'Rendered {len(variants)} subgroup-matrix variants')
diff --git a/utils/benchmark/conv-mm-results.json b/utils/benchmark/conv-mm-results.json
new file mode 100644
index 0000000..62b4e4a
--- /dev/null
+++ b/utils/benchmark/conv-mm-results.json
@@ -0,0 +1,828 @@
+{
+  "baseline": "224da79",
+  "gpu": {
+    "vendor": "apple",
+    "architecture": "metal-3"
+  },
+  "method": "8\u2013512 recorded dispatches per submit, scaled by operation count; submit + await sync; 3 warmups, 11 alternating samples per version; median milliseconds per dispatch; GPU timestamps",
+  "results": [
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [1, 64, 64, 64],
+      "repeats": 512,
+      "beforeMs": 0.013184,
+      "afterMs": 0.01344,
+      "speedup": 0.9809523809523809,
+      "samples": [
+        [
+          0.01472, 0.014464, 0.01472, 0.01152, 0.012544, 0.013056, 0.012928, 0.013184, 0.013184,
+          0.013312, 0.01344
+        ],
+        [
+          0.014464, 0.014464, 0.014848, 0.01472, 0.0128, 0.012928, 0.012928, 0.013184, 0.013184,
+          0.01344, 0.01344
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [1, 256, 256, 256],
+      "repeats": 120,
+      "beforeMs": 0.049152,
+      "afterMs": 0.049152,
+      "speedup": 1,
+      "samples": [
+        [
+          0.048605866666666664, 0.049152, 0.049152, 0.048605866666666664, 0.048605866666666664,
+          0.048605866666666664, 0.049152, 0.049152, 0.049152, 0.049152, 0.048605866666666664
+        ],
+        [
+          0.049152, 0.048605866666666664, 0.049152, 0.049152, 0.048605866666666664,
+          0.048605866666666664, 0.049152, 0.049152, 0.048605866666666664, 0.049152, 0.049152
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [1, 1024, 1024, 1024],
+      "repeats": 8,
+      "beforeMs": 1.47456,
+      "afterMs": 1.47456,
+      "speedup": 1,
+      "samples": [
+        [
+          1.482752, 1.47456, 1.482752, 1.482752, 1.47456, 1.47456, 1.482752, 1.47456, 1.47456,
+          1.482752, 1.47456
+        ],
+        [
+          1.47456, 1.482752, 1.482752, 1.482752, 1.482752, 1.482752, 1.47456, 1.47456, 1.47456,
+          1.47456, 1.47456
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [1, 128, 256, 512],
+      "repeats": 120,
+      "beforeMs": 0.05024426666666667,
+      "afterMs": 0.05024426666666667,
+      "speedup": 1,
+      "samples": [
+        [
+          0.05024426666666667, 0.05024426666666667, 0.05024426666666667, 0.05024426666666667,
+          0.05024426666666667, 0.05024426666666667, 0.05024426666666667, 0.05024426666666667,
+          0.05024426666666667, 0.05024426666666667, 0.05024426666666667
+        ],
+        [
+          0.0507904, 0.05024426666666667, 0.0507904, 0.05024426666666667, 0.05024426666666667,
+          0.05024426666666667, 0.05024426666666667, 0.05024426666666667, 0.05024426666666667,
+          0.05024426666666667, 0.05024426666666667
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [1, 65, 68, 100],
+      "repeats": 512,
+      "beforeMs": 0.013568,
+      "afterMs": 0.01344,
+      "speedup": 1.0095238095238095,
+      "samples": [
+        [
+          0.014976, 0.014848, 0.013312, 0.013312, 0.01344, 0.013312, 0.01344, 0.013568, 0.013568,
+          0.013824, 0.013952
+        ],
+        [
+          0.014976, 0.014976, 0.013312, 0.013312, 0.013312, 0.01344, 0.013312, 0.01344, 0.013696,
+          0.013696, 0.013952
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [1, 33, 36, 44],
+      "repeats": 512,
+      "beforeMs": 0.0128,
+      "afterMs": 0.012544,
+      "speedup": 1.0204081632653061,
+      "samples": [
+        [
+          0.011904, 0.012032, 0.012032, 0.012416, 0.012032, 0.0128, 0.012928, 0.013184, 0.013312,
+          0.013184, 0.013312
+        ],
+        [
+          0.012032, 0.012032, 0.012032, 0.011904, 0.012544, 0.012288, 0.013056, 0.013056, 0.01344,
+          0.013184, 0.01344
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [2, 400, 32, 400],
+      "repeats": 196,
+      "beforeMs": 0.027083755102040818,
+      "afterMs": 0.027418122448979593,
+      "speedup": 0.9878048780487805,
+      "samples": [
+        [
+          0.027083755102040818, 0.027083755102040818, 0.027083755102040818, 0.027083755102040818,
+          0.027083755102040818, 0.027083755102040818, 0.027083755102040818, 0.027083755102040818,
+          0.027418122448979593, 0.027418122448979593, 0.027418122448979593
+        ],
+        [
+          0.027418122448979593, 0.027083755102040818, 0.027083755102040818, 0.027418122448979593,
+          0.027083755102040818, 0.027418122448979593, 0.027752489795918368, 0.027418122448979593,
+          0.027418122448979593, 0.027418122448979593, 0.027418122448979593
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float32",
+      "shape": [2, 64, 400, 400],
+      "repeats": 98,
+      "beforeMs": 0.07623575510204082,
+      "afterMs": 0.07623575510204082,
+      "speedup": 1,
+      "samples": [
+        [
+          0.07690448979591837, 0.07690448979591837, 0.07690448979591837, 0.07623575510204082,
+          0.07623575510204082, 0.07623575510204082, 0.07623575510204082, 0.07690448979591837,
+          0.07623575510204082, 0.07623575510204082, 0.07623575510204082
+        ],
+        [
+          0.07623575510204082, 0.07623575510204082, 0.07623575510204082, 0.07623575510204082,
+          0.07623575510204082, 0.07623575510204082, 0.07623575510204082, 0.07623575510204082,
+          0.07623575510204082, 0.07623575510204082, 0.07623575510204082
+        ]
+      ]
+    },
+    {
+      "category": "convolution",
+      "dtype": "float32",
+      "shape": [64, 64, 56, 3, 1, 1],
+      "repeats": 18,
+      "beforeMs": 0.26942577777777776,
+      "afterMs": 0.23301688888888888,
+      "speedup": 1.15625,
+      "samples": [
+        [
+          0.26942577777777776, 0.26942577777777776, 0.2730666666666666, 0.26942577777777776,
+          0.26942577777777776, 0.26942577777777776, 0.2730666666666666, 0.26942577777777776,
+          0.26942577777777776, 0.26942577777777776, 0.26942577777777776
+        ],
+        [
+          0.23301688888888888, 0.23301688888888888, 0.23665777777777774, 0.23665777777777774,
+          0.23301688888888888, 0.23665777777777774, 0.23301688888888888, 0.23301688888888888,
+          0.23301688888888888, 0.23301688888888888, 0.23665777777777774
+        ]
+      ]
+    },
+    {
+      "category": "convolution",
+      "dtype": "float32",
+      "shape": [960, 48, 14, 3, 1, 1],
+      "repeats": 25,
+      "beforeMs": 1.36839168,
+      "afterMs": 1.28188416,
+      "speedup": 1.0674846625766872,
+      "samples": [
+        [
+          1.36839168, 1.36839168, 1.36839168, 1.36839168, 1.36577024, 1.36839168, 1.36839168,
+          1.36839168, 1.37101312, 1.36577024, 1.36839168
+        ],
+        [
+          1.27926272, 1.27926272, 1.28974848, 1.28188416, 1.28188416, 1.28188416, 1.28188416,
+          1.27926272, 1.2871270400000001, 1.27926272, 1.27926272
+        ]
+      ]
+    },
+    {
+      "category": "convolution",
+      "dtype": "float32",
+      "shape": [64, 64, 80, 3, 2, 1],
+      "repeats": 34,
+      "beforeMs": 0.2313035294117647,
+      "afterMs": 0.20239058823529413,
+      "speedup": 1.1428571428571428,
+      "samples": [
+        [
+          0.2313035294117647, 0.2313035294117647, 0.2313035294117647, 0.2313035294117647,
+          0.2332310588235294, 0.2313035294117647, 0.2313035294117647, 0.2313035294117647,
+          0.2313035294117647, 0.2313035294117647, 0.2313035294117647
+        ],
+        [
+          0.20239058823529413, 0.20239058823529413, 0.20239058823529413, 0.20239058823529413,
+          0.20239058823529413, 0.20239058823529413, 0.20239058823529413, 0.20431811764705882,
+          0.20239058823529413, 0.20239058823529413, 0.20239058823529413
+        ]
+      ]
+    },
+    {
+      "category": "convolution",
+      "dtype": "float32",
+      "shape": [32, 32, 40, 3, 1, 1],
+      "repeats": 136,
+      "beforeMs": 0.07324611764705882,
+      "afterMs": 0.06601788235294118,
+      "speedup": 1.1094890510948905,
+      "samples": [
+        [
+          0.073728, 0.073728, 0.073728, 0.07324611764705882, 0.07324611764705882,
+          0.07324611764705882, 0.07324611764705882, 0.07324611764705882, 0.07324611764705882,
+          0.07324611764705882, 0.073728
+        ],
+        [
+          0.065536, 0.06601788235294118, 0.06601788235294118, 0.06601788235294118, 0.065536,
+          0.065536, 0.06601788235294118, 0.06601788235294118, 0.06601788235294118,
+          0.06601788235294118, 0.065536
+        ]
+      ]
+    },
+    {
+      "category": "convolution",
+      "dtype": "float32",
+      "shape": [24, 16, 448, 3, 1, 1],
+      "repeats": 8,
+      "beforeMs": 3.301376,
+      "afterMs": 2.981888,
+      "speedup": 1.107142857142857,
+      "samples": [
+        [
+          3.301376, 3.301376, 3.301376, 3.301376, 3.301376, 3.301376, 3.301376, 3.309568, 3.309568,
+          3.309568, 3.301376
+        ],
+        [
+          2.981888, 2.973696, 2.973696, 2.981888, 2.973696, 2.981888, 2.973696, 2.981888, 2.981888,
+          2.981888, 2.981888
+        ]
+      ]
+    },
+    {
+      "category": "convolution",
+      "dtype": "float32",
+      "shape": [8, 12, 17, 2, 1, 0],
+      "repeats": 512,
+      "beforeMs": 0.01408,
+      "afterMs": 0.011776,
+      "speedup": 1.1956521739130435,
+      "samples": [
+        [
+          0.01216, 0.01408, 0.01408, 0.01408, 0.014336, 0.01408, 0.014592, 0.012672, 0.0128, 0.0128,
+          0.012928
+        ],
+        [
+          0.011776, 0.01216, 0.012288, 0.012288, 0.012672, 0.012672, 0.010368, 0.01088, 0.011008,
+          0.011008, 0.010624
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float32",
+      "shape": [64, 64, 56, 3, 1, 1],
+      "repeats": 18,
+      "beforeMs": 0.26942577777777776,
+      "afterMs": 0.23665777777777774,
+      "speedup": 1.1384615384615386,
+      "samples": [
+        [
+          0.26942577777777776, 0.26942577777777776, 0.26942577777777776, 0.26942577777777776,
+          0.2730666666666666, 0.2730666666666666, 0.26942577777777776, 0.26942577777777776,
+          0.26942577777777776, 0.26942577777777776, 0.2730666666666666
+        ],
+        [
+          0.23665777777777774, 0.23665777777777774, 0.23665777777777774, 0.23301688888888888,
+          0.23301688888888888, 0.23665777777777774, 0.23301688888888888, 0.23301688888888888,
+          0.23665777777777774, 0.23301688888888888, 0.23665777777777774
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float32",
+      "shape": [960, 48, 14, 3, 1, 1],
+      "repeats": 25,
+      "beforeMs": 1.37101312,
+      "afterMs": 1.28188416,
+      "speedup": 1.0695296523517384,
+      "samples": [
+        [
+          1.37101312, 1.3867417599999998, 1.36839168, 1.37101312, 1.36839168, 1.37101312,
+          1.37101312, 1.39984896, 1.43654912, 1.4155776, 1.37101312
+        ],
+        [
+          1.28188416, 1.29499136, 1.28188416, 1.28188416, 1.27926272, 1.28188416, 1.28188416,
+          1.27926272, 1.30547712, 1.36839168, 1.27926272
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float32",
+      "shape": [64, 64, 80, 3, 2, 1],
+      "repeats": 34,
+      "beforeMs": 0.2332310588235294,
+      "afterMs": 0.20239058823529413,
+      "speedup": 1.1523809523809523,
+      "samples": [
+        [
+          0.2332310588235294, 0.23515858823529412, 0.2332310588235294, 0.2313035294117647,
+          0.2313035294117647, 0.2332310588235294, 0.2313035294117647, 0.2332310588235294,
+          0.2332310588235294, 0.2313035294117647, 0.2313035294117647
+        ],
+        [
+          0.20239058823529413, 0.20239058823529413, 0.20239058823529413, 0.20431811764705882,
+          0.20239058823529413, 0.20239058823529413, 0.20239058823529413, 0.20239058823529413,
+          0.20239058823529413, 0.20239058823529413, 0.20239058823529413
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float32",
+      "shape": [32, 32, 40, 3, 1, 1],
+      "repeats": 136,
+      "beforeMs": 0.08577505882352941,
+      "afterMs": 0.07035482352941176,
+      "speedup": 1.2191780821917808,
+      "samples": [
+        [
+          0.08577505882352941, 0.08577505882352941, 0.08577505882352941, 0.08577505882352941,
+          0.08577505882352941, 0.08577505882352941, 0.08577505882352941, 0.08577505882352941,
+          0.08577505882352941, 0.08529317647058823, 0.08577505882352941
+        ],
+        [
+          0.06987294117647058, 0.06987294117647058, 0.06987294117647058, 0.07035482352941176,
+          0.07035482352941176, 0.07035482352941176, 0.06987294117647058, 0.07035482352941176,
+          0.07035482352941176, 0.06987294117647058, 0.07035482352941176
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float32",
+      "shape": [24, 16, 448, 3, 1, 1],
+      "repeats": 8,
+      "beforeMs": 3.678208,
+      "afterMs": 3.145728,
+      "speedup": 1.1692708333333333,
+      "samples": [
+        [
+          3.694592, 3.6864, 3.678208, 3.670016, 3.670016, 3.670016, 3.670016, 3.678208, 3.670016,
+          3.678208, 3.678208
+        ],
+        [
+          3.15392, 3.162112, 3.145728, 3.162112, 3.145728, 3.145728, 3.15392, 3.15392, 3.137536,
+          3.145728, 3.145728
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float32",
+      "shape": [8, 12, 17, 2, 1, 0],
+      "repeats": 512,
+      "beforeMs": 0.021632,
+      "afterMs": 0.011648,
+      "speedup": 1.857142857142857,
+      "samples": [
+        [
+          0.021632, 0.021632, 0.021504, 0.021632, 0.021504, 0.021632, 0.021632, 0.021504, 0.021504,
+          0.021632, 0.021632
+        ],
+        [
+          0.011648, 0.01152, 0.01152, 0.01152, 0.011648, 0.011648, 0.011904, 0.011648, 0.01152,
+          0.01152, 0.011776
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float16",
+      "shape": [1, 64, 64, 64],
+      "repeats": 512,
+      "beforeMs": 0.013696,
+      "afterMs": 0.013568,
+      "speedup": 1.0094339622641508,
+      "samples": [
+        [
+          0.01344, 0.013312, 0.013568, 0.013696, 0.013696, 0.01344, 0.013568, 0.013824, 0.013824,
+          0.014464, 0.01472
+        ],
+        [
+          0.013312, 0.013312, 0.013568, 0.01344, 0.013312, 0.013568, 0.013568, 0.013568, 0.01408,
+          0.014208, 0.014848
+        ]
+      ]
+    },
+    {
+      "category": "matrix",
+      "dtype": "float16",
+      "shape": [1, 256, 256, 256],
+      "repeats": 120,
+      "beforeMs": 0.03713706666666667,
+      "afterMs": 0.03713706666666667,
+      "speedup": 1,
+      "samples": [
+        [
+          0.03713706666666667, 0.03713706666666667, 0.0376832, 0.0376832, 0.0376832, 0.0376832,
+          0.03713706666666667, 0.03713706666666667, 0.03713706666666667, 0.03713706666666667,
+          0.0376832
+        ],
+        [
+          0.03713706666666667, 0.03713706666666667, 0.03713706666666667, 0.0376832,
+          0.03713706666666667, 0.03713706666666667, 0.03713706666666667, 0.03713706666666667,
+          0.0376832, 0.03713706666666667, 0.03713706666666667
+        ]
+      ]
+    },
+    {
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+          0.966656, 0.966656
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+          0.06085485714285715, 0.06085485714285715, 0.06085485714285715
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+          0.22209422222222222, 0.21845333333333333, 0.21845333333333333
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+          0.18204444444444445, 0.18568533333333334, 0.18568533333333334
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+      ]
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+    {
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+          1.16391936, 1.1665408, 1.16391936, 1.1665408
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+          1.0800332799999999, 1.0800332799999999
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+    {
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+          0.1272169411764706, 0.1272169411764706, 0.1272169411764706
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+          0.065536, 0.065536, 0.065536, 0.06601788235294118, 0.06601788235294118
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+          0.05782588235294118, 0.05830776470588235, 0.05782588235294118
+        ]
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+    {
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+          2.449408, 2.449408, 2.449408, 2.449408, 2.449408, 2.449408, 2.449408, 2.441216, 2.449408,
+          2.449408, 2.449408
+        ],
+        [
+          2.015232, 2.015232, 2.015232, 2.00704, 2.015232, 2.015232, 2.015232, 2.023424, 2.015232,
+          2.00704, 2.00704
+        ]
+      ]
+    },
+    {
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+      "dtype": "float16",
+      "shape": [8, 12, 17, 2, 1, 0],
+      "repeats": 512,
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+          0.014592, 0.014592, 0.014848, 0.01472, 0.014976, 0.015104, 0.01152, 0.013184, 0.013184,
+          0.012288, 0.012544
+        ],
+        [
+          0.011904, 0.011904, 0.012032, 0.01216, 0.011904, 0.01216, 0.010752, 0.01088, 0.010368,
+          0.0096, 0.010368
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float16",
+      "shape": [64, 64, 56, 3, 1, 1],
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+        [
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+          0.21845333333333333, 0.21845333333333333, 0.22209422222222222
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+          0.18568533333333334, 0.18568533333333334, 0.18568533333333334, 0.18568533333333334,
+          0.18204444444444445, 0.18568533333333334, 0.18568533333333334
+        ]
+      ]
+    },
+    {
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+          1.179648, 1.17440512, 1.16916224, 1.18489088
+        ],
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+          1.11673344, 1.09051904, 1.09051904, 1.1010048000000001, 1.08265472, 1.08527616,
+          1.0957619200000002, 1.0957619200000002, 1.0878976, 1.08527616, 1.08527616
+        ]
+      ]
+    },
+    {
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+          0.15227482352941177, 0.15420235294117648, 0.15998494117647058, 0.15420235294117648,
+          0.15420235294117648, 0.15420235294117648, 0.15420235294117648
+        ],
+        [
+          0.1272169411764706, 0.1291444705882353, 0.1272169411764706, 0.1272169411764706,
+          0.1291444705882353, 0.1291444705882353, 0.1272169411764706, 0.1291444705882353,
+          0.1291444705882353, 0.1291444705882353, 0.1272169411764706
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float16",
+      "shape": [32, 32, 40, 3, 1, 1],
+      "repeats": 136,
+      "beforeMs": 0.07758305882352942,
+      "afterMs": 0.06312658823529413,
+      "speedup": 1.2290076335877862,
+      "samples": [
+        [
+          0.07710117647058824, 0.07758305882352942, 0.07758305882352942, 0.07758305882352942,
+          0.08240188235294119, 0.07806494117647059, 0.07710117647058824, 0.07758305882352942,
+          0.07710117647058824, 0.07758305882352942, 0.07758305882352942
+        ],
+        [
+          0.06312658823529413, 0.06264470588235294, 0.06457223529411765, 0.0636084705882353,
+          0.06312658823529413, 0.06312658823529413, 0.06312658823529413, 0.06312658823529413,
+          0.06312658823529413, 0.06264470588235294, 0.06312658823529413
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float16",
+      "shape": [24, 16, 448, 3, 1, 1],
+      "repeats": 8,
+      "beforeMs": 2.711552,
+      "afterMs": 2.203648,
+      "speedup": 1.2304832713754648,
+      "samples": [
+        [
+          2.711552, 2.711552, 2.711552, 2.711552, 2.719744, 2.70336, 2.711552, 2.711552, 2.719744,
+          2.711552, 2.711552
+        ],
+        [
+          2.195456, 2.195456, 2.203648, 2.195456, 2.195456, 2.203648, 2.203648, 2.203648, 2.195456,
+          2.203648, 2.203648
+        ]
+      ]
+    },
+    {
+      "category": "clamp",
+      "dtype": "float16",
+      "shape": [8, 12, 17, 2, 1, 0],
+      "repeats": 512,
+      "beforeMs": 0.020608,
+      "afterMs": 0.011136,
+      "speedup": 1.8505747126436782,
+      "samples": [
+        [
+          0.020608, 0.020608, 0.020736, 0.02048, 0.02048, 0.02048, 0.02048, 0.020608, 0.020608,
+          0.02048, 0.020608
+        ],
+        [
+          0.011136, 0.011136, 0.011008, 0.011008, 0.011264, 0.011008, 0.011136, 0.011008, 0.011648,
+          0.01152, 0.011008
+        ]
+      ]
+    }
+  ],
+  "date": "2026-10-21",
+  "scope": "One Apple Metal GPU; local evidence only. Kernels use geometry constants and index reuse without vendor checks or changed tile sizes. Cross-vendor validation remains to be collected.",
+  "changes": [
+    "Specialize dense-convolution kernel height/width through pipeline overrides with uniform-driven raw-template fallback.",
+    "Reuse decoded NCHW batch coordinates in output stores, including the Tile32 batched-output correction."
+  ],
+  "matrixExperimentsNotRetained": [
+    "Explicit vector FMA chains",
+    "Wider 32-element K tiles",
+    "128-thread 8x4 register tiles",
+    "Compile-time matrix reduction size"
+  ],
+  "matrixConclusion": "No consistent local benefit in the candidate comparisons. MM/BMM shader sources and dispatch selection remain unchanged; matrix rows here are unchanged-kernel timing controls.",
+  "validation": {
+    "testFiles": 30,
+    "correctnessTests": 142,
+    "optInBenchmark": "tests/bench-kernels.test.ts",
+    "chromeBenchmarkCases": 27,
+    "cases": "CPU convolution references cover FP32/FP16, batches, both tile heights, spatial/channel tails, rectangular kernels, stride and dilation. Matrix references include the actual YOLO attention shapes."
+  }
+}
diff --git a/utils/benchmark/hf-convolution.ts b/utils/benchmark/hf-convolution.ts
new file mode 100644
index 0000000..6413a74
--- /dev/null
+++ b/utils/benchmark/hf-convolution.ts
@@ -0,0 +1,91 @@
+/**
+ * Experimental Hugging Face Conv adapter for kernel/model comparisons.
+ * Integration: MIT, https://github.com/barhanc/wgpu-executorch
+ * Generated shader: Apache-2.0; provenance and license in ./huggingface/NOTICE.
+ * This is opt-in benchmark code, not part of the default shader registry.
+ */
+import type { WgpuExecutionContext } from '../../src';
+import { createComputeBundle } from '../../src';
+import type { ConvolutionArgs } from '../../src/shaders/convolution';
+import generatedJson from './huggingface/conv-variants.json?raw';
+
+const generated = JSON.parse(generatedJson) as { variants: Record<string, string> };
+
+export type HfConvRoute = '1x1' | '3x3' | 'both';
+
+/**
+ * Record a supported dense convolution using the published HF register tile.
+ *
+ * @param ctx Context owning the recorded commands.
+ * @param args Existing convolution arguments; no tensor copies are introduced.
+ * @param route Which adapted template to enable.
+ * @param implicitRows Published implicit-convolution output tile height.
+ * @returns Whether this operator was recorded; false means use the usual fallback.
+ */
+export function recordHfConvolution(
+  ctx: WgpuExecutionContext,
+  args: ConvolutionArgs,
+  route: HfConvRoute = 'both',
+  implicitRows: 32 | 64 = 64
+): boolean {
+  const [input, weight, bias, stride, padding, dilation, transposed, , groups, output] = args;
+  if (transposed || groups !== 1 || input.shape.length !== 4 || weight.shape.length !== 4)
+    return false;
+  if (input.dtype !== 'float32' && input.dtype !== 'float16') return false;
+  const [batch, ic, ih, iw] = input.shape;
+  const [oc, , kh, kw] = weight.shape;
+  const [, , oh, ow] = output.shape;
+  const sh = stride[0],
+    sw = stride[1] ?? sh;
+  const ph = padding[0],
+    pw = padding[1] ?? ph;
+  const dh = dilation[0],
+    dw = dilation[1] ?? dh;
+  const pointwise =
+    kh === 1 && kw === 1 && sh === 1 && sw === 1 && ph === 0 && pw === 0 && dh === 1 && dw === 1;
+  const dense3x3 = kh === 3 && kw === 3;
+  if ((!pointwise || route === '3x3') && (!dense3x3 || route === '1x1')) return false;
+  const reduction = ic * kh * kw;
+  const tileK = reduction % 32 === 0 ? 32 : 16;
+  const scalar = input.dtype === 'float16' ? 'f16' : 'f32';
+  const rows = pointwise ? 64 : implicitRows;
+  const key =
+    `${pointwise ? '1x1' : '3x3'}-${scalar}-k${tileK}-m${rows}` as keyof typeof generated.variants;
+  /* eslint-disable @typescript-eslint/naming-convention -- Upstream WGSL names */
+  const constants: Record<string, number> = pointwise
+    ? {}
+    : {
+        CONV_STRIDE_H: sh,
+        CONV_STRIDE_W: sw,
+        CONV_DILATION_H: dh,
+        CONV_DILATION_W: dw,
+        CONV_PAD_TOP: ph,
+        CONV_PAD_LEFT: pw,
+        CONV_IN_H: ih,
+        CONV_IN_W: iw,
+        CONV_OUT_W: ow,
+        CONV_IN_CHANNELS: ic,
+      };
+  /* eslint-enable @typescript-eslint/naming-convention */
+  const params = ctx.uniformBuffer(new Uint32Array([oc, reduction, oh * ow, bias ? 1 : 0]));
+  const bundle = createComputeBundle(
+    ctx.device,
+    generated.variants[key],
+    [
+      { binding: 0, buffer: output.buffer },
+      { binding: 1, buffer: input.buffer },
+      { binding: 2, buffer: weight.buffer },
+      { binding: 3, buffer: bias?.buffer ?? weight.buffer },
+      { binding: 4, buffer: params },
+    ],
+    constants
+  );
+  ctx.addDispatch({
+    pipeline: bundle.pipeline,
+    bindGroup: bundle.bindGroup,
+    workgroupCountX: Math.ceil((oh * ow) / 64),
+    workgroupCountY: Math.ceil(oc / rows),
+    workgroupCountZ: batch,
+  });
+  return true;
+}
diff --git a/utils/benchmark/hf-matrix.ts b/utils/benchmark/hf-matrix.ts
new file mode 100644
index 0000000..51c81d7
--- /dev/null
+++ b/utils/benchmark/hf-matrix.ts
@@ -0,0 +1,96 @@
+/**
+ * Opt-in adapter of HF's experimental aligned 1x1 and implicit 3x3 subgroup-matrix Conv.
+ * Integration MIT, https://github.com/barhanc/wgpu-executorch
+ * Upstream shader Apache-2.0: ./huggingface/NOTICE and LICENSE.
+ */
+import type { WgpuExecutionContext } from '../../src';
+import { createComputeBundle } from '../../src';
+import type { ConvolutionArgs } from '../../src/shaders/convolution';
+import generatedJson from './huggingface/matrix-variants.json?raw';
+
+const generated = JSON.parse(generatedJson) as { variants: Record<string, string> };
+
+/**
+ * Record the published aligned matrix route, falling back for unsupported shapes/devices.
+ *
+ * @param ctx Context with experimental matrix and subgroup-size features enabled.
+ * @param args Standard convolution arguments on existing buffers.
+ * @returns Whether a matrix dispatch was recorded.
+ */
+export function recordHfMatrix(ctx: WgpuExecutionContext, args: ConvolutionArgs): boolean {
+  const [input, weight, bias, stride, padding, dilation, transposed, , groups, output] = args;
+  if (transposed || groups !== 1 || input.shape.length !== 4 || weight.shape.length !== 4)
+    return false;
+  if (input.dtype !== 'float32' && input.dtype !== 'float16') return false;
+  const features = ctx.device.features as unknown as Set<string>;
+  if (
+    !['subgroups', 'subgroup-size-control', 'chromium-experimental-subgroup-matrix'].every((name) =>
+      features.has(name)
+    )
+  )
+    return false;
+  const [batch, ic, ih, iw] = input.shape;
+  const [oc, , kh, kw] = weight.shape;
+  const implicit = kh === 3 && kw === 3;
+  if (
+    !implicit &&
+    (kh !== 1 ||
+      kw !== 1 ||
+      stride.some((v) => v !== 1) ||
+      padding.some((v) => v !== 0) ||
+      dilation.some((v) => v !== 1))
+  )
+    return false;
+  const [, , oh, ow] = output.shape;
+  const n = oh * ow;
+  if (!implicit && (ic < 32 || ic % 32 !== 0 || n % 64 !== 0 || oc < 16)) return false;
+  const half = input.dtype === 'float16';
+  const direct = half
+    ? oc % 32 === 0
+    : oc % 64 === 0 && ctx.device.limits.maxComputeWorkgroupStorageSize >= 24576;
+  const rows = !half && direct ? 64 : 32;
+  const key = `${implicit ? '3x3' : '1x1'}-${half ? 'f16' : 'f32'}-${direct ? 'direct' : 'shared'}`;
+  const params = ctx.uniformBuffer(new Uint32Array([bias ? 1 : 0, 0, 0, 0]));
+  /* eslint-disable @typescript-eslint/naming-convention -- Published WGSL names */
+  const constants = {
+    M: oc,
+    K: ic * kh * kw,
+    N: n,
+    ...(implicit
+      ? {
+          K_LOOP: Math.ceil((ic * kh * kw) / 32) * 32,
+          CONV_STRIDE_H: stride[0],
+          CONV_STRIDE_W: stride[1] ?? stride[0],
+          CONV_DILATION_H: dilation[0],
+          CONV_DILATION_W: dilation[1] ?? dilation[0],
+          CONV_PAD_TOP: padding[0],
+          CONV_PAD_LEFT: padding[1] ?? padding[0],
+          CONV_IN_H: ih,
+          CONV_IN_W: iw,
+          CONV_OUT_W: ow,
+          CONV_IN_CHANNELS: ic,
+        }
+      : {}),
+  };
+  /* eslint-enable @typescript-eslint/naming-convention */
+  const bundle = createComputeBundle(
+    ctx.device,
+    generated.variants[key],
+    [
+      { binding: 0, buffer: output.buffer },
+      { binding: 1, buffer: input.buffer },
+      { binding: 2, buffer: weight.buffer },
+      { binding: 3, buffer: bias?.buffer ?? weight.buffer },
+      { binding: 4, buffer: params },
+    ],
+    constants
+  );
+  ctx.addDispatch({
+    pipeline: bundle.pipeline,
+    bindGroup: bundle.bindGroup,
+    workgroupCountX: Math.ceil(n / 64),
+    workgroupCountY: Math.ceil(oc / rows),
+    workgroupCountZ: batch,
+  });
+  return true;
+}
diff --git a/utils/benchmark/hf-results.json b/utils/benchmark/hf-results.json
new file mode 100644
index 0000000..a62eef1
--- /dev/null
+++ b/utils/benchmark/hf-results.json
@@ -0,0 +1,4146 @@
+{
+  "baseline": "01e4f13",
+  "sourceRevision": "7b19a1ea4fd2abef3203991ca933405f12cfcc62",
+  "conclusion": "No full-YOLO speedup from these adapted register or subgroup-matrix routes on this adapter. Keep experimental adapters opt-in; default runtime and model artifacts unchanged.",
+  "scope": [
+    "Direct adaptations of the published Conv register and subgroup-matrix templates, not generic kernels inspired by HF.",
+    "1x1 direct register GEMM, 3x3 implicit gathering, 64/32-row register tiles, K16/32, published carried-gather mode 1.",
+    "Experimental matrix: aligned 1x1 plus implicit 3x3 with K tails, FP32 accumulation and 32-lane subgroups; request up to 32KiB workgroup storage when adapter permits. Both baseline and HF variants share the same device/limits.",
+    "The complete HF loader/selection heuristics, split-K, explicit im2col, other operators and graph fusion are not implemented or assessed.",
+    "15 raw convolution shapes, both precisions, 8 warmups and 51 rotated samples, dispatches recorded once. GPU timestamps for repeated raw kernels; submit+sync wall time for unchanged full YOLO graph. No camera/pre/post/presentation.",
+    "Two independent runs; absolute times vary with device/browser state. Use paired within-run ratios. Findings are for this Apple/Metal adapter and Chrome, not a cross-hardware ranking."
+  ],
+  "numerics": [
+    "All model variants pass the existing project PyTorch fixture tolerances: f32 abs <=0.01 everywhere; f16 abs <=0.5 for at least 95% of output elements. These are existing tolerances, not bitwise equivalence.",
+    "HF preserves FP32 accumulation even for FP16 storage. Baseline uses FP16 accumulation. FP16 comparisons include an accuracy/performance tradeoff.",
+    "22 Node CPU-oracle cases cover register routes, tails, batches, stride, dilation and optional bias. Browser CPU oracles independently cover both matrix routes, batch2, partial tiles and absent bias; poisoned outputs detect missing writes.",
+    "Raw HF outputs match the rounded F32 reference on deliberately dyadic inputs. This exactness is specific to these bounded diagnostic inputs, not a general exact-output claim."
+  ],
+  "modelSummary": [
+    {
+      "run": 1,
+      "precision": "float32",
+      "routes": ["baseline", "1x1", "3x3", "both", "3x3-m32", "both-m32", "matrix"],
+      "medianMs": [
+        15.200000047683716, 16.5, 19.399999976158142, 20.799999952316284, 19.399999976158142, 21,
+        17.09999990463257
+      ],
+      "speedupsAgainstBaseline": [
+        1, 0.9212121241020433, 0.7835051580599967, 0.7307692347369956, 0.7835051580599967,
+        0.7238095260801769, 0.8888888966347817
+      ],
+      "referenceChecksPass": true
+    },
+    {
+      "run": 1,
+      "precision": "float16",
+      "routes": ["baseline", "1x1", "3x3", "both", "3x3-m32", "both-m32", "matrix"],
+      "medianMs": [
+        12.199999928474426, 13.400000095367432, 15.5, 17.299999952316284, 16.200000047683716,
+        17.699999928474426, 14.600000023841858
+      ],
+      "speedupsAgainstBaseline": [
+        1, 0.9104477493766688, 0.7870967695789952, 0.70520230994804, 0.7530864131212635,
+        0.689265535467488, 0.8356164320925875
+      ],
+      "referenceChecksPass": true
+    },
+    {
+      "run": 2,
+      "precision": "float32",
+      "routes": ["baseline", "1x1", "3x3", "both", "3x3-m32", "both-m32", "matrix"],
+      "medianMs": [
+        13.400000095367432, 14.599999904632568, 17.09999990463257, 17.899999976158142,
+        17.299999952316284, 18.300000071525574, 15.199999928474426
+      ],
+      "speedupsAgainstBaseline": [
+        1, 0.917808231705236, 0.7836257409415092, 0.748603358280197, 0.7745664816359329,
+        0.7322404395078423, 0.8815789577909785
+      ],
+      "referenceChecksPass": true
+    },
+    {
+      "run": 2,
+      "precision": "float16",
+      "routes": ["baseline", "1x1", "3x3", "both", "3x3-m32", "both-m32", "matrix"],
+      "medianMs": [
+        11.399999976158142, 12.899999976158142, 14.799999952316284, 16.299999952316284,
+        15.300000071525574, 16.699999928474426, 13.899999976158142
+      ],
+      "speedupsAgainstBaseline": [
+        1, 0.8837209300176505, 0.7702702711410466, 0.6993865036507663, 0.7450980341741554,
+        0.682634732034969, 0.8201438845835897
+      ],
+      "referenceChecksPass": true
+    }
+  ],
+  "reproduce": {
+    "command": "WGPU_KERNEL_BASELINE=01e4f13 npm run benchmark:hf -- /tmp/hf-run.json",
+    "shaderGeneration": "Install Jinja2 in a separate Python environment, then run utils/benchmark/adapt-hf-conv.py and utils/benchmark/adapt-hf-matrix.py. Generated shaders are committed; normal tests and benchmarks require no Python/Jinja2."
+  },
+  "runs": [
+    {
+      "baseline": "01e4f13",
+      "method": "Pinned Hugging Face Conv adaptation against archived baseline; see per-run method and numerical validation.",
+      "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
+      "results": [
+        {
+          "precision": "float32",
+          "upstreamRevision": "7b19a1ea4fd2abef3203991ca933405f12cfcc62",
+          "gpu": {
+            "vendor": "apple",
+            "architecture": "metal-3"
+          },
+          "matrixAvailable": true,
+          "maxComputeWorkgroupStorageSize": 32768,
+          "subgroupInfo": {
+            "min": 32,
+            "max": 32,
+            "matrixConfigs": [
+              {
+                "componentType": "f32",
+                "resultComponentType": "f32",
+                "M": 8,
+                "N": 8,
+                "K": 8
+              },
+              {
+                "componentType": "f16",
+                "resultComponentType": "f16",
+                "M": 8,
+                "N": 8,
+                "K": 8
+              }
+            ]
+          },
+          "availableFeatures": [
+            "depth32float-stencil8",
+            "chromium-experimental-subgroup-matrix",
+            "rg11b10ufloat-renderable",
+            "bgra8unorm-storage",
+            "texture-formats-tier1",
+            "texture-compression-bc",
+            "dual-source-blending",
+            "core-features-and-limits",
+            "float32-filterable",
+            "indirect-first-instance",
+            "texture-compression-astc-sliced-3d",
+            "float32-blendable",
+            "subgroup-size-control",
+            "texture-compression-unaligned",
+            "texture-compression-astc",
+            "texture-compression-etc2",
+            "depth-clip-control",
+            "texture-compression-bc-sliced-3d",
+            "texture-formats-tier2",
+            "timestamp-query",
+            "clip-distances",
+            "shader-f16",
+            "primitive-index",
+            "texture-component-swizzle",
+            "subgroups"
+          ],
+          "browser": "Mozilla/5.0 (Macintosh; Intel Mac OS X 10_15_7) AppleWebKit/537.36 (KHTML, like Gecko) HeadlessChrome/155.0.0.0 Safari/537.36",
+          "method": "Pinned HF register-tiled Conv template, 64x64 and 32x64/8x4 register layouts, carried implicit gathering (published default mode=1), K=32 when reduction divisible by 32 else 16; FP32 accumulation preserved. Bindings and geometry pipeline constants adapted. This is not the full HF loader/route-selection policy; split-K excluded. Aligned 1x1 and implicit 3x3 subgroup-matrix routes measured separately when experimental features are available; published f32 wide/f16 narrow tiles, direct inputs when aligned, subgroup size pinned to 32. Identical buffers/graphs, commands recorded once. Kernel timings: repeated dispatches, GPU timestamps. Model timings: rotated alternating submit+sync wall clock, no camera/pre/post/presentation. CPU-oracle tests cover the adapters; raw shaders compared to F32 arithmetic; models validated against project PyTorch fixtures.",
+          "warmups": 8,
+          "samples": 51,
+          "results": [
+            {
+              "category": "kernel",
+              "shape": [48, 64, 160, 1, 1, 0],
+              "variants": ["baseline", "hf-m64"],
+              "medians": [0.20664475, 0.2710335],
+              "samples": [
+                [
+                  0.41190625, 0.16605525, 0.16669025, 0.203218, 0.17345025, 0.20271775, 0.38910425,
+                  0.32032, 0.45725325, 0.24883825, 0.20309325, 0.343682, 0.20664475, 0.2508275,
+                  0.2034785, 0.233652, 0.163295, 0.164097, 0.20305125, 0.26226375, 0.23602675,
+                  0.1645655, 0.34568175, 0.202989, 0.165951, 0.2031865, 0.16595125, 0.247911,
+                  0.3865805, 0.2673275, 0.16471925, 0.42196375, 0.2023, 0.17718725, 0.20266475,
+                  0.40386075, 0.403194, 0.1649795, 0.45794075, 0.3452915, 0.20200875, 0.43081725,
+                  0.2530575, 0.372998, 0.24680775, 0.165011, 0.2251425, 0.3738, 0.126607,
+                  0.15666775, 0.164365
+                ],
+                [
+                  0.4828855, 0.22139325, 0.353806, 0.562419, 0.3824175, 0.2702835, 0.226528,
+                  0.2710335, 0.2538895, 0.52259, 0.2709295, 0.52403775, 0.2538585, 0.27087725,
+                  0.483459, 0.27130425, 0.33594325, 0.358243, 0.2710335, 0.222851, 0.21832025,
+                  0.42763125, 0.270148, 0.4285895, 0.318945, 0.24494275, 0.22061175, 0.2712335,
+                  0.2253925, 0.59496375, 0.2198515, 0.27184825, 0.433328, 0.3525305, 0.4792625,
+                  0.27106675, 0.25078675, 0.3268345, 0.2735145, 0.2601195, 0.2692855, 0.2304235,
+                  0.2182365, 0.22127825, 0.43673375, 0.2218615, 0.21814275, 0.2189135, 0.1962485,
+                  0.4273075, 0.21339325
+                ]
+              ],
+              "speedups": [1, 0.7624325037310886],
+              "repeats": 4,
+              "errorsVsFloat32Reference": [0, 0]
+            },
+            {
+              "category": "kernel",
+              "shape": [64, 64, 80, 1, 1, 0],
+              "variants": ["baseline", "hf-m64", "hf-matrix"],
+              "medians": [0.05021725, 0.069690625, 0.0528265],
+              "samples": [
+                [
+                  0.107854375, 0.04987875, 0.049519375, 0.08236725, 0.049712, 0.0495245, 0.12195975,
+                  0.054524375, 0.0498735, 0.051087, 0.12218375, 0.04952975, 0.0667635, 0.049701625,
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+                  0.11537675, 0.04978475, 0.049628625, 0.05047225, 0.04951925, 0.050529625,
+                  0.05020675, 0.04936825, 0.049748375, 0.049696375, 0.050633875, 0.049826625,
+                  0.049920375, 0.05080575, 0.04950375, 0.05611825, 0.05021725, 0.054914875,
+                  0.049363125, 0.049613, 0.132870875, 0.04946725, 0.078237125, 0.049535
+                ],
+                [
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+                  0.065336625, 0.06394075, 0.09724175, 0.1264285, 0.064774125, 0.1478445,
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+                  0.06586775, 0.147735125, 0.086518125, 0.064472, 0.160526375, 0.167484375,
+                  0.065102125, 0.072976875, 0.0644355, 0.064143875, 0.0638315, 0.06994575,
+                  0.06427925
+                ],
+                [
+                  0.117880125, 0.051664375, 0.094648125, 0.051649375, 0.052524375, 0.053415,
+                  0.05167025, 0.052165125, 0.051686, 0.0520505, 0.051659875, 0.052071375,
+                  0.05186825, 0.051764, 0.05198275, 0.052363, 0.13376675, 0.0528265, 0.051587125,
+                  0.05253475, 0.074138375, 0.058597125, 0.05171725, 0.053139, 0.055014, 0.135548,
+                  0.053748375, 0.05229525, 0.129282625, 0.051665, 0.05224325, 0.0529255, 0.05358175,
+                  0.0543315, 0.051889, 0.053066, 0.074570625, 0.05179525, 0.12010575, 0.054789875,
+                  0.0517535, 0.13451675, 0.05171725, 0.05161825, 0.052961875, 0.103377125,
+                  0.0571545, 0.051722375, 0.08162775, 0.060081375, 0.133839625
+                ]
+              ],
+              "speedups": [1, 0.7205739652930361, 0.9506071763224897],
+              "repeats": 8,
+              "errorsVsFloat32Reference": [0, 0, 0]
+            },
+            {
+              "category": "kernel",
+              "shape": [96, 128, 80, 1, 1, 0],
+              "variants": ["baseline", "hf-m64", "hf-matrix"],
+              "medians": [0.20151475, 0.246715, 0.19700725],
+              "samples": [
+                [
+                  0.20061875, 0.200452, 0.40944575, 0.45652775, 0.34540625, 0.200567, 0.2012335,
+                  0.20151475, 0.3064015, 0.20201775, 0.26064175, 0.217132, 0.2023095, 0.20252825,
+                  0.200924, 0.19319525, 0.2008195, 0.16571625, 0.24630875, 0.20167375, 0.20460125,
+                  0.257496, 0.310787, 0.1626435, 0.162362, 0.162362, 0.45341, 0.16240375,
+                  0.18697625, 0.17521625, 0.359609, 0.42376425, 0.35716125, 0.20127825, 0.28961,
+                  0.16156, 0.1230815, 0.1613725, 0.161664, 0.37666075, 0.21405925, 0.1616435,
+                  0.16157025, 0.211153, 0.16241425, 0.20134075, 0.36939025, 0.42371225, 0.200747,
+                  0.3328075, 0.2011325
+                ],
+                [
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+                  0.24533625, 0.48772175, 0.4980965, 0.24543375, 0.245038, 0.30741175, 0.36574425,
+                  0.25475675, 0.49275275, 0.5012635, 0.50547125, 0.245215, 0.24530875, 0.2456525,
+                  0.246715, 0.197945, 0.24429875, 0.19973675, 0.4966695, 0.19834075, 0.22008,
+                  0.36507775, 0.1996325, 0.4650765, 0.24448575, 0.19756975, 0.246142, 0.385348,
+                  0.4043585, 0.244767, 0.29358925, 0.20666375, 0.19697625, 0.40734775, 0.35965075,
+                  0.408525, 0.198351, 0.307464, 0.46399275, 0.20131975, 0.19809075, 0.2469545,
+                  0.33747425, 0.24531925
+                ],
+                [
+                  0.26396075, 0.16257825, 0.16043275, 0.16250525, 0.38373825, 0.160089, 0.45054875,
+                  0.41829975, 0.16315375, 0.16226825, 0.44821175, 0.4178165, 0.44836825, 0.198528,
+                  0.302558, 0.25828775, 0.1996325, 0.317016, 0.199247, 0.450566, 0.435462,
+                  0.19700725, 0.15934125, 0.16463275, 0.45582625, 0.2561105, 0.447472, 0.159612,
+                  0.1984345, 0.15996625, 0.200549, 0.32387, 0.1606955, 0.1647685, 0.15973725,
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+                  0.15959125, 0.159508, 0.16004975, 0.16018525, 0.2832145, 0.16008075, 0.3603695,
+                  0.182716, 0.19898625
+                ]
+              ],
+              "speedups": [1, 0.8167916421782219, 1.0228798686342762],
+              "repeats": 4,
+              "errorsVsFloat32Reference": [0, 0, 0]
+            },
+            {
+              "category": "kernel",
+              "shape": [192, 128, 40, 1, 1, 0],
+              "variants": ["baseline", "hf-m64", "hf-matrix"],
+              "medians": [0.12247033333333333, 0.15546983333333333, 0.12249816666666667],
+              "samples": [
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+                  0.11750500000000001, 0.2205035, 0.28375266666666665, 0.119519, 0.12002600000000001
+                ],
+                [
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+                  0.13077583333333334, 0.13309516666666668, 0.27102366666666666,
+                  0.13589366666666666, 0.26716266666666666
+                ],
+                [
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+                1, 0.8837209300176505, 0.7702702711410466, 0.6993865036507663, 0.7450980341741554,
+                0.682634732034969, 0.8201438845835897
+              ],
+              "repeats": 1,
+              "validation": [
+                {
+                  "maxAbs": 17.733627319335938,
+                  "meanAbs": 0.013195362013996707,
+                  "beyondTolerance": 4223,
+                  "tolerance": 0.5,
+                  "allowedBeyondTolerance": 35280,
+                  "passesProjectReferenceTolerance": true
+                },
+                {
+                  "maxAbs": 10.358627319335938,
+                  "meanAbs": 0.010291656360117094,
+                  "beyondTolerance": 2893,
+                  "tolerance": 0.5,
+                  "allowedBeyondTolerance": 35280,
+                  "passesProjectReferenceTolerance": true
+                },
+                {
+                  "maxAbs": 16.7381591796875,
+                  "meanAbs": 0.011552178193775638,
+                  "beyondTolerance": 3149,
+                  "tolerance": 0.5,
+                  "allowedBeyondTolerance": 35280,
+                  "passesProjectReferenceTolerance": true
+                },
+                {
+                  "maxAbs": 7.288127899169922,
+                  "meanAbs": 0.008190269806242342,
+                  "beyondTolerance": 1661,
+                  "tolerance": 0.5,
+                  "allowedBeyondTolerance": 35280,
+                  "passesProjectReferenceTolerance": true
+                },
+                {
+                  "maxAbs": 16.7381591796875,
+                  "meanAbs": 0.011552178193775638,
+                  "beyondTolerance": 3149,
+                  "tolerance": 0.5,
+                  "allowedBeyondTolerance": 35280,
+                  "passesProjectReferenceTolerance": true
+                },
+                {
+                  "maxAbs": 7.288127899169922,
+                  "meanAbs": 0.008190269806242342,
+                  "beyondTolerance": 1661,
+                  "tolerance": 0.5,
+                  "allowedBeyondTolerance": 35280,
+                  "passesProjectReferenceTolerance": true
+                },
+                {
+                  "maxAbs": 13.983627319335938,
+                  "meanAbs": 0.010531825289943474,
+                  "beyondTolerance": 2716,
+                  "tolerance": 0.5,
+                  "allowedBeyondTolerance": 35280,
+                  "passesProjectReferenceTolerance": true
+                }
+              ]
+            }
+          ]
+        }
+      ]
+    }
+  ],
+  "host": "Apple M1 Pro",
+  "verification": {
+    "testsPassed": 209,
+    "testsSkipped": 2,
+    "typecheck": "passed",
+    "lint": "passed",
+    "exampleBuild": "passed",
+    "productionSourceChanges": false
+  }
+}
diff --git a/utils/benchmark/huggingface/LICENSE b/utils/benchmark/huggingface/LICENSE
new file mode 100644
index 0000000..d645695
--- /dev/null
+++ b/utils/benchmark/huggingface/LICENSE
@@ -0,0 +1,202 @@
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
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+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
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+      file or class name and description of purpose be included on the
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+   Copyright [yyyy] [name of copyright owner]
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/utils/benchmark/huggingface/NOTICE b/utils/benchmark/huggingface/NOTICE
new file mode 100644
index 0000000..2f4b571
--- /dev/null
+++ b/utils/benchmark/huggingface/NOTICE
@@ -0,0 +1,17 @@
+Hugging Face WebGPU Conv adaptation
+Upstream: webgpu-kernels/ai.onnx.Conv
+Revision: 7b19a1ea4fd2abef3203991ca933405f12cfcc62
+Source: https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja
+Upstream shader: Apache-2.0 (see LICENSE and upstream metadata.json).
+Integration code: MIT, https://github.com/barhanc/wgpu-executorch
+Changes: bind existing buffers; guard optional bias via uniform; expose shape
+geometry as pipeline constants. Shader load/compute/store loops are retained.
+Generated variants use published 64x64/32x64, 8x4-per-thread register layouts,
+K=16/32 and carried implicit gathering (IMPLICIT_TILED_GATHER_MODE=1), no split-K or activation/residual fusion. This is not the entire HF
+loader or route-selection policy. The separately rendered subgroup-matrix
+adaptation is from conv-1x1-subgroup-matrix.wgsl.jinja at the same revision:
+aligned 1x1 and implicit 3x3, f32 accumulation, 8x8 hardware matrices,
+32/64-row output tiles, 32-lane subgroups; no split-K or fused activation.
+Original WGSL templates are included unmodified; metadata JSON is reformatted. Generated derivatives
+change bindings, optional-bias guarding and literal shapes into pipeline constants.
+Manifest: https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/manifest.json
diff --git a/utils/benchmark/huggingface/conv-1x1-gemm-tiled-reg.wgsl.jinja b/utils/benchmark/huggingface/conv-1x1-gemm-tiled-reg.wgsl.jinja
new file mode 100644
index 0000000..5032965
--- /dev/null
+++ b/utils/benchmark/huggingface/conv-1x1-gemm-tiled-reg.wgsl.jinja
@@ -0,0 +1,345 @@
+// Register-blocked batched matrix product:
+// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN
+// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a
+// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z
+// batch offset. Accumulation is f32; an optional epilogue applies configured
+// bias, residual, and activation terms in the accumulator domain on store.
+// Every matrix dimension is bounds-checked.
+// f16 operands remain packed in workgroup memory and widen only at the FMA site;
+// the f32 accumulation order is retained while shared traffic is halved.
+//
+// Both shared tiles are stored as vec4 groups along the axis each lane consumes
+// contiguously: tileA groups four K values for one output row, tileB groups four
+// N columns for one K. One micro-tile step therefore reads TM + 4 vector words
+// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many
+// FMAs and the K loop runs four accumulation steps per iteration.
+{{ env.wgsl.resourceDeclarations }}
+{% set tileT = "f16" if usesF16 else "f32" %}
+{% set GEMM_BK = gemmKTile if gemmKTile is defined else 16 %}
+{% set GEMM_TM = gemmThreadRows if gemmThreadRows is defined else 8 %}
+{% set GEMM_WG_X = 16 %}
+{% set GEMM_BM = gemmMTile if gemmMTile is defined else 64 %}
+{% set GEMM_BN = 64 %}
+{% set GEMM_TN = 4 %}
+{% set GEMM_WG_Y = gemmWorkgroupY if gemmWorkgroupY is defined else (GEMM_BM / GEMM_TM)|int %}
+{% set components = ["x", "y", "z", "w"] %}
+const BK: u32 = {{ GEMM_BK }}u;
+const BM: u32 = {{ GEMM_BM }}u;
+const BN: u32 = {{ GEMM_BN }}u;
+const TM: u32 = {{ GEMM_TM }}u;
+const TN: u32 = {{ GEMM_TN }}u;
+const WG_X: u32 = {{ GEMM_WG_X }}u;
+const WG_SIZE: u32 = {{ GEMM_WG_X * GEMM_WG_Y }}u;
+// Vector words per tile row: A groups K, B groups N.
+const AK_VECS: u32 = BK / 4u;
+const BN_VECS: u32 = BN / 4u;
+
+// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel
+// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.
+// Overlapping windows may reread input values, trading address arithmetic and
+// repeated input loads for writing and rereading an expanded column matrix.
+{% set implicitIm2col = implicitIm2col is defined and implicitIm2col %}
+{% set splitKValue = splitK if splitK is defined else 1 %}
+{% set splitKPartial = splitKValue > 1 %}
+{% set kTiles = kTiles | default(0) %}
+{% set mPadded = mPadded | default(0) %}
+{% set nPadded = nPadded | default(0) %}
+{% set batchCount = batchCount | default(0) %}
+{% set gemmKLimit = "kEnd" if splitKPartial else "K" %}
+{% set implicitGatherMode = tunables.IMPLICIT_TILED_GATHER_MODE if tunables.IMPLICIT_TILED_GATHER_MODE is defined else 0 %}
+{% set implicitGatherWgSize = GEMM_WG_X * GEMM_WG_Y %}
+{% set implicitGatherColumnVecs = 16 %}
+{% set implicitGatherKChunks = (implicitGatherWgSize / implicitGatherColumnVecs)|int %}
+{% set implicitGatherDivides = implicitGatherWgSize % implicitGatherColumnVecs == 0 and implicitGatherKChunks > 0 and GEMM_BK % implicitGatherKChunks == 0 %}
+{% set useCarriedImplicitGather = implicitIm2col and implicitGatherMode == 1 and implicitGatherDivides %}
+{% if useCarriedImplicitGather %}
+{% set implicitGatherLoadWidth = (GEMM_BK / implicitGatherKChunks)|int %}
+{% endif %}
+{% if implicitIm2col %}
+const CONV_KERNEL_H: u32 = {{ convKernelH }}u;
+const CONV_KERNEL_W: u32 = {{ convKernelW }}u;
+const CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;
+const CONV_STRIDE_H: u32 = {{ convStrideH }}u;
+const CONV_STRIDE_W: u32 = {{ convStrideW }}u;
+const CONV_DILATION_H: u32 = {{ convDilationH }}u;
+const CONV_DILATION_W: u32 = {{ convDilationW }}u;
+const CONV_PAD_TOP: i32 = {{ convPadTop }};
+const CONV_PAD_LEFT: i32 = {{ convPadLeft }};
+const CONV_IN_H: u32 = {{ convInH }}u;
+const CONV_IN_W: u32 = {{ convInW }}u;
+const CONV_OUT_W: u32 = {{ convOutW }}u;
+const CONV_IN_CHANNELS: u32 = {{ convInChannels }}u;
+{% endif %}
+{% if splitKPartial %}
+// Split-K publishes raw f32 partials. A second pass owns the bias, optional
+// epilogue, output cast, and logical-shape store.
+const SPLIT_K: u32 = {{ splitKValue }}u;
+const K_TILES: u32 = {{ kTiles }}u;
+const PARTIAL_ROWS: u32 = {{ mPadded }}u;
+const PARTIAL_COLS: u32 = {{ nPadded }}u;
+const PARTIAL_BATCH_STRIDE: u32 = PARTIAL_ROWS * PARTIAL_COLS;
+const PARTIAL_SLICE_STRIDE: u32 = {{ batchCount }}u * PARTIAL_BATCH_STRIDE;
+{% endif %}
+{% set emitConvStoreOut = not splitKPartial %}
+{% if emitConvStoreOut | default(true) %}fn store_out(m: u32, n: u32, yBase: u32, raw: f32{% if convPreloadBias | default(false) %}, rowBias: f32{% endif %}) {
+  if (m >= params.M || n >= params.N) {
+    return;
+  }
+  var v = raw;
+{% if hasBias %}
+  v = v + {% if convPreloadBias | default(false) %}rowBias{% else %}f32(bias[m]){% endif %};
+{% endif %}
+  y[yBase + m * params.N + n] = {{ T }}(v);
+}
+{% endif %}
+
+var<workgroup> tileA: array<array<vec4<{{ tileT }}>, AK_VECS>, BM>;
+var<workgroup> tileB: array<array<vec4<{{ tileT }}>, BN_VECS>, BK>;
+{% macro load_a_vec4(rowBase, columnBase, rowLimit, columnLimit) %}
+    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {
+      let ar = linear / AK_VECS;
+      let ac4 = linear % AK_VECS;
+      let am = {{ rowBase }} + ar;
+      let ak = {{ columnBase }} + ac4 * 4u;
+      var av = vec4<{{ tileT }}>({{ tileT }}(0.0));
+      if (am < {{ rowLimit }}) {
+        let aBase = am * K + ak;
+        if (ak + 3u < {{ columnLimit }}) {
+          av = vec4<{{ tileT }}>({{ tileT }}(w[aBase]), {{ tileT }}(w[aBase + 1u]), {{ tileT }}(w[aBase + 2u]), {{ tileT }}(w[aBase + 3u]));
+        } else {
+          for (var t = 0u; t < 4u; t = t + 1u) {
+            if (ak + t < {{ columnLimit }}) {
+              av[t] = {{ tileT }}(w[aBase + t]);
+            }
+          }
+        }
+      }
+      tileA[ar][ac4] = av;
+    }{% endmacro %}
+{% macro load_b_vec4(rowBase, columnBase, rowLimit, columnLimit) %}
+    for (var linear = li; linear < BK * BN_VECS; linear += WG_SIZE) {
+      let br = linear / BN_VECS;
+      let bc4 = linear % BN_VECS;
+      let bk = {{ rowBase }} + br;
+      let bn = {{ columnBase }} + bc4 * 4u;
+      var bvec = vec4<{{ tileT }}>({{ tileT }}(0.0));
+      if (bk < {{ rowLimit }}) {
+        let bBase = xBatchBase + bk * N + bn;
+        if (bn + 3u < {{ columnLimit }}) {
+          bvec = vec4<{{ tileT }}>({{ tileT }}(xm[bBase]), {{ tileT }}(xm[bBase + 1u]), {{ tileT }}(xm[bBase + 2u]), {{ tileT }}(xm[bBase + 3u]));
+        } else {
+          for (var t = 0u; t < 4u; t = t + 1u) {
+            if (bn + t < {{ columnLimit }}) {
+              bvec[t] = {{ tileT }}(xm[bBase + t]);
+            }
+          }
+        }
+      }
+      tileB[br][bc4] = bvec;
+    }{% endmacro %}
+{% macro load_b_implicit_vec4(rowBase, columnBase, rowLimit, columnLimit) %}
+    for (var linear = li; linear < BK * BN_VECS; linear += WG_SIZE) {
+      let br = linear / BN_VECS;
+      let bc4 = linear % BN_VECS;
+      let bk = {{ rowBase }} + br;
+      var bvec = vec4<{{ tileT }}>({{ tileT }}(0.0));
+      if (bk < {{ rowLimit }}) {
+        // k flattens the input-channel and spatial-tap axes; n is the output position.
+        let ic = bk / CONV_KSIZE;
+        let kq = bk % CONV_KSIZE;
+        let kh = kq / CONV_KERNEL_W;
+        let kw = kq % CONV_KERNEL_W;
+        let planeBase = (batch * CONV_IN_CHANNELS + ic) * CONV_IN_H;
+        for (var t = 0u; t < 4u; t = t + 1u) {
+          let bn = {{ columnBase }} + bc4 * 4u + t;
+          if (bn < {{ columnLimit }}) {
+            let oh = bn / CONV_OUT_W;
+            let ow = bn % CONV_OUT_W;
+            let ih = i32(oh * CONV_STRIDE_H + kh * CONV_DILATION_H) - CONV_PAD_TOP;
+            let iw = i32(ow * CONV_STRIDE_W + kw * CONV_DILATION_W) - CONV_PAD_LEFT;
+            if (ih >= 0 && ih < i32(CONV_IN_H) && iw >= 0 && iw < i32(CONV_IN_W)) {
+              bvec[t] = {{ tileT }}(xm[(planeBase + u32(ih)) * CONV_IN_W + u32(iw)]);
+            }
+          }
+        }
+      }
+      tileB[br][bc4] = bvec;
+    }{% endmacro %}
+{% macro load_b_implicit_carried(rowBase, columnBase, rowLimit, columnLimit) %}
+    let bColVec = li / {{ implicitGatherKChunks }}u;
+    let bChunk = li % {{ implicitGatherKChunks }}u;
+    let bLocalK = bChunk * {{ implicitGatherLoadWidth }}u;
+    let bStartK = {{ rowBase }} + bLocalK;
+    let bCol0 = {{ columnBase }} + bColVec * 4u;
+    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);
+    let inColumn = bCols < vec4<u32>({{ columnLimit }});
+    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);
+    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);
+    var carriedK = bStartK;
+    var carriedIc = carriedK / CONV_KSIZE;
+    let carriedKq = carriedK % CONV_KSIZE;
+    var carriedKh = carriedKq / CONV_KERNEL_W;
+    var carriedKw = carriedKq % CONV_KERNEL_W;
+    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));
+    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));
+
+    // Interior words can carry four addresses. Padding, the N tail, and the
+    // final K tile retain the coordinate-checked loop below and publish exact
+    // zeros.
+    let interior = all(inColumn)
+      && bStartK + {{ implicitGatherLoadWidth }}u <= {{ rowLimit }}
+      && all(ih0 >= vec4<i32>(0))
+      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))
+      && all(iw0 >= vec4<i32>(0))
+      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));
+    if (interior) {
+      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;
+      let colStep = i32(CONV_DILATION_W);
+      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);
+      let planeStep = i32(CONV_IN_H * CONV_IN_W);
+      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;
+      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;
+      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;
+      for (var i = 0u; i < {{ implicitGatherLoadWidth }}u; i = i + 1u) {
+        tileB[bLocalK + i][bColVec] = vec4<{{ tileT }}>(
+{% for component in components %}
+          {{ tileT }}(xm[batchBase + u32(carriedAddress.{{ component }})]){% if not loop.last %},{% endif %}
+{% endfor %}
+        );
+        carriedAddress = carriedAddress + vec4<i32>(colStep);
+        carriedKw = carriedKw + 1u;
+        if (carriedKw == CONV_KERNEL_W) {
+          carriedKw = 0u;
+          carriedAddress = carriedAddress - vec4<i32>(kwWrap);
+          carriedKh = carriedKh + 1u;
+          if (carriedKh == CONV_KERNEL_H) {
+            carriedKh = 0u;
+            carriedAddress = carriedAddress - vec4<i32>(khWrap);
+          }
+        }
+      }
+    } else {
+      for (var i = 0u; i < {{ implicitGatherLoadWidth }}u; i = i + 1u) {
+        var carriedValue = vec4<{{ tileT }}>({{ tileT }}(0.0));
+        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;
+        let carriedOk = inColumn
+          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))
+          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));
+        if (carriedK < {{ rowLimit }}) {
+{% for component in components %}
+          if (carriedOk.{{ component }}) {
+            carriedValue.{{ component }} = {{ tileT }}(xm[(carriedRow + u32(carriedIh.{{ component }})) * CONV_IN_W + u32(carriedIw.{{ component }})]);
+          }
+{% endfor %}
+        }
+        tileB[bLocalK + i][bColVec] = carriedValue;
+        carriedK = carriedK + 1u;
+        carriedKw = carriedKw + 1u;
+        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));
+        if (carriedKw == CONV_KERNEL_W) {
+          carriedKw = 0u;
+          carriedIw = iw0;
+          carriedKh = carriedKh + 1u;
+          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));
+          if (carriedKh == CONV_KERNEL_H) {
+            carriedKh = 0u;
+            carriedIh = ih0;
+            carriedIc = carriedIc + 1u;
+          }
+        }
+      }
+    }{% endmacro %}
+
+@compute @workgroup_size({{ GEMM_WG_X }}, {{ GEMM_WG_Y }}, 1)
+fn main(
+  @builtin(workgroup_id) wg: vec3<u32>,
+  @builtin(local_invocation_id) lid: vec3<u32>
+) {
+  let M = params.M;
+  let K = params.K;
+  let N = params.N;
+  let mBase = wg.y * BM;
+  let nBase = wg.x * BN;
+{% if splitKPartial %}
+  // z carries a K slice within a batch image, matching the subgroup-matrix
+  // Conv split-K layout and the shared reduction pass.
+  let slice = wg.z % SPLIT_K;
+  let batch = wg.z / SPLIT_K;
+{% else %}
+  let batch = wg.z;
+{% endif %}
+{% if not implicitIm2col %}
+  let xBatchBase = batch * K * N;
+{% endif %}
+  let li = lid.y * WG_X + lid.x;
+
+  // The statically named accumulator vectors form TM independent FMA chains.
+{% for row in range(GEMM_TM) %}
+  var acc{{ row }} = vec{{ GEMM_TN }}<f32>(0.0);
+{% endfor %}
+
+{% if splitKPartial %}
+  // Partition whole BK-wide tiles by quotient boundaries. This keeps every
+  // slice within one tile of every other slice and creates no empty tail slice
+  // whenever K_TILES >= SPLIT_K (this route requires a stronger floor).
+  let kBegin = (slice * K_TILES / SPLIT_K) * BK;
+  let kEnd = min(((slice + 1u) * K_TILES / SPLIT_K) * BK, K);
+  let kCount = kEnd - kBegin;
+  let numTiles = (kCount + BK - 1u) / BK;
+{% else %}
+  let numTiles = (K + BK - 1u) / BK;
+{% endif %}
+  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {
+{% if splitKPartial %}
+    let kBase = kBegin + kt * BK;
+{% else %}
+    let kBase = kt * BK;
+{% endif %}
+{{ load_a_vec4("mBase", "kBase", "M", gemmKLimit) }}
+{% if useCarriedImplicitGather %}
+{{ load_b_implicit_carried("kBase", "nBase", gemmKLimit, "N") }}
+{% elif implicitIm2col %}
+{{ load_b_implicit_vec4("kBase", "nBase", gemmKLimit, "N") }}
+{% else %}
+{{ load_b_vec4("kBase", "nBase", gemmKLimit, "N") }}
+{% endif %}
+    workgroupBarrier();
+    // One iteration consumes four K steps: TM vector words of A and four of B
+    // cover TM x TN x 4 FMAs.
+    let aRow = lid.y * TM;
+    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {
+{% for row in range(GEMM_TM) %}
+      let av{{ row }} = vec4<f32>(tileA[aRow + {{ row }}u][kv]);
+{% endfor %}
+{% for sub in range(4) %}
+      let bv{{ sub }} = vec{{ GEMM_TN }}<f32>(tileB[kv * 4u + {{ sub }}u][lid.x]);
+{% for row in range(GEMM_TM) %}
+      acc{{ row }} += vec{{ GEMM_TN }}<f32>(av{{ row }}.{{ components[sub] }}) * bv{{ sub }};
+{% endfor %}
+{% endfor %}
+    }
+    workgroupBarrier();
+  }
+
+{% if splitKPartial %}
+  let m0 = mBase + lid.y * TM;
+  let n0 = nBase + lid.x * TN;
+  let partialBase = slice * PARTIAL_SLICE_STRIDE + batch * PARTIAL_BATCH_STRIDE;
+{% else %}
+  let yBatchBase = batch * M * N;
+  let m0 = mBase + lid.y * TM;
+  let n0 = nBase + lid.x * TN;
+{% endif %}
+{% for row in range(GEMM_TM) %}
+{% if convPreloadBias | default(false) %}
+  var rowBias{{ row }} = 0.0;
+  if (m0 + {{ row }}u < M) { rowBias{{ row }} = f32(bias[m0 + {{ row }}u]); }
+{% endif %}
+{% for column in range(GEMM_TN) %}
+{% if splitKPartial %}
+  y[partialBase + (m0 + {{ row }}u) * PARTIAL_COLS + n0 + {{ column }}u] = acc{{ row }}.{{ components[column] }};
+{% else %}
+  store_out(m0 + {{ row }}u, n0 + {{ column }}u, yBatchBase, acc{{ row }}.{{ components[column] }}{% if convPreloadBias | default(false) %}, rowBias{{ row }}{% endif %});
+{% endif %}
+{% endfor %}
+{% endfor %}}
diff --git a/utils/benchmark/huggingface/conv-1x1-subgroup-matrix.wgsl.jinja b/utils/benchmark/huggingface/conv-1x1-subgroup-matrix.wgsl.jinja
new file mode 100644
index 0000000..a64be28
--- /dev/null
+++ b/utils/benchmark/huggingface/conv-1x1-subgroup-matrix.wgsl.jinja
@@ -0,0 +1,495 @@
+// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).
+// A is row-major; B may be a direct matrix view, a materialized column matrix,
+// or an on-demand gather. Accumulation is f32. A configured epilogue may apply
+// bias or other output transforms after the full K reduction.
+//
+// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces
+// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and
+// zero-fills directly from NCHW without materializing the column matrix.
+//
+// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw
+// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines
+// the slices and applies bias or an epilogue. Padded tail cells remain zero and
+// are never copied to the logical output.
+{% set directMatrixInputs = directMatrixInputs is defined and directMatrixInputs %}
+{% set fusedNarrowProjection = false %}
+{% set polyphase = false %}
+{% set implicit = implicitIm2col is defined and implicitIm2col %}
+{% set implicit3d = implicit and (convSpatialDims is defined and convSpatialDims == 3) %}
+{% set splitKValue = splitK if splitK is defined else 1 %}
+{% set splitKPartial = splitKValue > 1 %}
+{% set kLoopVar = "K_LOOP" if padded else "K" %}
+{% set nColsVar = "N_COLS" if padded else "N" %}
+{% set hasZ = false %}
+{% set hasActivation = false %}
+{% set convKernelH = convKernelH | default(0) %}
+{% set convKernelW = convKernelW | default(0) %}
+{% set convStrideH = convStrideH | default(0) %}
+{% set convStrideW = convStrideW | default(0) %}
+{% set convDilationH = convDilationH | default(0) %}
+{% set convDilationW = convDilationW | default(0) %}
+{% set convPadTop = convPadTop | default(0) %}
+{% set convPadLeft = convPadLeft | default(0) %}
+{% set convInH = convInH | default(0) %}
+{% set convInW = convInW | default(0) %}
+{% set convOutW = convOutW | default(0) %}
+{% set convInChannels = convInChannels | default(0) %}
+{% set convKernelD = convKernelD | default(0) %}
+{% set convStrideD = convStrideD | default(0) %}
+{% set convDilationD = convDilationD | default(0) %}
+{% set convPadFront = convPadFront | default(0) %}
+{% set convInD = convInD | default(0) %}
+{% set convOutH = convOutH | default(0) %}
+{% set nPadded = nPadded | default(0) %}
+{% set mPadded = mPadded | default(0) %}
+{% set kChunk = kChunk | default(0) %}
+{% set batchCount = batchCount | default(0) %}
+enable subgroups;
+{% if pinSubgroupSize32 %}
+enable subgroup_size_control;
+{% endif %}
+enable chromium_experimental_subgroup_matrix;
+diagnostic(off, chromium.subgroup_matrix_uniformity);
+
+{{ env.wgsl.resourceDeclarations }}
+{% set operandScalar = fScalar %}
+{% set accScalar = "f32" %}
+{% set useDirectMatrixStore = directMatrixStore is defined and directMatrixStore %}
+{% set tileRowsValue = tileRows if tileRows is defined else 32 %}
+{% set tileColsValue = 64 %}
+{% set workgroupThreadsValue = workgroupThreads if workgroupThreads is defined else 128 %}
+{% set subgroupRowsValue = subgroupRows if subgroupRows is defined else 2 %}
+{% set subRowsValue = (tileRowsValue / subgroupRowsValue)|int %}
+{% set subColsValue = 32 %}
+{% set bLoadWidth = (tileColsValue * 32 / workgroupThreadsValue)|int %}
+{% set bKChunks = (32 / bLoadWidth)|int %}
+
+const M: u32 = {{ M }}u;
+const K: u32 = {{ K }}u;
+{% if not (splitKPartial and padded) or implicit %}
+const N: u32 = {{ N }}u;
+{% endif %}
+{% if padded %}
+const K_LOOP: u32 = {{ kPadded }}u;
+{% endif %}
+{% if implicit %}
+const CONV_KERNEL_H: u32 = {{ convKernelH }}u;
+const CONV_KERNEL_W: u32 = {{ convKernelW }}u;
+{% if implicit3d %}
+const CONV_KERNEL_D: u32 = {{ convKernelD }}u;
+const CONV_KSIZE_HW: u32 = CONV_KERNEL_H * CONV_KERNEL_W;
+const CONV_KSIZE: u32 = CONV_KERNEL_D * CONV_KSIZE_HW;
+const CONV_STRIDE_D: u32 = {{ convStrideD }}u;
+const CONV_DILATION_D: u32 = {{ convDilationD }}u;
+const CONV_PAD_FRONT: i32 = {{ convPadFront }};
+const CONV_IN_D: i32 = {{ convInD }};
+const CONV_OUT_H: u32 = {{ convOutH }}u;
+{% else %}
+const CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;
+{% endif %}
+const CONV_STRIDE_H: u32 = {{ convStrideH }}u;
+const CONV_STRIDE_W: u32 = {{ convStrideW }}u;
+const CONV_DILATION_H: u32 = {{ convDilationH }}u;
+const CONV_DILATION_W: u32 = {{ convDilationW }}u;
+const CONV_PAD_TOP: i32 = {{ convPadTop }};
+const CONV_PAD_LEFT: i32 = {{ convPadLeft }};
+const CONV_IN_H: i32 = {{ convInH }};
+const CONV_IN_W: i32 = {{ convInW }};
+const CONV_OUT_W: u32 = {{ convOutW }}u;
+{% if implicit3d %}
+// X is [batch, inChannels, inD, inH, inW]; the tile gather indexes it directly.
+const B_BATCH_STRIDE: u32 = {{ convInChannels }}u * u32(CONV_IN_D) * u32(CONV_IN_H) * u32(CONV_IN_W);
+{% else %}
+// X is [batch, inChannels, inH, inW]; the tile gather indexes it directly.
+const B_BATCH_STRIDE: u32 = {{ convInChannels }}u * u32(CONV_IN_H) * u32(CONV_IN_W);
+{% endif %}
+{% else %}
+{% if padded %}
+const N_COLS: u32 = {{ nPadded }}u;
+{% endif %}
+const B_BATCH_STRIDE: u32 = {{ kLoopVar }} * {{ nColsVar }};
+{% endif %}
+{% if not splitKPartial and not polyphase and not fusedNarrowProjection %}
+const C_BATCH_STRIDE: u32 = M * N;
+{% endif %}
+{% if splitKPartial %}
+const SPLIT_K: u32 = {{ splitKValue }}u;
+// Whole 32-wide K tiles per slice, rounded up, with the last slice clamped to
+// K_LOOP. This avoids padding K to a multiple of SPLIT_K times the tile width.
+// A slice entirely past K_LOOP runs zero iterations and stores zero
+// accumulators, which is the correct partial for an empty K range.
+const K_CHUNK: u32 = {{ kChunk }}u;
+const PARTIAL_ROWS: u32 = {{ mPadded }}u;
+const PARTIAL_COLS: u32 = {{ nPadded }}u;
+const PARTIAL_SLICE_STRIDE: u32 = {{ batchCount }}u * PARTIAL_ROWS * PARTIAL_COLS;
+{% endif %}
+const TILE_COLS: u32 = {{ tileColsValue }}u;
+const TILE_ROWS: u32 = {{ tileRowsValue }}u;
+const TILE_K: u32 = 32u;
+const SUB_COLS: u32 = {{ subColsValue }}u;
+const SUB_ROWS: u32 = {{ subRowsValue }}u;
+
+{% if not directMatrixInputs %}
+var<workgroup> tile_A: array<{{ operandScalar }}, {{ tileRowsValue }} * 32>;
+var<workgroup> tile_B: array<{{ operandScalar }}, {{ tileColsValue }} * 32>;
+{% endif %}
+{% if (not useDirectMatrixStore or padded) and not splitKPartial and not fusedNarrowProjection %}
+var<workgroup> scratch: array<array<array<{{ accScalar }}, 64>, 4>, {{ (workgroupThreadsValue / 32)|int }}>;
+
+{% endif %}
+{% if not directMatrixInputs %}
+fn loadSHMA(tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {
+  let a_global = tile_base + row;
+  let col = c_idx * 8u;
+  for (var col_offset = 0u; col_offset < 8u; col_offset = col_offset + 1u) {
+    let k = k_idx + col + col_offset;
+    if (a_global < M{% if padded %} && k < K{% endif %}) {
+{% set A_PHASE = "" %}
+{% if operandScalar == "f16" %}
+      tile_A[row * TILE_K + col + col_offset] = f16(w[{{ A_PHASE }}a_global * K + k]);
+{% else %}
+      tile_A[row * TILE_K + col + col_offset] = f32(w[{{ A_PHASE }}a_global * K + k]);
+{% endif %}
+    } else {
+{% if operandScalar == "f16" %}
+      tile_A[row * TILE_K + col + col_offset] = 0.0h;
+{% else %}
+      tile_A[row * TILE_K + col + col_offset] = 0.0;
+{% endif %}
+    }
+  }
+}
+
+fn loadSHMB(b_base: u32, tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {
+  let b_col = tile_base + row;
+  let col = c_idx * {{ bLoadWidth }}u;
+{% if implicit %}
+  // One output position per tile column, so its window origin is loop-invariant.
+{% if implicit3d %}
+  let id0 = i32((b_col / (CONV_OUT_W * CONV_OUT_H)) * CONV_STRIDE_D) - CONV_PAD_FRONT;
+  let ih0 = i32(((b_col / CONV_OUT_W) % CONV_OUT_H) * CONV_STRIDE_H) - CONV_PAD_TOP;
+{% else %}
+  let ih0 = i32((b_col / CONV_OUT_W) * CONV_STRIDE_H) - CONV_PAD_TOP;
+{% endif %}
+  let iw0 = i32((b_col % CONV_OUT_W) * CONV_STRIDE_W) - CONV_PAD_LEFT;
+  let in_column = b_col < N;
+  // k advances by exactly one per element, so the (in-channel, tap-row, tap-col)
+  // decomposition is CARRIED across the loop instead of recomputed: two divisions
+  // and two moduli per loaded element become one increment and one compare, with
+  // the source coordinates advanced by the dilation in step. Only the entry values
+  // divide, and their divisors are compile-time literals.
+  var k = k_idx + col;
+  var ic = k / CONV_KSIZE;
+  var kq = k % CONV_KSIZE;
+{% if implicit3d %}
+  var kd = kq / CONV_KSIZE_HW;
+  var khw = kq % CONV_KSIZE_HW;
+  var kh = khw / CONV_KERNEL_W;
+  var kw = khw % CONV_KERNEL_W;
+  var id = id0 + i32(kd * CONV_DILATION_D);
+{% else %}
+  var kh = kq / CONV_KERNEL_W;
+  var kw = kq % CONV_KERNEL_W;
+{% endif %}
+  var ih = ih0 + i32(kh * CONV_DILATION_H);
+  var iw = iw0 + i32(kw * CONV_DILATION_W);
+  // A tile column whose whole kernel window and K span are in bounds cannot
+  // take any of the element guards below. Hoist them into one uniform test so
+  // the interior loop carries a plain address instead of recomputing coordinates.
+  let interior = in_column
+    && k_idx + col + {{ bLoadWidth }}u <= K
+{% if implicit3d %}
+    && id0 >= 0 && id0 + i32((CONV_KERNEL_D - 1u) * CONV_DILATION_D) < CONV_IN_D
+{% endif %}
+    && ih0 >= 0 && ih0 + i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H) < CONV_IN_H
+    && iw0 >= 0 && iw0 + i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W) < CONV_IN_W;
+  if (interior) {
+    let colStep = i32(CONV_DILATION_W);
+    let rowStep = i32(CONV_DILATION_H) * CONV_IN_W;
+{% if implicit3d %}
+    let depthStep = i32(CONV_DILATION_D) * CONV_IN_H * CONV_IN_W;
+    let planeStep = CONV_IN_D * CONV_IN_H * CONV_IN_W;
+{% else %}
+    let planeStep = CONV_IN_H * CONV_IN_W;
+{% endif %}
+    // Advancing k already added one colStep, so each wrap rewinds that plus the taps it walked.
+    let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;
+{% if implicit3d %}
+    let khWrap = rowStep * i32(CONV_KERNEL_H) - depthStep;
+    let kdWrap = depthStep * i32(CONV_KERNEL_D) - planeStep;
+    var addr = i32(b_base) + i32(ic) * planeStep + (id * CONV_IN_H + ih) * CONV_IN_W + iw;
+{% else %}
+    let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;
+    var addr = i32(b_base) + i32(ic) * planeStep + ih * CONV_IN_W + iw;
+{% endif %}
+    for (var i = 0u; i < {{ bLoadWidth }}u; i = i + 1u) {
+      tile_B[row * TILE_K + col + i] = {{ operandScalar }}(xm[u32(addr)]);
+      addr = addr + colStep;
+      kw = kw + 1u;
+      if (kw == CONV_KERNEL_W) {
+        kw = 0u;
+        addr = addr - kwWrap;
+        kh = kh + 1u;
+        if (kh == CONV_KERNEL_H) {
+          kh = 0u;
+          addr = addr - khWrap;
+{% if implicit3d %}
+          kd = kd + 1u;
+          if (kd == CONV_KERNEL_D) {
+            kd = 0u;
+            addr = addr - kdWrap;
+          }
+{% endif %}
+        }
+      }
+    }
+    return;
+  }
+  for (var i = 0u; i < {{ bLoadWidth }}u; i = i + 1u) {
+    var value = {{ operandScalar }}(0.0);
+    // The K and N tails read as exact zeros, exactly as the materialized padded
+    // cols buffer does, so they contribute nothing to the dot product.
+    if (in_column && k < K{% if implicit3d %} && id >= 0 && id < CONV_IN_D{% endif %} && ih >= 0 && ih < CONV_IN_H && iw >= 0 && iw < CONV_IN_W) {
+{% if implicit3d %}
+      value = {{ operandScalar }}(xm[b_base + ((ic * u32(CONV_IN_D) + u32(id)) * u32(CONV_IN_H) + u32(ih)) * u32(CONV_IN_W) + u32(iw)]);
+{% else %}
+      value = {{ operandScalar }}(xm[b_base + (ic * u32(CONV_IN_H) + u32(ih)) * u32(CONV_IN_W) + u32(iw)]);
+{% endif %}
+    }
+    tile_B[row * TILE_K + col + i] = value;
+    k = k + 1u;
+    kw = kw + 1u;
+    iw = iw + i32(CONV_DILATION_W);
+    if (kw == CONV_KERNEL_W) {
+      kw = 0u;
+      iw = iw0;
+      kh = kh + 1u;
+      ih = ih + i32(CONV_DILATION_H);
+      if (kh == CONV_KERNEL_H) {
+        kh = 0u;
+        ih = ih0;
+{% if implicit3d %}
+        kd = kd + 1u;
+        id = id + i32(CONV_DILATION_D);
+        if (kd == CONV_KERNEL_D) {
+          kd = 0u;
+          id = id0;
+          ic = ic + 1u;
+        }
+{% else %}
+        ic = ic + 1u;
+{% endif %}
+      }
+    }
+  }
+{% else %}
+  for (var i = 0u; i < {{ bLoadWidth }}u; i = i + 1u) {
+    let k = k_idx + col + i;
+{% if operandScalar == "f16" %}
+    tile_B[row * TILE_K + col + i] = f16(xm[b_base + k * {{ nColsVar }} + b_col]);
+{% else %}
+    tile_B[row * TILE_K + col + i] = f32(xm[b_base + k * {{ nColsVar }} + b_col]);
+{% endif %}
+  }
+{% endif %}
+}
+{% endif %}
+{% set hasActivation = false %}
+{% set biasAdd = " + bv" if hasBias else "" %}
+{% macro store_val(valExpr, idxExpr) %}
+{% if hasActivation or hasZ %}
+epi({{ valExpr }}){% else %}
+{{ T }}({{ valExpr }}){% endif %}{% endmacro %}
+
+{% if (not useDirectMatrixStore or padded) and not splitKPartial and not fusedNarrowProjection %}
+fn storeOutput(offset: u32, {% if hasBias or polyphase %}row_base: u32, {% endif %}row: u32, col: u32, src_slot: u32, row_limit: i32{% if padded %}, col_anchor: u32{% endif %}) {
+  if (row_limit > 0 && row < u32(row_limit)) {
+    let col2 = col + 1u;
+{% if hasBias %}
+    let bv = {{ accScalar }}(bias[row_base + row]);
+{% endif %}
+{% if padded %}
+    // Padded GEMM: the last column tile runs past the logical N; only write
+    // columns inside the real output. Each subgroup-matrix column maps to a
+    // distinct y column (anchor + local), so the guards are independent.
+    if (col_anchor + col +  0u < N) { y[offset + row * N + col]        = {{ store_val("scratch[src_slot][0][row * 8u + col]" ~ biasAdd, "offset + row * N + col") }}; }
+    if (col_anchor + col +  8u < N) { y[offset + row * N + col +  8u]  = {{ store_val("scratch[src_slot][1][row * 8u + col]" ~ biasAdd, "offset + row * N + col + 8u") }}; }
+    if (col_anchor + col + 16u < N) { y[offset + row * N + col + 16u]  = {{ store_val("scratch[src_slot][2][row * 8u + col]" ~ biasAdd, "offset + row * N + col + 16u") }}; }
+    if (col_anchor + col + 24u < N) { y[offset + row * N + col + 24u]  = {{ store_val("scratch[src_slot][3][row * 8u + col]" ~ biasAdd, "offset + row * N + col + 24u") }}; }
+    if (col_anchor + col2 +  0u < N) { y[offset + row * N + col2]       = {{ store_val("scratch[src_slot][0][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2") }}; }
+    if (col_anchor + col2 +  8u < N) { y[offset + row * N + col2 +  8u] = {{ store_val("scratch[src_slot][1][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2 + 8u") }}; }
+    if (col_anchor + col2 + 16u < N) { y[offset + row * N + col2 + 16u] = {{ store_val("scratch[src_slot][2][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2 + 16u") }}; }
+    if (col_anchor + col2 + 24u < N) { y[offset + row * N + col2 + 24u] = {{ store_val("scratch[src_slot][3][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2 + 24u") }}; }
+{% else %}
+    y[offset + row * N + col]       = {{ store_val("scratch[src_slot][0][row * 8u + col]" ~ biasAdd, "offset + row * N + col") }};
+    y[offset + row * N + col + 8u]  = {{ store_val("scratch[src_slot][1][row * 8u + col]" ~ biasAdd, "offset + row * N + col + 8u") }};
+    y[offset + row * N + col + 16u] = {{ store_val("scratch[src_slot][2][row * 8u + col]" ~ biasAdd, "offset + row * N + col + 16u") }};
+    y[offset + row * N + col + 24u] = {{ store_val("scratch[src_slot][3][row * 8u + col]" ~ biasAdd, "offset + row * N + col + 24u") }};
+
+    y[offset + row * N + col2]       = {{ store_val("scratch[src_slot][0][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2") }};
+    y[offset + row * N + col2 + 8u]  = {{ store_val("scratch[src_slot][1][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2 + 8u") }};
+    y[offset + row * N + col2 + 16u] = {{ store_val("scratch[src_slot][2][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2 + 16u") }};
+    y[offset + row * N + col2 + 24u] = {{ store_val("scratch[src_slot][3][row * 8u + col2]" ~ biasAdd, "offset + row * N + col2 + 24u") }};
+{% endif %}
+  }
+}
+
+{% endif %}
+@compute @workgroup_size({{ workgroupThreadsValue }}, 1, 1){{ " @subgroup_size(32)" if pinSubgroupSize32 else "" }}
+fn main(
+  @builtin(workgroup_id) workgroup_id: vec3<u32>,
+  @builtin(local_invocation_index) local_idx: u32,
+{% if (not useDirectMatrixStore or padded) and not splitKPartial and not fusedNarrowProjection %}
+  @builtin(subgroup_invocation_id) sg_id: u32,
+{% endif %}
+  @builtin(subgroup_size) sg_size: u32
+) {
+{% if splitKPartial %}
+  // z carries both axes, with split slices contiguous inside each batch image.
+  let slice = workgroup_id.z % SPLIT_K;
+  let batch = workgroup_id.z / SPLIT_K;
+  let b_base = batch * B_BATCH_STRIDE;
+  let c_base = slice * PARTIAL_SLICE_STRIDE + batch * PARTIAL_ROWS * PARTIAL_COLS;
+{% else %}
+  let batch = workgroup_id.z;
+  let b_base = batch * B_BATCH_STRIDE;
+  let c_base = batch * C_BATCH_STRIDE;
+{% endif %}
+  let a_global_base = workgroup_id.y * TILE_ROWS;
+  let b_global_base = workgroup_id.x * TILE_COLS;
+  let subtile_id = local_idx / sg_size;
+  let subtile_idx = subtile_id / {{ subgroupRowsValue }}u;
+  let subtile_idy = subtile_id % {{ subgroupRowsValue }}u;
+  let base_A = subtile_idy * SUB_ROWS;
+  let base_B = subtile_idx * SUB_COLS;
+
+  var matC00: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+  var matC01: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+  var matC02: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+  var matC03: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+  var matC10: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+  var matC11: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+  var matC12: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+  var matC13: subgroup_matrix_result<{{ accScalar }}, 8, 8>;
+
+{% if splitKPartial %}
+  let k_begin = slice * K_CHUNK;
+  let k_end = min(k_begin + K_CHUNK, {{ kLoopVar }});
+  for (var kidx = k_begin; kidx < k_end; kidx = kidx + TILE_K) {
+{% else %}
+  for (var kidx = 0u; kidx < {{ kLoopVar }}; kidx = kidx + TILE_K) {
+{% endif %}
+{% if not directMatrixInputs %}
+    loadSHMA(a_global_base, kidx, local_idx / 4u, local_idx % 4u);
+    loadSHMB(b_base, b_global_base, kidx, local_idx / {{ bKChunks }}u, local_idx % {{ bKChunks }}u);
+    workgroupBarrier();
+{% endif %}
+
+    for (var step = 0u; step < TILE_K; step = step + 8u) {
+{% set directInputs = directMatrixInputs is defined and directMatrixInputs %}
+      let matrix_a_offset = {% if directInputs %}(a_global_base + subtile_idy * SUB_ROWS) * K + kidx + step{% else %}subtile_idy * SUB_ROWS * TILE_K + step{% endif %};
+{% for r in range(2) %}
+      var matA{{ r }}: subgroup_matrix_left<{{ operandScalar }}, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<{{ operandScalar }}, 8, 8>, row_major>(&{{ "w" if directInputs else "tile_A" }}, matrix_a_offset{% if r > 0 %} + 8u * {{ "K" if directInputs else "TILE_K" }}{% endif %}, {{ "K" if directInputs else "TILE_K" }});
+{% endfor %}
+
+      let matrix_b_offset = {% if directInputs %}b_base + (kidx + step) * N + b_global_base + subtile_idx * SUB_COLS{% else %}subtile_idx * SUB_COLS * TILE_K + step{% endif %};
+{% for c in range(4) %}
+      var matB{{ c }}: subgroup_matrix_right<{{ operandScalar }}, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<{{ operandScalar }}, 8, 8>, {% if directInputs %}row_major{% else %}col_major{% endif %}>(&{{ "xm" if directInputs else "tile_B" }}, matrix_b_offset{% if c > 0 %} + {{ c * 8 }}u{% if not directInputs %} * TILE_K{% endif %}{% endif %}, {{ "N" if directInputs else "TILE_K" }});
+{% endfor %}
+
+      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);
+      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);
+      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);
+      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);
+      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);
+      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);
+      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);
+      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);
+    }
+{% if not directMatrixInputs %}
+    workgroupBarrier();
+{% endif %}
+  }
+
+{% if splitKPartial %}
+  // Raw partials, no bias and no epilogue — the reduce pass owns both. The
+  // scratch is whole tiles in both axes, so this needs none of the column or
+  // row guards the real output store carries.
+  let partial_offset = c_base + (a_global_base + base_A) * PARTIAL_COLS + b_global_base + base_B;
+  subgroupMatrixStore<row_major>(&y, partial_offset + 0u * PARTIAL_COLS +  0u, matC00, PARTIAL_COLS);
+  subgroupMatrixStore<row_major>(&y, partial_offset + 0u * PARTIAL_COLS +  8u, matC01, PARTIAL_COLS);
+  subgroupMatrixStore<row_major>(&y, partial_offset + 0u * PARTIAL_COLS + 16u, matC02, PARTIAL_COLS);
+  subgroupMatrixStore<row_major>(&y, partial_offset + 0u * PARTIAL_COLS + 24u, matC03, PARTIAL_COLS);
+  subgroupMatrixStore<row_major>(&y, partial_offset + 8u * PARTIAL_COLS +  0u, matC10, PARTIAL_COLS);
+  subgroupMatrixStore<row_major>(&y, partial_offset + 8u * PARTIAL_COLS +  8u, matC11, PARTIAL_COLS);
+  subgroupMatrixStore<row_major>(&y, partial_offset + 8u * PARTIAL_COLS + 16u, matC12, PARTIAL_COLS);
+  subgroupMatrixStore<row_major>(&y, partial_offset + 8u * PARTIAL_COLS + 24u, matC13, PARTIAL_COLS);
+{% elif useDirectMatrixStore %}
+{% if padded %}
+  // Padded N only needs guarded publication for the final partial-width tile.
+  // Full tiles can use the same direct collective stores as the aligned path;
+  // the branch is uniform because b_global_base depends only on workgroup_id.x.
+  if (b_global_base + TILE_COLS <= N) {
+{% endif %}
+  // Full f32 output tiles can be published by the subgroup-matrix collectives
+  // directly. With no epilogue this removes scratch traffic and three barriers.
+  // When an epilogue is present, publish the raw accumulators first, then apply
+  // bias, residual Z, and activation cooperatively after one storage barrier.
+  let matrix_c_offset = c_base + (a_global_base + base_A) * N + b_global_base + base_B;
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N +  0u, matC00, N);
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N +  8u, matC01, N);
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N + 16u, matC02, N);
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N + 24u, matC03, N);
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N +  0u, matC10, N);
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N +  8u, matC11, N);
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N + 16u, matC12, N);
+  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N + 24u, matC13, N);
+{% if hasBias or hasActivation or hasZ %}
+  storageBarrier();
+  for (var tile_idx = local_idx; tile_idx < TILE_ROWS * TILE_COLS; tile_idx += {{ workgroupThreadsValue }}u) {
+    let local_row = tile_idx / TILE_COLS;
+    let local_col = tile_idx % TILE_COLS;
+    let global_row = a_global_base + local_row;
+    let global_col = b_global_base + local_col;
+    let y_index = c_base + global_row * N + global_col;
+    var raw = f32(y[y_index]);
+{% if hasBias %}
+    raw += f32(bias[global_row]);
+{% endif %}
+    y[y_index] = {{ T }}(raw);
+  }
+{% endif %}
+{% if padded %}
+    return;
+  }
+{% endif %}
+{% endif %}
+{% if (not useDirectMatrixStore or padded) and not splitKPartial and not fusedNarrowProjection %}
+  // The four scratch banks are reused across the two row-groups, and each is written
+  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers
+  // give the reads visibility of the store AND stop the second row-group's store from
+  // clobbering the first's still-in-flight readback when a partial final M-tile
+  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);
+  workgroupBarrier();
+  let row = sg_id / 4u;
+  let col = (sg_id % 4u) * 2u;
+  let row_base = a_global_base + base_A;
+  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;
+  var row_limit = i32(M) - i32(row_base);
+  storeOutput(matrix_c_offset, {% if hasBias or polyphase %}row_base, {% endif %}row, col, subtile_id, row_limit{% if padded %}, b_global_base + base_B{% endif %});
+  workgroupBarrier();
+
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);
+  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);
+  workgroupBarrier();
+  matrix_c_offset = matrix_c_offset + 8u * N;
+  row_limit = i32(M) - i32(row_base + 8u);
+  storeOutput(matrix_c_offset, {% if hasBias or polyphase %}row_base + 8u, {% endif %}row, col, subtile_id, row_limit{% if padded %}, b_global_base + base_B{% endif %});
+{% endif %}
+}
diff --git a/utils/benchmark/huggingface/conv-variants.json b/utils/benchmark/huggingface/conv-variants.json
new file mode 100644
index 0000000..090add4
--- /dev/null
+++ b/utils/benchmark/huggingface/conv-variants.json
@@ -0,0 +1,19 @@
+{
+  "upstream": "https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja",
+  "revision": "7b19a1ea4fd2abef3203991ca933405f12cfcc62",
+  "sha256": "7eacb50256ee91107af84b0fe0d4fc22c05b880616b7113ba3ccfced037b9c72",
+  "variants": {
+    "1x1-f32-k16-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\n\n@group(0) @binding(0) var<storage, read_write> y: array<f32>;\n@group(0) @binding(1) var<storage, read> xm: array<f32>;\n@group(0) @binding(2) var<storage, read> w: array<f32>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 16u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f32(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f32>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f32>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let xBatchBase = batch * K * N;\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f32>(f32(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f32>(f32(w[aBase]), f32(w[aBase + 1u]), f32(w[aBase + 2u]), f32(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f32(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    for (var linear = li; linear < BK * BN_VECS; linear += WG_SIZE) {\n      let br = linear / BN_VECS;\n      let bc4 = linear % BN_VECS;\n      let bk = kBase + br;\n      let bn = nBase + bc4 * 4u;\n      var bvec = vec4<f32>(f32(0.0));\n      if (bk < K) {\n        let bBase = xBatchBase + bk * N + bn;\n        if (bn + 3u < N) {\n          bvec = vec4<f32>(f32(xm[bBase]), f32(xm[bBase + 1u]), f32(xm[bBase + 2u]), f32(xm[bBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (bn + t < N) {\n              bvec[t] = f32(xm[bBase + t]);\n            }\n          }\n        }\n      }\n      tileB[br][bc4] = bvec;\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "1x1-f32-k32-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\n\n@group(0) @binding(0) var<storage, read_write> y: array<f32>;\n@group(0) @binding(1) var<storage, read> xm: array<f32>;\n@group(0) @binding(2) var<storage, read> w: array<f32>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 32u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f32(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f32>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f32>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let xBatchBase = batch * K * N;\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f32>(f32(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f32>(f32(w[aBase]), f32(w[aBase + 1u]), f32(w[aBase + 2u]), f32(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f32(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    for (var linear = li; linear < BK * BN_VECS; linear += WG_SIZE) {\n      let br = linear / BN_VECS;\n      let bc4 = linear % BN_VECS;\n      let bk = kBase + br;\n      let bn = nBase + bc4 * 4u;\n      var bvec = vec4<f32>(f32(0.0));\n      if (bk < K) {\n        let bBase = xBatchBase + bk * N + bn;\n        if (bn + 3u < N) {\n          bvec = vec4<f32>(f32(xm[bBase]), f32(xm[bBase + 1u]), f32(xm[bBase + 2u]), f32(xm[bBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (bn + t < N) {\n              bvec[t] = f32(xm[bBase + t]);\n            }\n          }\n        }\n      }\n      tileB[br][bc4] = bvec;\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f32-k16-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\n\n@group(0) @binding(0) var<storage, read_write> y: array<f32>;\n@group(0) @binding(1) var<storage, read> xm: array<f32>;\n@group(0) @binding(2) var<storage, read> w: array<f32>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 16u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f32(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f32>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f32>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f32>(f32(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f32>(f32(w[aBase]), f32(w[aBase + 1u]), f32(w[aBase + 2u]), f32(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f32(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 8u;\n    let bChunk = li % 8u;\n    let bLocalK = bChunk * 2u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 2u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 2u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f32>(\n\n          f32(xm[batchBase + u32(carriedAddress.x)]),\n\n          f32(xm[batchBase + u32(carriedAddress.y)]),\n\n          f32(xm[batchBase + u32(carriedAddress.z)]),\n\n          f32(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 2u; i = i + 1u) {\n        var carriedValue = vec4<f32>(f32(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f32(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f32(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f32(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f32(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f32-k32-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\n\n@group(0) @binding(0) var<storage, read_write> y: array<f32>;\n@group(0) @binding(1) var<storage, read> xm: array<f32>;\n@group(0) @binding(2) var<storage, read> w: array<f32>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 32u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f32(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f32>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f32>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f32>(f32(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f32>(f32(w[aBase]), f32(w[aBase + 1u]), f32(w[aBase + 2u]), f32(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f32(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 8u;\n    let bChunk = li % 8u;\n    let bLocalK = bChunk * 4u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 4u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f32>(\n\n          f32(xm[batchBase + u32(carriedAddress.x)]),\n\n          f32(xm[batchBase + u32(carriedAddress.y)]),\n\n          f32(xm[batchBase + u32(carriedAddress.z)]),\n\n          f32(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        var carriedValue = vec4<f32>(f32(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f32(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f32(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f32(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f32(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f32-k16-m32": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\n\n@group(0) @binding(0) var<storage, read_write> y: array<f32>;\n@group(0) @binding(1) var<storage, read> xm: array<f32>;\n@group(0) @binding(2) var<storage, read> w: array<f32>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 16u;\nconst BM: u32 = 32u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 64u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f32(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f32>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f32>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 4, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f32>(f32(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f32>(f32(w[aBase]), f32(w[aBase + 1u]), f32(w[aBase + 2u]), f32(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f32(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 4u;\n    let bChunk = li % 4u;\n    let bLocalK = bChunk * 4u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 4u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f32>(\n\n          f32(xm[batchBase + u32(carriedAddress.x)]),\n\n          f32(xm[batchBase + u32(carriedAddress.y)]),\n\n          f32(xm[batchBase + u32(carriedAddress.z)]),\n\n          f32(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        var carriedValue = vec4<f32>(f32(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f32(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f32(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f32(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f32(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f32-k32-m32": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\n\n@group(0) @binding(0) var<storage, read_write> y: array<f32>;\n@group(0) @binding(1) var<storage, read> xm: array<f32>;\n@group(0) @binding(2) var<storage, read> w: array<f32>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 32u;\nconst BM: u32 = 32u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 64u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f32(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f32>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f32>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 4, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f32>(f32(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f32>(f32(w[aBase]), f32(w[aBase + 1u]), f32(w[aBase + 2u]), f32(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f32(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 4u;\n    let bChunk = li % 4u;\n    let bLocalK = bChunk * 8u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 8u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 8u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f32>(\n\n          f32(xm[batchBase + u32(carriedAddress.x)]),\n\n          f32(xm[batchBase + u32(carriedAddress.y)]),\n\n          f32(xm[batchBase + u32(carriedAddress.z)]),\n\n          f32(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 8u; i = i + 1u) {\n        var carriedValue = vec4<f32>(f32(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f32(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f32(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f32(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f32(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "1x1-f16-k16-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> y: array<f16>;\n@group(0) @binding(1) var<storage, read> xm: array<f16>;\n@group(0) @binding(2) var<storage, read> w: array<f16>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 16u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f16(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f16>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f16>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let xBatchBase = batch * K * N;\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f16>(f16(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f16>(f16(w[aBase]), f16(w[aBase + 1u]), f16(w[aBase + 2u]), f16(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f16(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    for (var linear = li; linear < BK * BN_VECS; linear += WG_SIZE) {\n      let br = linear / BN_VECS;\n      let bc4 = linear % BN_VECS;\n      let bk = kBase + br;\n      let bn = nBase + bc4 * 4u;\n      var bvec = vec4<f16>(f16(0.0));\n      if (bk < K) {\n        let bBase = xBatchBase + bk * N + bn;\n        if (bn + 3u < N) {\n          bvec = vec4<f16>(f16(xm[bBase]), f16(xm[bBase + 1u]), f16(xm[bBase + 2u]), f16(xm[bBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (bn + t < N) {\n              bvec[t] = f16(xm[bBase + t]);\n            }\n          }\n        }\n      }\n      tileB[br][bc4] = bvec;\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "1x1-f16-k32-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> y: array<f16>;\n@group(0) @binding(1) var<storage, read> xm: array<f16>;\n@group(0) @binding(2) var<storage, read> w: array<f16>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 32u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f16(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f16>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f16>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let xBatchBase = batch * K * N;\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f16>(f16(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f16>(f16(w[aBase]), f16(w[aBase + 1u]), f16(w[aBase + 2u]), f16(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f16(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    for (var linear = li; linear < BK * BN_VECS; linear += WG_SIZE) {\n      let br = linear / BN_VECS;\n      let bc4 = linear % BN_VECS;\n      let bk = kBase + br;\n      let bn = nBase + bc4 * 4u;\n      var bvec = vec4<f16>(f16(0.0));\n      if (bk < K) {\n        let bBase = xBatchBase + bk * N + bn;\n        if (bn + 3u < N) {\n          bvec = vec4<f16>(f16(xm[bBase]), f16(xm[bBase + 1u]), f16(xm[bBase + 2u]), f16(xm[bBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (bn + t < N) {\n              bvec[t] = f16(xm[bBase + t]);\n            }\n          }\n        }\n      }\n      tileB[br][bc4] = bvec;\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f16-k16-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> y: array<f16>;\n@group(0) @binding(1) var<storage, read> xm: array<f16>;\n@group(0) @binding(2) var<storage, read> w: array<f16>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 16u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f16(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f16>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f16>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f16>(f16(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f16>(f16(w[aBase]), f16(w[aBase + 1u]), f16(w[aBase + 2u]), f16(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f16(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 8u;\n    let bChunk = li % 8u;\n    let bLocalK = bChunk * 2u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 2u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 2u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f16>(\n\n          f16(xm[batchBase + u32(carriedAddress.x)]),\n\n          f16(xm[batchBase + u32(carriedAddress.y)]),\n\n          f16(xm[batchBase + u32(carriedAddress.z)]),\n\n          f16(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 2u; i = i + 1u) {\n        var carriedValue = vec4<f16>(f16(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f16(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f16(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f16(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f16(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f16-k32-m64": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> y: array<f16>;\n@group(0) @binding(1) var<storage, read> xm: array<f16>;\n@group(0) @binding(2) var<storage, read> w: array<f16>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 32u;\nconst BM: u32 = 64u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 128u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f16(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f16>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f16>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 8, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f16>(f16(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f16>(f16(w[aBase]), f16(w[aBase + 1u]), f16(w[aBase + 2u]), f16(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f16(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 8u;\n    let bChunk = li % 8u;\n    let bLocalK = bChunk * 4u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 4u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f16>(\n\n          f16(xm[batchBase + u32(carriedAddress.x)]),\n\n          f16(xm[batchBase + u32(carriedAddress.y)]),\n\n          f16(xm[batchBase + u32(carriedAddress.z)]),\n\n          f16(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        var carriedValue = vec4<f16>(f16(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f16(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f16(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f16(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f16(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f16-k16-m32": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> y: array<f16>;\n@group(0) @binding(1) var<storage, read> xm: array<f16>;\n@group(0) @binding(2) var<storage, read> w: array<f16>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 16u;\nconst BM: u32 = 32u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 64u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f16(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f16>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f16>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 4, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f16>(f16(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f16>(f16(w[aBase]), f16(w[aBase + 1u]), f16(w[aBase + 2u]), f16(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f16(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 4u;\n    let bChunk = li % 4u;\n    let bLocalK = bChunk * 4u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 4u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f16>(\n\n          f16(xm[batchBase + u32(carriedAddress.x)]),\n\n          f16(xm[batchBase + u32(carriedAddress.y)]),\n\n          f16(xm[batchBase + u32(carriedAddress.z)]),\n\n          f16(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 4u; i = i + 1u) {\n        var carriedValue = vec4<f16>(f16(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f16(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f16(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f16(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f16(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}",
+    "3x3-f16-k32-m32": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-gemm-tiled-reg.wgsl.jinja\n// Upstream Apache-2.0; integration MIT (https://github.com/barhanc/wgpu-executorch).\n// Register-blocked batched matrix product:\n// C[b] (M x N) = A (M x K) * B[b] (K x N). Workgroup lanes compute TM x TN\n// micro-tiles. The defaults use a 16x8 lane grid with an 8x4 micro-tile over a\n// 64x64 output tile. A is shared across the batch; B and C use the dispatch.z\n// batch offset. Accumulation is f32; an optional epilogue applies configured\n// bias, residual, and activation terms in the accumulator domain on store.\n// Every matrix dimension is bounds-checked.\n// f16 operands remain packed in workgroup memory and widen only at the FMA site;\n// the f32 accumulation order is retained while shared traffic is halved.\n//\n// Both shared tiles are stored as vec4 groups along the axis each lane consumes\n// contiguously: tileA groups four K values for one output row, tileB groups four\n// N columns for one K. One micro-tile step therefore reads TM + 4 vector words\n// instead of 4 * (TM + TN) scalars, so a shared word feeds four times as many\n// FMAs and the K loop runs four accumulation steps per iteration.\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> y: array<f16>;\n@group(0) @binding(1) var<storage, read> xm: array<f16>;\n@group(0) @binding(2) var<storage, read> w: array<f16>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\nstruct Params { M: u32, K: u32, N: u32, has_bias: u32 }\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n\n\n\n\n\n\n\n\nconst BK: u32 = 32u;\nconst BM: u32 = 32u;\nconst BN: u32 = 64u;\nconst TM: u32 = 8u;\nconst TN: u32 = 4u;\nconst WG_X: u32 = 16u;\nconst WG_SIZE: u32 = 64u;\n// Vector words per tile row: A groups K, B groups N.\nconst AK_VECS: u32 = BK / 4u;\nconst BN_VECS: u32 = BN / 4u;\n\n// implicitIm2col leaves B unmaterialized. While staging a tile, the kernel\n// decodes each (k, n) column-matrix coordinate into a raw NCHW input address.\n// Overlapping windows may reread input values, trading address arithmetic and\n// repeated input loads for writing and rereading an expanded column matrix.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: u32 = 1u;\noverride CONV_IN_W: u32 = 1u;\noverride CONV_OUT_W: u32 = 1u;\noverride CONV_IN_CHANNELS: u32 = 1u;\n\n\n\nfn store_out(m: u32, n: u32, yBase: u32, raw: f32) {\n  if (m >= params.M || n >= params.N) {\n    return;\n  }\n  var v = raw;\n\n  if (params.has_bias != 0u) { v = v + f32(bias[m]); }\n\n  y[yBase + m * params.N + n] = f16(v);\n}\n\n\nvar<workgroup> tileA: array<array<vec4<f16>, AK_VECS>, BM>;\nvar<workgroup> tileB: array<array<vec4<f16>, BN_VECS>, BK>;\n\n\n\n\n\n@compute @workgroup_size(16, 4, 1)\nfn main(\n  @builtin(workgroup_id) wg: vec3<u32>,\n  @builtin(local_invocation_id) lid: vec3<u32>\n) {\n  let M = params.M;\n  let K = params.K;\n  let N = params.N;\n  let mBase = wg.y * BM;\n  let nBase = wg.x * BN;\n\n  let batch = wg.z;\n\n\n  let li = lid.y * WG_X + lid.x;\n\n  // The statically named accumulator vectors form TM independent FMA chains.\n\n  var acc0 = vec4<f32>(0.0);\n\n  var acc1 = vec4<f32>(0.0);\n\n  var acc2 = vec4<f32>(0.0);\n\n  var acc3 = vec4<f32>(0.0);\n\n  var acc4 = vec4<f32>(0.0);\n\n  var acc5 = vec4<f32>(0.0);\n\n  var acc6 = vec4<f32>(0.0);\n\n  var acc7 = vec4<f32>(0.0);\n\n\n\n  let numTiles = (K + BK - 1u) / BK;\n\n  for (var kt: u32 = 0u; kt < numTiles; kt = kt + 1u) {\n\n    let kBase = kt * BK;\n\n\n    for (var linear = li; linear < BM * AK_VECS; linear += WG_SIZE) {\n      let ar = linear / AK_VECS;\n      let ac4 = linear % AK_VECS;\n      let am = mBase + ar;\n      let ak = kBase + ac4 * 4u;\n      var av = vec4<f16>(f16(0.0));\n      if (am < M) {\n        let aBase = am * K + ak;\n        if (ak + 3u < K) {\n          av = vec4<f16>(f16(w[aBase]), f16(w[aBase + 1u]), f16(w[aBase + 2u]), f16(w[aBase + 3u]));\n        } else {\n          for (var t = 0u; t < 4u; t = t + 1u) {\n            if (ak + t < K) {\n              av[t] = f16(w[aBase + t]);\n            }\n          }\n        }\n      }\n      tileA[ar][ac4] = av;\n    }\n\n\n    let bColVec = li / 4u;\n    let bChunk = li % 4u;\n    let bLocalK = bChunk * 8u;\n    let bStartK = kBase + bLocalK;\n    let bCol0 = nBase + bColVec * 4u;\n    let bCols = vec4<u32>(bCol0, bCol0 + 1u, bCol0 + 2u, bCol0 + 3u);\n    let inColumn = bCols < vec4<u32>(N);\n    let ih0 = vec4<i32>((bCols / vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_H) - vec4<i32>(CONV_PAD_TOP);\n    let iw0 = vec4<i32>((bCols % vec4<u32>(CONV_OUT_W)) * CONV_STRIDE_W) - vec4<i32>(CONV_PAD_LEFT);\n    var carriedK = bStartK;\n    var carriedIc = carriedK / CONV_KSIZE;\n    let carriedKq = carriedK % CONV_KSIZE;\n    var carriedKh = carriedKq / CONV_KERNEL_W;\n    var carriedKw = carriedKq % CONV_KERNEL_W;\n    var carriedIh = ih0 + vec4<i32>(i32(carriedKh * CONV_DILATION_H));\n    var carriedIw = iw0 + vec4<i32>(i32(carriedKw * CONV_DILATION_W));\n\n    // Interior words can carry four addresses. Padding, the N tail, and the\n    // final K tile retain the coordinate-checked loop below and publish exact\n    // zeros.\n    let interior = all(inColumn)\n      && bStartK + 8u <= K\n      && all(ih0 >= vec4<i32>(0))\n      && all(ih0 + vec4<i32>(i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H)) < vec4<i32>(i32(CONV_IN_H)))\n      && all(iw0 >= vec4<i32>(0))\n      && all(iw0 + vec4<i32>(i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W)) < vec4<i32>(i32(CONV_IN_W)));\n    if (interior) {\n      let batchBase = batch * CONV_IN_CHANNELS * CONV_IN_H * CONV_IN_W;\n      let colStep = i32(CONV_DILATION_W);\n      let rowStep = i32(CONV_DILATION_H * CONV_IN_W);\n      let planeStep = i32(CONV_IN_H * CONV_IN_W);\n      let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n      let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n      var carriedAddress = vec4<i32>(i32(carriedIc) * planeStep) + carriedIh * vec4<i32>(i32(CONV_IN_W)) + carriedIw;\n      for (var i = 0u; i < 8u; i = i + 1u) {\n        tileB[bLocalK + i][bColVec] = vec4<f16>(\n\n          f16(xm[batchBase + u32(carriedAddress.x)]),\n\n          f16(xm[batchBase + u32(carriedAddress.y)]),\n\n          f16(xm[batchBase + u32(carriedAddress.z)]),\n\n          f16(xm[batchBase + u32(carriedAddress.w)])\n\n        );\n        carriedAddress = carriedAddress + vec4<i32>(colStep);\n        carriedKw = carriedKw + 1u;\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedAddress = carriedAddress - vec4<i32>(kwWrap);\n          carriedKh = carriedKh + 1u;\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedAddress = carriedAddress - vec4<i32>(khWrap);\n          }\n        }\n      }\n    } else {\n      for (var i = 0u; i < 8u; i = i + 1u) {\n        var carriedValue = vec4<f16>(f16(0.0));\n        let carriedRow = (batch * CONV_IN_CHANNELS + carriedIc) * CONV_IN_H;\n        let carriedOk = inColumn\n          & (carriedIh >= vec4<i32>(0)) & (carriedIh < vec4<i32>(i32(CONV_IN_H)))\n          & (carriedIw >= vec4<i32>(0)) & (carriedIw < vec4<i32>(i32(CONV_IN_W)));\n        if (carriedK < K) {\n\n          if (carriedOk.x) {\n            carriedValue.x = f16(xm[(carriedRow + u32(carriedIh.x)) * CONV_IN_W + u32(carriedIw.x)]);\n          }\n\n          if (carriedOk.y) {\n            carriedValue.y = f16(xm[(carriedRow + u32(carriedIh.y)) * CONV_IN_W + u32(carriedIw.y)]);\n          }\n\n          if (carriedOk.z) {\n            carriedValue.z = f16(xm[(carriedRow + u32(carriedIh.z)) * CONV_IN_W + u32(carriedIw.z)]);\n          }\n\n          if (carriedOk.w) {\n            carriedValue.w = f16(xm[(carriedRow + u32(carriedIh.w)) * CONV_IN_W + u32(carriedIw.w)]);\n          }\n\n        }\n        tileB[bLocalK + i][bColVec] = carriedValue;\n        carriedK = carriedK + 1u;\n        carriedKw = carriedKw + 1u;\n        carriedIw = carriedIw + vec4<i32>(i32(CONV_DILATION_W));\n        if (carriedKw == CONV_KERNEL_W) {\n          carriedKw = 0u;\n          carriedIw = iw0;\n          carriedKh = carriedKh + 1u;\n          carriedIh = carriedIh + vec4<i32>(i32(CONV_DILATION_H));\n          if (carriedKh == CONV_KERNEL_H) {\n            carriedKh = 0u;\n            carriedIh = ih0;\n            carriedIc = carriedIc + 1u;\n          }\n        }\n      }\n    }\n\n    workgroupBarrier();\n    // One iteration consumes four K steps: TM vector words of A and four of B\n    // cover TM x TN x 4 FMAs.\n    let aRow = lid.y * TM;\n    for (var kv: u32 = 0u; kv < AK_VECS; kv = kv + 1u) {\n\n      let av0 = vec4<f32>(tileA[aRow + 0u][kv]);\n\n      let av1 = vec4<f32>(tileA[aRow + 1u][kv]);\n\n      let av2 = vec4<f32>(tileA[aRow + 2u][kv]);\n\n      let av3 = vec4<f32>(tileA[aRow + 3u][kv]);\n\n      let av4 = vec4<f32>(tileA[aRow + 4u][kv]);\n\n      let av5 = vec4<f32>(tileA[aRow + 5u][kv]);\n\n      let av6 = vec4<f32>(tileA[aRow + 6u][kv]);\n\n      let av7 = vec4<f32>(tileA[aRow + 7u][kv]);\n\n\n      let bv0 = vec4<f32>(tileB[kv * 4u + 0u][lid.x]);\n\n      acc0 += vec4<f32>(av0.x) * bv0;\n\n      acc1 += vec4<f32>(av1.x) * bv0;\n\n      acc2 += vec4<f32>(av2.x) * bv0;\n\n      acc3 += vec4<f32>(av3.x) * bv0;\n\n      acc4 += vec4<f32>(av4.x) * bv0;\n\n      acc5 += vec4<f32>(av5.x) * bv0;\n\n      acc6 += vec4<f32>(av6.x) * bv0;\n\n      acc7 += vec4<f32>(av7.x) * bv0;\n\n\n      let bv1 = vec4<f32>(tileB[kv * 4u + 1u][lid.x]);\n\n      acc0 += vec4<f32>(av0.y) * bv1;\n\n      acc1 += vec4<f32>(av1.y) * bv1;\n\n      acc2 += vec4<f32>(av2.y) * bv1;\n\n      acc3 += vec4<f32>(av3.y) * bv1;\n\n      acc4 += vec4<f32>(av4.y) * bv1;\n\n      acc5 += vec4<f32>(av5.y) * bv1;\n\n      acc6 += vec4<f32>(av6.y) * bv1;\n\n      acc7 += vec4<f32>(av7.y) * bv1;\n\n\n      let bv2 = vec4<f32>(tileB[kv * 4u + 2u][lid.x]);\n\n      acc0 += vec4<f32>(av0.z) * bv2;\n\n      acc1 += vec4<f32>(av1.z) * bv2;\n\n      acc2 += vec4<f32>(av2.z) * bv2;\n\n      acc3 += vec4<f32>(av3.z) * bv2;\n\n      acc4 += vec4<f32>(av4.z) * bv2;\n\n      acc5 += vec4<f32>(av5.z) * bv2;\n\n      acc6 += vec4<f32>(av6.z) * bv2;\n\n      acc7 += vec4<f32>(av7.z) * bv2;\n\n\n      let bv3 = vec4<f32>(tileB[kv * 4u + 3u][lid.x]);\n\n      acc0 += vec4<f32>(av0.w) * bv3;\n\n      acc1 += vec4<f32>(av1.w) * bv3;\n\n      acc2 += vec4<f32>(av2.w) * bv3;\n\n      acc3 += vec4<f32>(av3.w) * bv3;\n\n      acc4 += vec4<f32>(av4.w) * bv3;\n\n      acc5 += vec4<f32>(av5.w) * bv3;\n\n      acc6 += vec4<f32>(av6.w) * bv3;\n\n      acc7 += vec4<f32>(av7.w) * bv3;\n\n\n    }\n    workgroupBarrier();\n  }\n\n\n  let yBatchBase = batch * M * N;\n  let m0 = mBase + lid.y * TM;\n  let n0 = nBase + lid.x * TN;\n\n\n\n\n\n  store_out(m0 + 0u, n0 + 0u, yBatchBase, acc0.x);\n\n\n\n  store_out(m0 + 0u, n0 + 1u, yBatchBase, acc0.y);\n\n\n\n  store_out(m0 + 0u, n0 + 2u, yBatchBase, acc0.z);\n\n\n\n  store_out(m0 + 0u, n0 + 3u, yBatchBase, acc0.w);\n\n\n\n\n\n\n  store_out(m0 + 1u, n0 + 0u, yBatchBase, acc1.x);\n\n\n\n  store_out(m0 + 1u, n0 + 1u, yBatchBase, acc1.y);\n\n\n\n  store_out(m0 + 1u, n0 + 2u, yBatchBase, acc1.z);\n\n\n\n  store_out(m0 + 1u, n0 + 3u, yBatchBase, acc1.w);\n\n\n\n\n\n\n  store_out(m0 + 2u, n0 + 0u, yBatchBase, acc2.x);\n\n\n\n  store_out(m0 + 2u, n0 + 1u, yBatchBase, acc2.y);\n\n\n\n  store_out(m0 + 2u, n0 + 2u, yBatchBase, acc2.z);\n\n\n\n  store_out(m0 + 2u, n0 + 3u, yBatchBase, acc2.w);\n\n\n\n\n\n\n  store_out(m0 + 3u, n0 + 0u, yBatchBase, acc3.x);\n\n\n\n  store_out(m0 + 3u, n0 + 1u, yBatchBase, acc3.y);\n\n\n\n  store_out(m0 + 3u, n0 + 2u, yBatchBase, acc3.z);\n\n\n\n  store_out(m0 + 3u, n0 + 3u, yBatchBase, acc3.w);\n\n\n\n\n\n\n  store_out(m0 + 4u, n0 + 0u, yBatchBase, acc4.x);\n\n\n\n  store_out(m0 + 4u, n0 + 1u, yBatchBase, acc4.y);\n\n\n\n  store_out(m0 + 4u, n0 + 2u, yBatchBase, acc4.z);\n\n\n\n  store_out(m0 + 4u, n0 + 3u, yBatchBase, acc4.w);\n\n\n\n\n\n\n  store_out(m0 + 5u, n0 + 0u, yBatchBase, acc5.x);\n\n\n\n  store_out(m0 + 5u, n0 + 1u, yBatchBase, acc5.y);\n\n\n\n  store_out(m0 + 5u, n0 + 2u, yBatchBase, acc5.z);\n\n\n\n  store_out(m0 + 5u, n0 + 3u, yBatchBase, acc5.w);\n\n\n\n\n\n\n  store_out(m0 + 6u, n0 + 0u, yBatchBase, acc6.x);\n\n\n\n  store_out(m0 + 6u, n0 + 1u, yBatchBase, acc6.y);\n\n\n\n  store_out(m0 + 6u, n0 + 2u, yBatchBase, acc6.z);\n\n\n\n  store_out(m0 + 6u, n0 + 3u, yBatchBase, acc6.w);\n\n\n\n\n\n\n  store_out(m0 + 7u, n0 + 0u, yBatchBase, acc7.x);\n\n\n\n  store_out(m0 + 7u, n0 + 1u, yBatchBase, acc7.y);\n\n\n\n  store_out(m0 + 7u, n0 + 2u, yBatchBase, acc7.z);\n\n\n\n  store_out(m0 + 7u, n0 + 3u, yBatchBase, acc7.w);\n\n\n}"
+  }
+}
diff --git a/utils/benchmark/huggingface/matrix-variants.json b/utils/benchmark/huggingface/matrix-variants.json
new file mode 100644
index 0000000..8958ed9
--- /dev/null
+++ b/utils/benchmark/huggingface/matrix-variants.json
@@ -0,0 +1,15 @@
+{
+  "upstream": "https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja",
+  "revision": "7b19a1ea4fd2abef3203991ca933405f12cfcc62",
+  "sha256": "fccfc351a2c3936ac10a88cbc62798431421a4c7a2efd9afe22334b21c096e5f",
+  "variants": {
+    "1x1-f32-shared": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f32>;\n    @group(0) @binding(1) var<storage, read> xm: array<f32>;\n    @group(0) @binding(2) var<storage, read> w: array<f32>;\n    @group(0) @binding(3) var<storage, read> bias: array<f32>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\n\n\noverride B_BATCH_STRIDE: u32 = K * N;\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 32u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\nvar<workgroup> tile_A: array<f32, 32 * 32>;\nvar<workgroup> tile_B: array<f32, 64 * 32>;\n\n\nvar<workgroup> scratch: array<array<array<f32, 64>, 4>, 4>;\n\n\n\nfn loadSHMA(tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let a_global = tile_base + row;\n  let col = c_idx * 8u;\n  for (var col_offset = 0u; col_offset < 8u; col_offset = col_offset + 1u) {\n    let k = k_idx + col + col_offset;\n    if (a_global < M) {\n\n\n      tile_A[row * TILE_K + col + col_offset] = f32(w[a_global * K + k]);\n\n    } else {\n\n      tile_A[row * TILE_K + col + col_offset] = 0.0;\n\n    }\n  }\n}\n\nfn loadSHMB(b_base: u32, tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let b_col = tile_base + row;\n  let col = c_idx * 16u;\n\n  for (var i = 0u; i < 16u; i = i + 1u) {\n    let k = k_idx + col + i;\n\n    tile_B[row * TILE_K + col + i] = f32(xm[b_base + k * N + b_col]);\n\n  }\n\n}\n\n\n\n\n\n\nfn storeOutput(offset: u32, row_base: u32, row: u32, col: u32, src_slot: u32, row_limit: i32) {\n  if (row_limit > 0 && row < u32(row_limit)) {\n    let col2 = col + 1u;\n\n    var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }\n\n\n    y[offset + row * N + col]       = \n\nf32(scratch[src_slot][0][row * 8u + col] + bv);\n    y[offset + row * N + col + 8u]  = \n\nf32(scratch[src_slot][1][row * 8u + col] + bv);\n    y[offset + row * N + col + 16u] = \n\nf32(scratch[src_slot][2][row * 8u + col] + bv);\n    y[offset + row * N + col + 24u] = \n\nf32(scratch[src_slot][3][row * 8u + col] + bv);\n\n    y[offset + row * N + col2]       = \n\nf32(scratch[src_slot][0][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 8u]  = \n\nf32(scratch[src_slot][1][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 16u] = \n\nf32(scratch[src_slot][2][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 24u] = \n\nf32(scratch[src_slot][3][row * 8u + col2] + bv);\n\n  }\n}\n\n\n@compute @workgroup_size(128, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_invocation_id) sg_id: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 2u;\n  let subtile_idy = subtile_id % 2u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K; kidx = kidx + TILE_K) {\n\n\n    loadSHMA(a_global_base, kidx, local_idx / 4u, local_idx % 4u);\n    loadSHMB(b_base, b_global_base, kidx, local_idx / 2u, local_idx % 2u);\n    workgroupBarrier();\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = subtile_idy * SUB_ROWS * TILE_K + step;\n\n      var matA0: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&tile_A, matrix_a_offset, TILE_K);\n\n      var matA1: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&tile_A, matrix_a_offset + 8u * TILE_K, TILE_K);\n\n\n      let matrix_b_offset = subtile_idx * SUB_COLS * TILE_K + step;\n\n      var matB0: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset, TILE_K);\n\n      var matB1: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 8u * TILE_K, TILE_K);\n\n      var matB2: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 16u * TILE_K, TILE_K);\n\n      var matB3: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 24u * TILE_K, TILE_K);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n    workgroupBarrier();\n\n  }\n\n\n\n  // The four scratch banks are reused across the two row-groups, and each is written\n  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers\n  // give the reads visibility of the store AND stop the second row-group's store from\n  // clobbering the first's still-in-flight readback when a partial final M-tile\n  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);\n  workgroupBarrier();\n  let row = sg_id / 4u;\n  let col = (sg_id % 4u) * 2u;\n  let row_base = a_global_base + base_A;\n  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;\n  var row_limit = i32(M) - i32(row_base);\n  storeOutput(matrix_c_offset, row_base, row, col, subtile_id, row_limit);\n  workgroupBarrier();\n\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);\n  workgroupBarrier();\n  matrix_c_offset = matrix_c_offset + 8u * N;\n  row_limit = i32(M) - i32(row_base + 8u);\n  storeOutput(matrix_c_offset, row_base + 8u, row, col, subtile_id, row_limit);\n\n}",
+    "1x1-f32-direct": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f32>;\n    @group(0) @binding(1) var<storage, read> xm: array<f32>;\n    @group(0) @binding(2) var<storage, read> w: array<f32>;\n    @group(0) @binding(3) var<storage, read> bias: array<f32>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\n\n\noverride B_BATCH_STRIDE: u32 = K * N;\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 64u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\n\n\n\n\n\n\n\n@compute @workgroup_size(256, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 4u;\n  let subtile_idy = subtile_id % 4u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K; kidx = kidx + TILE_K) {\n\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = (a_global_base + subtile_idy * SUB_ROWS) * K + kidx + step;\n\n      var matA0: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&w, matrix_a_offset, K);\n\n      var matA1: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&w, matrix_a_offset + 8u * K, K);\n\n\n      let matrix_b_offset = b_base + (kidx + step) * N + b_global_base + subtile_idx * SUB_COLS;\n\n      var matB0: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, row_major>(&xm, matrix_b_offset, N);\n\n      var matB1: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, row_major>(&xm, matrix_b_offset + 8u, N);\n\n      var matB2: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, row_major>(&xm, matrix_b_offset + 16u, N);\n\n      var matB3: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, row_major>(&xm, matrix_b_offset + 24u, N);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n  }\n\n\n\n  // Full f32 output tiles can be published by the subgroup-matrix collectives\n  // directly. With no epilogue this removes scratch traffic and three barriers.\n  // When an epilogue is present, publish the raw accumulators first, then apply\n  // bias, residual Z, and activation cooperatively after one storage barrier.\n  let matrix_c_offset = c_base + (a_global_base + base_A) * N + b_global_base + base_B;\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N +  0u, matC00, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N +  8u, matC01, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N + 16u, matC02, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N + 24u, matC03, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N +  0u, matC10, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N +  8u, matC11, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N + 16u, matC12, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N + 24u, matC13, N);\n\n  storageBarrier();\n  for (var tile_idx = local_idx; tile_idx < TILE_ROWS * TILE_COLS; tile_idx += 256u) {\n    let local_row = tile_idx / TILE_COLS;\n    let local_col = tile_idx % TILE_COLS;\n    let global_row = a_global_base + local_row;\n    let global_col = b_global_base + local_col;\n    let y_index = c_base + global_row * N + global_col;\n    var raw = f32(y[y_index]);\n\n    if (params.has_bias != 0u) { raw += f32(bias[global_row]); }\n\n    y[y_index] = f32(raw);\n  }\n\n\n\n\n}",
+    "3x3-f32-shared": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f32>;\n    @group(0) @binding(1) var<storage, read> xm: array<f32>;\n    @group(0) @binding(2) var<storage, read> w: array<f32>;\n    @group(0) @binding(3) var<storage, read> bias: array<f32>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride CONV_IN_CHANNELS: u32 = 1u;\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\noverride K_LOOP: u32 = 32u;\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\n\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\n\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: i32 = 1;\noverride CONV_IN_W: i32 = 1;\noverride CONV_OUT_W: u32 = 1u;\n\n// X is [batch, inChannels, inH, inW]; the tile gather indexes it directly.\noverride B_BATCH_STRIDE: u32 = CONV_IN_CHANNELS * u32(CONV_IN_H) * u32(CONV_IN_W);\n\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 32u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\nvar<workgroup> tile_A: array<f32, 32 * 32>;\nvar<workgroup> tile_B: array<f32, 64 * 32>;\n\n\nvar<workgroup> scratch: array<array<array<f32, 64>, 4>, 4>;\n\n\n\nfn loadSHMA(tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let a_global = tile_base + row;\n  let col = c_idx * 8u;\n  for (var col_offset = 0u; col_offset < 8u; col_offset = col_offset + 1u) {\n    let k = k_idx + col + col_offset;\n    if (a_global < M && k < K) {\n\n\n      tile_A[row * TILE_K + col + col_offset] = f32(w[a_global * K + k]);\n\n    } else {\n\n      tile_A[row * TILE_K + col + col_offset] = 0.0;\n\n    }\n  }\n}\n\nfn loadSHMB(b_base: u32, tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let b_col = tile_base + row;\n  let col = c_idx * 16u;\n\n  // One output position per tile column, so its window origin is loop-invariant.\n\n  let ih0 = i32((b_col / CONV_OUT_W) * CONV_STRIDE_H) - CONV_PAD_TOP;\n\n  let iw0 = i32((b_col % CONV_OUT_W) * CONV_STRIDE_W) - CONV_PAD_LEFT;\n  let in_column = b_col < N;\n  // k advances by exactly one per element, so the (in-channel, tap-row, tap-col)\n  // decomposition is CARRIED across the loop instead of recomputed: two divisions\n  // and two moduli per loaded element become one increment and one compare, with\n  // the source coordinates advanced by the dilation in step. Only the entry values\n  // divide, and their divisors are compile-time literals.\n  var k = k_idx + col;\n  var ic = k / CONV_KSIZE;\n  var kq = k % CONV_KSIZE;\n\n  var kh = kq / CONV_KERNEL_W;\n  var kw = kq % CONV_KERNEL_W;\n\n  var ih = ih0 + i32(kh * CONV_DILATION_H);\n  var iw = iw0 + i32(kw * CONV_DILATION_W);\n  // A tile column whose whole kernel window and K span are in bounds cannot\n  // take any of the element guards below. Hoist them into one uniform test so\n  // the interior loop carries a plain address instead of recomputing coordinates.\n  let interior = in_column\n    && k_idx + col + 16u <= K\n\n    && ih0 >= 0 && ih0 + i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H) < CONV_IN_H\n    && iw0 >= 0 && iw0 + i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W) < CONV_IN_W;\n  if (interior) {\n    let colStep = i32(CONV_DILATION_W);\n    let rowStep = i32(CONV_DILATION_H) * CONV_IN_W;\n\n    let planeStep = CONV_IN_H * CONV_IN_W;\n\n    // Advancing k already added one colStep, so each wrap rewinds that plus the taps it walked.\n    let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n\n    let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n    var addr = i32(b_base) + i32(ic) * planeStep + ih * CONV_IN_W + iw;\n\n    for (var i = 0u; i < 16u; i = i + 1u) {\n      tile_B[row * TILE_K + col + i] = f32(xm[u32(addr)]);\n      addr = addr + colStep;\n      kw = kw + 1u;\n      if (kw == CONV_KERNEL_W) {\n        kw = 0u;\n        addr = addr - kwWrap;\n        kh = kh + 1u;\n        if (kh == CONV_KERNEL_H) {\n          kh = 0u;\n          addr = addr - khWrap;\n\n        }\n      }\n    }\n    return;\n  }\n  for (var i = 0u; i < 16u; i = i + 1u) {\n    var value = f32(0.0);\n    // The K and N tails read as exact zeros, exactly as the materialized padded\n    // cols buffer does, so they contribute nothing to the dot product.\n    if (in_column && k < K && ih >= 0 && ih < CONV_IN_H && iw >= 0 && iw < CONV_IN_W) {\n\n      value = f32(xm[b_base + (ic * u32(CONV_IN_H) + u32(ih)) * u32(CONV_IN_W) + u32(iw)]);\n\n    }\n    tile_B[row * TILE_K + col + i] = value;\n    k = k + 1u;\n    kw = kw + 1u;\n    iw = iw + i32(CONV_DILATION_W);\n    if (kw == CONV_KERNEL_W) {\n      kw = 0u;\n      iw = iw0;\n      kh = kh + 1u;\n      ih = ih + i32(CONV_DILATION_H);\n      if (kh == CONV_KERNEL_H) {\n        kh = 0u;\n        ih = ih0;\n\n        ic = ic + 1u;\n\n      }\n    }\n  }\n\n}\n\n\n\n\n\n\nfn storeOutput(offset: u32, row_base: u32, row: u32, col: u32, src_slot: u32, row_limit: i32, col_anchor: u32) {\n  if (row_limit > 0 && row < u32(row_limit)) {\n    let col2 = col + 1u;\n\n    var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }\n\n\n    // Padded GEMM: the last column tile runs past the logical N; only write\n    // columns inside the real output. Each subgroup-matrix column maps to a\n    // distinct y column (anchor + local), so the guards are independent.\n    if (col_anchor + col +  0u < N) { y[offset + row * N + col]        = \n\nf32(scratch[src_slot][0][row * 8u + col] + bv); }\n    if (col_anchor + col +  8u < N) { y[offset + row * N + col +  8u]  = \n\nf32(scratch[src_slot][1][row * 8u + col] + bv); }\n    if (col_anchor + col + 16u < N) { y[offset + row * N + col + 16u]  = \n\nf32(scratch[src_slot][2][row * 8u + col] + bv); }\n    if (col_anchor + col + 24u < N) { y[offset + row * N + col + 24u]  = \n\nf32(scratch[src_slot][3][row * 8u + col] + bv); }\n    if (col_anchor + col2 +  0u < N) { y[offset + row * N + col2]       = \n\nf32(scratch[src_slot][0][row * 8u + col2] + bv); }\n    if (col_anchor + col2 +  8u < N) { y[offset + row * N + col2 +  8u] = \n\nf32(scratch[src_slot][1][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 16u < N) { y[offset + row * N + col2 + 16u] = \n\nf32(scratch[src_slot][2][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 24u < N) { y[offset + row * N + col2 + 24u] = \n\nf32(scratch[src_slot][3][row * 8u + col2] + bv); }\n\n  }\n}\n\n\n@compute @workgroup_size(128, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_invocation_id) sg_id: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 2u;\n  let subtile_idy = subtile_id % 2u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K_LOOP; kidx = kidx + TILE_K) {\n\n\n    loadSHMA(a_global_base, kidx, local_idx / 4u, local_idx % 4u);\n    loadSHMB(b_base, b_global_base, kidx, local_idx / 2u, local_idx % 2u);\n    workgroupBarrier();\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = subtile_idy * SUB_ROWS * TILE_K + step;\n\n      var matA0: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&tile_A, matrix_a_offset, TILE_K);\n\n      var matA1: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&tile_A, matrix_a_offset + 8u * TILE_K, TILE_K);\n\n\n      let matrix_b_offset = subtile_idx * SUB_COLS * TILE_K + step;\n\n      var matB0: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset, TILE_K);\n\n      var matB1: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 8u * TILE_K, TILE_K);\n\n      var matB2: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 16u * TILE_K, TILE_K);\n\n      var matB3: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 24u * TILE_K, TILE_K);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n    workgroupBarrier();\n\n  }\n\n\n\n  // The four scratch banks are reused across the two row-groups, and each is written\n  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers\n  // give the reads visibility of the store AND stop the second row-group's store from\n  // clobbering the first's still-in-flight readback when a partial final M-tile\n  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);\n  workgroupBarrier();\n  let row = sg_id / 4u;\n  let col = (sg_id % 4u) * 2u;\n  let row_base = a_global_base + base_A;\n  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;\n  var row_limit = i32(M) - i32(row_base);\n  storeOutput(matrix_c_offset, row_base, row, col, subtile_id, row_limit, b_global_base + base_B);\n  workgroupBarrier();\n\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);\n  workgroupBarrier();\n  matrix_c_offset = matrix_c_offset + 8u * N;\n  row_limit = i32(M) - i32(row_base + 8u);\n  storeOutput(matrix_c_offset, row_base + 8u, row, col, subtile_id, row_limit, b_global_base + base_B);\n\n}",
+    "3x3-f32-direct": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f32>;\n    @group(0) @binding(1) var<storage, read> xm: array<f32>;\n    @group(0) @binding(2) var<storage, read> w: array<f32>;\n    @group(0) @binding(3) var<storage, read> bias: array<f32>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride CONV_IN_CHANNELS: u32 = 1u;\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\noverride K_LOOP: u32 = 32u;\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\n\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\n\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: i32 = 1;\noverride CONV_IN_W: i32 = 1;\noverride CONV_OUT_W: u32 = 1u;\n\n// X is [batch, inChannels, inH, inW]; the tile gather indexes it directly.\noverride B_BATCH_STRIDE: u32 = CONV_IN_CHANNELS * u32(CONV_IN_H) * u32(CONV_IN_W);\n\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 64u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\nvar<workgroup> tile_A: array<f32, 64 * 32>;\nvar<workgroup> tile_B: array<f32, 64 * 32>;\n\n\nvar<workgroup> scratch: array<array<array<f32, 64>, 4>, 8>;\n\n\n\nfn loadSHMA(tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let a_global = tile_base + row;\n  let col = c_idx * 8u;\n  for (var col_offset = 0u; col_offset < 8u; col_offset = col_offset + 1u) {\n    let k = k_idx + col + col_offset;\n    if (a_global < M && k < K) {\n\n\n      tile_A[row * TILE_K + col + col_offset] = f32(w[a_global * K + k]);\n\n    } else {\n\n      tile_A[row * TILE_K + col + col_offset] = 0.0;\n\n    }\n  }\n}\n\nfn loadSHMB(b_base: u32, tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let b_col = tile_base + row;\n  let col = c_idx * 8u;\n\n  // One output position per tile column, so its window origin is loop-invariant.\n\n  let ih0 = i32((b_col / CONV_OUT_W) * CONV_STRIDE_H) - CONV_PAD_TOP;\n\n  let iw0 = i32((b_col % CONV_OUT_W) * CONV_STRIDE_W) - CONV_PAD_LEFT;\n  let in_column = b_col < N;\n  // k advances by exactly one per element, so the (in-channel, tap-row, tap-col)\n  // decomposition is CARRIED across the loop instead of recomputed: two divisions\n  // and two moduli per loaded element become one increment and one compare, with\n  // the source coordinates advanced by the dilation in step. Only the entry values\n  // divide, and their divisors are compile-time literals.\n  var k = k_idx + col;\n  var ic = k / CONV_KSIZE;\n  var kq = k % CONV_KSIZE;\n\n  var kh = kq / CONV_KERNEL_W;\n  var kw = kq % CONV_KERNEL_W;\n\n  var ih = ih0 + i32(kh * CONV_DILATION_H);\n  var iw = iw0 + i32(kw * CONV_DILATION_W);\n  // A tile column whose whole kernel window and K span are in bounds cannot\n  // take any of the element guards below. Hoist them into one uniform test so\n  // the interior loop carries a plain address instead of recomputing coordinates.\n  let interior = in_column\n    && k_idx + col + 8u <= K\n\n    && ih0 >= 0 && ih0 + i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H) < CONV_IN_H\n    && iw0 >= 0 && iw0 + i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W) < CONV_IN_W;\n  if (interior) {\n    let colStep = i32(CONV_DILATION_W);\n    let rowStep = i32(CONV_DILATION_H) * CONV_IN_W;\n\n    let planeStep = CONV_IN_H * CONV_IN_W;\n\n    // Advancing k already added one colStep, so each wrap rewinds that plus the taps it walked.\n    let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n\n    let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n    var addr = i32(b_base) + i32(ic) * planeStep + ih * CONV_IN_W + iw;\n\n    for (var i = 0u; i < 8u; i = i + 1u) {\n      tile_B[row * TILE_K + col + i] = f32(xm[u32(addr)]);\n      addr = addr + colStep;\n      kw = kw + 1u;\n      if (kw == CONV_KERNEL_W) {\n        kw = 0u;\n        addr = addr - kwWrap;\n        kh = kh + 1u;\n        if (kh == CONV_KERNEL_H) {\n          kh = 0u;\n          addr = addr - khWrap;\n\n        }\n      }\n    }\n    return;\n  }\n  for (var i = 0u; i < 8u; i = i + 1u) {\n    var value = f32(0.0);\n    // The K and N tails read as exact zeros, exactly as the materialized padded\n    // cols buffer does, so they contribute nothing to the dot product.\n    if (in_column && k < K && ih >= 0 && ih < CONV_IN_H && iw >= 0 && iw < CONV_IN_W) {\n\n      value = f32(xm[b_base + (ic * u32(CONV_IN_H) + u32(ih)) * u32(CONV_IN_W) + u32(iw)]);\n\n    }\n    tile_B[row * TILE_K + col + i] = value;\n    k = k + 1u;\n    kw = kw + 1u;\n    iw = iw + i32(CONV_DILATION_W);\n    if (kw == CONV_KERNEL_W) {\n      kw = 0u;\n      iw = iw0;\n      kh = kh + 1u;\n      ih = ih + i32(CONV_DILATION_H);\n      if (kh == CONV_KERNEL_H) {\n        kh = 0u;\n        ih = ih0;\n\n        ic = ic + 1u;\n\n      }\n    }\n  }\n\n}\n\n\n\n\n\n\nfn storeOutput(offset: u32, row_base: u32, row: u32, col: u32, src_slot: u32, row_limit: i32, col_anchor: u32) {\n  if (row_limit > 0 && row < u32(row_limit)) {\n    let col2 = col + 1u;\n\n    var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }\n\n\n    // Padded GEMM: the last column tile runs past the logical N; only write\n    // columns inside the real output. Each subgroup-matrix column maps to a\n    // distinct y column (anchor + local), so the guards are independent.\n    if (col_anchor + col +  0u < N) { y[offset + row * N + col]        = \n\nf32(scratch[src_slot][0][row * 8u + col] + bv); }\n    if (col_anchor + col +  8u < N) { y[offset + row * N + col +  8u]  = \n\nf32(scratch[src_slot][1][row * 8u + col] + bv); }\n    if (col_anchor + col + 16u < N) { y[offset + row * N + col + 16u]  = \n\nf32(scratch[src_slot][2][row * 8u + col] + bv); }\n    if (col_anchor + col + 24u < N) { y[offset + row * N + col + 24u]  = \n\nf32(scratch[src_slot][3][row * 8u + col] + bv); }\n    if (col_anchor + col2 +  0u < N) { y[offset + row * N + col2]       = \n\nf32(scratch[src_slot][0][row * 8u + col2] + bv); }\n    if (col_anchor + col2 +  8u < N) { y[offset + row * N + col2 +  8u] = \n\nf32(scratch[src_slot][1][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 16u < N) { y[offset + row * N + col2 + 16u] = \n\nf32(scratch[src_slot][2][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 24u < N) { y[offset + row * N + col2 + 24u] = \n\nf32(scratch[src_slot][3][row * 8u + col2] + bv); }\n\n  }\n}\n\n\n@compute @workgroup_size(256, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_invocation_id) sg_id: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 4u;\n  let subtile_idy = subtile_id % 4u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K_LOOP; kidx = kidx + TILE_K) {\n\n\n    loadSHMA(a_global_base, kidx, local_idx / 4u, local_idx % 4u);\n    loadSHMB(b_base, b_global_base, kidx, local_idx / 4u, local_idx % 4u);\n    workgroupBarrier();\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = subtile_idy * SUB_ROWS * TILE_K + step;\n\n      var matA0: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&tile_A, matrix_a_offset, TILE_K);\n\n      var matA1: subgroup_matrix_left<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f32, 8, 8>, row_major>(&tile_A, matrix_a_offset + 8u * TILE_K, TILE_K);\n\n\n      let matrix_b_offset = subtile_idx * SUB_COLS * TILE_K + step;\n\n      var matB0: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset, TILE_K);\n\n      var matB1: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 8u * TILE_K, TILE_K);\n\n      var matB2: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 16u * TILE_K, TILE_K);\n\n      var matB3: subgroup_matrix_right<f32, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f32, 8, 8>, col_major>(&tile_B, matrix_b_offset + 24u * TILE_K, TILE_K);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n    workgroupBarrier();\n\n  }\n\n\n\n  // Padded N only needs guarded publication for the final partial-width tile.\n  // Full tiles can use the same direct collective stores as the aligned path;\n  // the branch is uniform because b_global_base depends only on workgroup_id.x.\n  if (b_global_base + TILE_COLS <= N) {\n\n  // Full f32 output tiles can be published by the subgroup-matrix collectives\n  // directly. With no epilogue this removes scratch traffic and three barriers.\n  // When an epilogue is present, publish the raw accumulators first, then apply\n  // bias, residual Z, and activation cooperatively after one storage barrier.\n  let matrix_c_offset = c_base + (a_global_base + base_A) * N + b_global_base + base_B;\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N +  0u, matC00, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N +  8u, matC01, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N + 16u, matC02, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 0u * N + 24u, matC03, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N +  0u, matC10, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N +  8u, matC11, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N + 16u, matC12, N);\n  subgroupMatrixStore<row_major>(&y, matrix_c_offset + 8u * N + 24u, matC13, N);\n\n  storageBarrier();\n  for (var tile_idx = local_idx; tile_idx < TILE_ROWS * TILE_COLS; tile_idx += 256u) {\n    let local_row = tile_idx / TILE_COLS;\n    let local_col = tile_idx % TILE_COLS;\n    let global_row = a_global_base + local_row;\n    let global_col = b_global_base + local_col;\n    let y_index = c_base + global_row * N + global_col;\n    var raw = f32(y[y_index]);\n\n    if (params.has_bias != 0u) { raw += f32(bias[global_row]); }\n\n    y[y_index] = f32(raw);\n  }\n\n\n    return;\n  }\n\n\n\n  // The four scratch banks are reused across the two row-groups, and each is written\n  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers\n  // give the reads visibility of the store AND stop the second row-group's store from\n  // clobbering the first's still-in-flight readback when a partial final M-tile\n  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);\n  workgroupBarrier();\n  let row = sg_id / 4u;\n  let col = (sg_id % 4u) * 2u;\n  let row_base = a_global_base + base_A;\n  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;\n  var row_limit = i32(M) - i32(row_base);\n  storeOutput(matrix_c_offset, row_base, row, col, subtile_id, row_limit, b_global_base + base_B);\n  workgroupBarrier();\n\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);\n  workgroupBarrier();\n  matrix_c_offset = matrix_c_offset + 8u * N;\n  row_limit = i32(M) - i32(row_base + 8u);\n  storeOutput(matrix_c_offset, row_base + 8u, row, col, subtile_id, row_limit, b_global_base + base_B);\n\n}",
+    "1x1-f16-shared": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\nenable f16;\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f16>;\n    @group(0) @binding(1) var<storage, read> xm: array<f16>;\n    @group(0) @binding(2) var<storage, read> w: array<f16>;\n    @group(0) @binding(3) var<storage, read> bias: array<f16>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\n\n\noverride B_BATCH_STRIDE: u32 = K * N;\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 32u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\nvar<workgroup> tile_A: array<f16, 32 * 32>;\nvar<workgroup> tile_B: array<f16, 64 * 32>;\n\n\nvar<workgroup> scratch: array<array<array<f32, 64>, 4>, 4>;\n\n\n\nfn loadSHMA(tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let a_global = tile_base + row;\n  let col = c_idx * 8u;\n  for (var col_offset = 0u; col_offset < 8u; col_offset = col_offset + 1u) {\n    let k = k_idx + col + col_offset;\n    if (a_global < M) {\n\n\n      tile_A[row * TILE_K + col + col_offset] = f16(w[a_global * K + k]);\n\n    } else {\n\n      tile_A[row * TILE_K + col + col_offset] = 0.0h;\n\n    }\n  }\n}\n\nfn loadSHMB(b_base: u32, tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let b_col = tile_base + row;\n  let col = c_idx * 16u;\n\n  for (var i = 0u; i < 16u; i = i + 1u) {\n    let k = k_idx + col + i;\n\n    tile_B[row * TILE_K + col + i] = f16(xm[b_base + k * N + b_col]);\n\n  }\n\n}\n\n\n\n\n\n\nfn storeOutput(offset: u32, row_base: u32, row: u32, col: u32, src_slot: u32, row_limit: i32) {\n  if (row_limit > 0 && row < u32(row_limit)) {\n    let col2 = col + 1u;\n\n    var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }\n\n\n    y[offset + row * N + col]       = \n\nf16(scratch[src_slot][0][row * 8u + col] + bv);\n    y[offset + row * N + col + 8u]  = \n\nf16(scratch[src_slot][1][row * 8u + col] + bv);\n    y[offset + row * N + col + 16u] = \n\nf16(scratch[src_slot][2][row * 8u + col] + bv);\n    y[offset + row * N + col + 24u] = \n\nf16(scratch[src_slot][3][row * 8u + col] + bv);\n\n    y[offset + row * N + col2]       = \n\nf16(scratch[src_slot][0][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 8u]  = \n\nf16(scratch[src_slot][1][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 16u] = \n\nf16(scratch[src_slot][2][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 24u] = \n\nf16(scratch[src_slot][3][row * 8u + col2] + bv);\n\n  }\n}\n\n\n@compute @workgroup_size(128, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_invocation_id) sg_id: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 2u;\n  let subtile_idy = subtile_id % 2u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K; kidx = kidx + TILE_K) {\n\n\n    loadSHMA(a_global_base, kidx, local_idx / 4u, local_idx % 4u);\n    loadSHMB(b_base, b_global_base, kidx, local_idx / 2u, local_idx % 2u);\n    workgroupBarrier();\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = subtile_idy * SUB_ROWS * TILE_K + step;\n\n      var matA0: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&tile_A, matrix_a_offset, TILE_K);\n\n      var matA1: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&tile_A, matrix_a_offset + 8u * TILE_K, TILE_K);\n\n\n      let matrix_b_offset = subtile_idx * SUB_COLS * TILE_K + step;\n\n      var matB0: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset, TILE_K);\n\n      var matB1: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 8u * TILE_K, TILE_K);\n\n      var matB2: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 16u * TILE_K, TILE_K);\n\n      var matB3: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 24u * TILE_K, TILE_K);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n    workgroupBarrier();\n\n  }\n\n\n\n  // The four scratch banks are reused across the two row-groups, and each is written\n  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers\n  // give the reads visibility of the store AND stop the second row-group's store from\n  // clobbering the first's still-in-flight readback when a partial final M-tile\n  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);\n  workgroupBarrier();\n  let row = sg_id / 4u;\n  let col = (sg_id % 4u) * 2u;\n  let row_base = a_global_base + base_A;\n  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;\n  var row_limit = i32(M) - i32(row_base);\n  storeOutput(matrix_c_offset, row_base, row, col, subtile_id, row_limit);\n  workgroupBarrier();\n\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);\n  workgroupBarrier();\n  matrix_c_offset = matrix_c_offset + 8u * N;\n  row_limit = i32(M) - i32(row_base + 8u);\n  storeOutput(matrix_c_offset, row_base + 8u, row, col, subtile_id, row_limit);\n\n}",
+    "1x1-f16-direct": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\nenable f16;\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f16>;\n    @group(0) @binding(1) var<storage, read> xm: array<f16>;\n    @group(0) @binding(2) var<storage, read> w: array<f16>;\n    @group(0) @binding(3) var<storage, read> bias: array<f16>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\n\n\noverride B_BATCH_STRIDE: u32 = K * N;\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 32u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\n\nvar<workgroup> scratch: array<array<array<f32, 64>, 4>, 4>;\n\n\n\n\n\n\n\n\nfn storeOutput(offset: u32, row_base: u32, row: u32, col: u32, src_slot: u32, row_limit: i32) {\n  if (row_limit > 0 && row < u32(row_limit)) {\n    let col2 = col + 1u;\n\n    var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }\n\n\n    y[offset + row * N + col]       = \n\nf16(scratch[src_slot][0][row * 8u + col] + bv);\n    y[offset + row * N + col + 8u]  = \n\nf16(scratch[src_slot][1][row * 8u + col] + bv);\n    y[offset + row * N + col + 16u] = \n\nf16(scratch[src_slot][2][row * 8u + col] + bv);\n    y[offset + row * N + col + 24u] = \n\nf16(scratch[src_slot][3][row * 8u + col] + bv);\n\n    y[offset + row * N + col2]       = \n\nf16(scratch[src_slot][0][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 8u]  = \n\nf16(scratch[src_slot][1][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 16u] = \n\nf16(scratch[src_slot][2][row * 8u + col2] + bv);\n    y[offset + row * N + col2 + 24u] = \n\nf16(scratch[src_slot][3][row * 8u + col2] + bv);\n\n  }\n}\n\n\n@compute @workgroup_size(128, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_invocation_id) sg_id: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 2u;\n  let subtile_idy = subtile_id % 2u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K; kidx = kidx + TILE_K) {\n\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = (a_global_base + subtile_idy * SUB_ROWS) * K + kidx + step;\n\n      var matA0: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&w, matrix_a_offset, K);\n\n      var matA1: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&w, matrix_a_offset + 8u * K, K);\n\n\n      let matrix_b_offset = b_base + (kidx + step) * N + b_global_base + subtile_idx * SUB_COLS;\n\n      var matB0: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, row_major>(&xm, matrix_b_offset, N);\n\n      var matB1: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, row_major>(&xm, matrix_b_offset + 8u, N);\n\n      var matB2: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, row_major>(&xm, matrix_b_offset + 16u, N);\n\n      var matB3: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, row_major>(&xm, matrix_b_offset + 24u, N);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n  }\n\n\n\n  // The four scratch banks are reused across the two row-groups, and each is written\n  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers\n  // give the reads visibility of the store AND stop the second row-group's store from\n  // clobbering the first's still-in-flight readback when a partial final M-tile\n  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);\n  workgroupBarrier();\n  let row = sg_id / 4u;\n  let col = (sg_id % 4u) * 2u;\n  let row_base = a_global_base + base_A;\n  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;\n  var row_limit = i32(M) - i32(row_base);\n  storeOutput(matrix_c_offset, row_base, row, col, subtile_id, row_limit);\n  workgroupBarrier();\n\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);\n  workgroupBarrier();\n  matrix_c_offset = matrix_c_offset + 8u * N;\n  row_limit = i32(M) - i32(row_base + 8u);\n  storeOutput(matrix_c_offset, row_base + 8u, row, col, subtile_id, row_limit);\n\n}",
+    "3x3-f16-shared": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\nenable f16;\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f16>;\n    @group(0) @binding(1) var<storage, read> xm: array<f16>;\n    @group(0) @binding(2) var<storage, read> w: array<f16>;\n    @group(0) @binding(3) var<storage, read> bias: array<f16>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride CONV_IN_CHANNELS: u32 = 1u;\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\noverride K_LOOP: u32 = 32u;\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\n\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\n\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: i32 = 1;\noverride CONV_IN_W: i32 = 1;\noverride CONV_OUT_W: u32 = 1u;\n\n// X is [batch, inChannels, inH, inW]; the tile gather indexes it directly.\noverride B_BATCH_STRIDE: u32 = CONV_IN_CHANNELS * u32(CONV_IN_H) * u32(CONV_IN_W);\n\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 32u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\nvar<workgroup> tile_A: array<f16, 32 * 32>;\nvar<workgroup> tile_B: array<f16, 64 * 32>;\n\n\nvar<workgroup> scratch: array<array<array<f32, 64>, 4>, 4>;\n\n\n\nfn loadSHMA(tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let a_global = tile_base + row;\n  let col = c_idx * 8u;\n  for (var col_offset = 0u; col_offset < 8u; col_offset = col_offset + 1u) {\n    let k = k_idx + col + col_offset;\n    if (a_global < M && k < K) {\n\n\n      tile_A[row * TILE_K + col + col_offset] = f16(w[a_global * K + k]);\n\n    } else {\n\n      tile_A[row * TILE_K + col + col_offset] = 0.0h;\n\n    }\n  }\n}\n\nfn loadSHMB(b_base: u32, tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let b_col = tile_base + row;\n  let col = c_idx * 16u;\n\n  // One output position per tile column, so its window origin is loop-invariant.\n\n  let ih0 = i32((b_col / CONV_OUT_W) * CONV_STRIDE_H) - CONV_PAD_TOP;\n\n  let iw0 = i32((b_col % CONV_OUT_W) * CONV_STRIDE_W) - CONV_PAD_LEFT;\n  let in_column = b_col < N;\n  // k advances by exactly one per element, so the (in-channel, tap-row, tap-col)\n  // decomposition is CARRIED across the loop instead of recomputed: two divisions\n  // and two moduli per loaded element become one increment and one compare, with\n  // the source coordinates advanced by the dilation in step. Only the entry values\n  // divide, and their divisors are compile-time literals.\n  var k = k_idx + col;\n  var ic = k / CONV_KSIZE;\n  var kq = k % CONV_KSIZE;\n\n  var kh = kq / CONV_KERNEL_W;\n  var kw = kq % CONV_KERNEL_W;\n\n  var ih = ih0 + i32(kh * CONV_DILATION_H);\n  var iw = iw0 + i32(kw * CONV_DILATION_W);\n  // A tile column whose whole kernel window and K span are in bounds cannot\n  // take any of the element guards below. Hoist them into one uniform test so\n  // the interior loop carries a plain address instead of recomputing coordinates.\n  let interior = in_column\n    && k_idx + col + 16u <= K\n\n    && ih0 >= 0 && ih0 + i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H) < CONV_IN_H\n    && iw0 >= 0 && iw0 + i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W) < CONV_IN_W;\n  if (interior) {\n    let colStep = i32(CONV_DILATION_W);\n    let rowStep = i32(CONV_DILATION_H) * CONV_IN_W;\n\n    let planeStep = CONV_IN_H * CONV_IN_W;\n\n    // Advancing k already added one colStep, so each wrap rewinds that plus the taps it walked.\n    let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n\n    let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n    var addr = i32(b_base) + i32(ic) * planeStep + ih * CONV_IN_W + iw;\n\n    for (var i = 0u; i < 16u; i = i + 1u) {\n      tile_B[row * TILE_K + col + i] = f16(xm[u32(addr)]);\n      addr = addr + colStep;\n      kw = kw + 1u;\n      if (kw == CONV_KERNEL_W) {\n        kw = 0u;\n        addr = addr - kwWrap;\n        kh = kh + 1u;\n        if (kh == CONV_KERNEL_H) {\n          kh = 0u;\n          addr = addr - khWrap;\n\n        }\n      }\n    }\n    return;\n  }\n  for (var i = 0u; i < 16u; i = i + 1u) {\n    var value = f16(0.0);\n    // The K and N tails read as exact zeros, exactly as the materialized padded\n    // cols buffer does, so they contribute nothing to the dot product.\n    if (in_column && k < K && ih >= 0 && ih < CONV_IN_H && iw >= 0 && iw < CONV_IN_W) {\n\n      value = f16(xm[b_base + (ic * u32(CONV_IN_H) + u32(ih)) * u32(CONV_IN_W) + u32(iw)]);\n\n    }\n    tile_B[row * TILE_K + col + i] = value;\n    k = k + 1u;\n    kw = kw + 1u;\n    iw = iw + i32(CONV_DILATION_W);\n    if (kw == CONV_KERNEL_W) {\n      kw = 0u;\n      iw = iw0;\n      kh = kh + 1u;\n      ih = ih + i32(CONV_DILATION_H);\n      if (kh == CONV_KERNEL_H) {\n        kh = 0u;\n        ih = ih0;\n\n        ic = ic + 1u;\n\n      }\n    }\n  }\n\n}\n\n\n\n\n\n\nfn storeOutput(offset: u32, row_base: u32, row: u32, col: u32, src_slot: u32, row_limit: i32, col_anchor: u32) {\n  if (row_limit > 0 && row < u32(row_limit)) {\n    let col2 = col + 1u;\n\n    var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }\n\n\n    // Padded GEMM: the last column tile runs past the logical N; only write\n    // columns inside the real output. Each subgroup-matrix column maps to a\n    // distinct y column (anchor + local), so the guards are independent.\n    if (col_anchor + col +  0u < N) { y[offset + row * N + col]        = \n\nf16(scratch[src_slot][0][row * 8u + col] + bv); }\n    if (col_anchor + col +  8u < N) { y[offset + row * N + col +  8u]  = \n\nf16(scratch[src_slot][1][row * 8u + col] + bv); }\n    if (col_anchor + col + 16u < N) { y[offset + row * N + col + 16u]  = \n\nf16(scratch[src_slot][2][row * 8u + col] + bv); }\n    if (col_anchor + col + 24u < N) { y[offset + row * N + col + 24u]  = \n\nf16(scratch[src_slot][3][row * 8u + col] + bv); }\n    if (col_anchor + col2 +  0u < N) { y[offset + row * N + col2]       = \n\nf16(scratch[src_slot][0][row * 8u + col2] + bv); }\n    if (col_anchor + col2 +  8u < N) { y[offset + row * N + col2 +  8u] = \n\nf16(scratch[src_slot][1][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 16u < N) { y[offset + row * N + col2 + 16u] = \n\nf16(scratch[src_slot][2][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 24u < N) { y[offset + row * N + col2 + 24u] = \n\nf16(scratch[src_slot][3][row * 8u + col2] + bv); }\n\n  }\n}\n\n\n@compute @workgroup_size(128, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_invocation_id) sg_id: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 2u;\n  let subtile_idy = subtile_id % 2u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K_LOOP; kidx = kidx + TILE_K) {\n\n\n    loadSHMA(a_global_base, kidx, local_idx / 4u, local_idx % 4u);\n    loadSHMB(b_base, b_global_base, kidx, local_idx / 2u, local_idx % 2u);\n    workgroupBarrier();\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = subtile_idy * SUB_ROWS * TILE_K + step;\n\n      var matA0: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&tile_A, matrix_a_offset, TILE_K);\n\n      var matA1: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&tile_A, matrix_a_offset + 8u * TILE_K, TILE_K);\n\n\n      let matrix_b_offset = subtile_idx * SUB_COLS * TILE_K + step;\n\n      var matB0: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset, TILE_K);\n\n      var matB1: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 8u * TILE_K, TILE_K);\n\n      var matB2: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 16u * TILE_K, TILE_K);\n\n      var matB3: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 24u * TILE_K, TILE_K);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n    workgroupBarrier();\n\n  }\n\n\n\n  // The four scratch banks are reused across the two row-groups, and each is written\n  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers\n  // give the reads visibility of the store AND stop the second row-group's store from\n  // clobbering the first's still-in-flight readback when a partial final M-tile\n  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);\n  workgroupBarrier();\n  let row = sg_id / 4u;\n  let col = (sg_id % 4u) * 2u;\n  let row_base = a_global_base + base_A;\n  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;\n  var row_limit = i32(M) - i32(row_base);\n  storeOutput(matrix_c_offset, row_base, row, col, subtile_id, row_limit, b_global_base + base_B);\n  workgroupBarrier();\n\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);\n  workgroupBarrier();\n  matrix_c_offset = matrix_c_offset + 8u * N;\n  row_limit = i32(M) - i32(row_base + 8u);\n  storeOutput(matrix_c_offset, row_base + 8u, row, col, subtile_id, row_limit, b_global_base + base_B);\n\n}",
+    "3x3-f16-direct": "// Adapted from https://huggingface.co/kernels/webgpu-kernels/ai.onnx.Conv/resolve/7b19a1ea4fd2abef3203991ca933405f12cfcc62/build/webgpu/conv-1x1-subgroup-matrix.wgsl.jinja\n// Apache-2.0; see LICENSE. Integration MIT, https://github.com/barhanc/wgpu-executorch\n// Batched subgroup-matrix product C[b] (M x N) = A (M x K) * B[b] (K x N).\n// A is row-major; B may be a direct matrix view, a materialized column matrix,\n// or an on-demand gather. Accumulation is f32. A configured epilogue may apply\n// bias or other output transforms after the full K reduction.\n//\n// Full 8x8 matrix loads require complete K/N tiles. The aligned path enforces\n// that geometry; `padded` zero-fills tails, and `implicitIm2col` gathers and\n// zero-fills directly from NCHW without materializing the column matrix.\n//\n// `splitK` assigns disjoint K ranges to workgroup_id.z. Each slice writes raw\n// sums to tile-padded [splitK,batch,M_PAD,N_PAD] scratch; a later pass combines\n// the slices and applies bias or an epilogue. Padded tail cells remain zero and\n// are never copied to the logical output.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nenable subgroups;\n\nenable subgroup_size_control;\n\nenable chromium_experimental_subgroup_matrix;\ndiagnostic(off, chromium.subgroup_matrix_uniformity);\n\nenable f16;\n\n    @group(0) @binding(0) var<storage, read_write> y: array<f16>;\n    @group(0) @binding(1) var<storage, read> xm: array<f16>;\n    @group(0) @binding(2) var<storage, read> w: array<f16>;\n    @group(0) @binding(3) var<storage, read> bias: array<f16>;\n    struct Params { has_bias: u32 }\n    @group(0) @binding(4) var<uniform> params: Params;\n    \n\n\n\n\n\n\n\n\n\n\n\n\noverride CONV_IN_CHANNELS: u32 = 1u;\noverride M: u32 = 1u;\noverride K: u32 = 32u;\n\noverride N: u32 = 64u;\n\n\noverride K_LOOP: u32 = 32u;\n\n\nconst CONV_KERNEL_H: u32 = 3u;\nconst CONV_KERNEL_W: u32 = 3u;\n\nconst CONV_KSIZE: u32 = CONV_KERNEL_H * CONV_KERNEL_W;\n\noverride CONV_STRIDE_H: u32 = 1u;\noverride CONV_STRIDE_W: u32 = 1u;\noverride CONV_DILATION_H: u32 = 1u;\noverride CONV_DILATION_W: u32 = 1u;\noverride CONV_PAD_TOP: i32 = 1;\noverride CONV_PAD_LEFT: i32 = 1;\noverride CONV_IN_H: i32 = 1;\noverride CONV_IN_W: i32 = 1;\noverride CONV_OUT_W: u32 = 1u;\n\n// X is [batch, inChannels, inH, inW]; the tile gather indexes it directly.\noverride B_BATCH_STRIDE: u32 = CONV_IN_CHANNELS * u32(CONV_IN_H) * u32(CONV_IN_W);\n\n\n\noverride C_BATCH_STRIDE: u32 = M * N;\n\n\nconst TILE_COLS: u32 = 64u;\nconst TILE_ROWS: u32 = 32u;\nconst TILE_K: u32 = 32u;\nconst SUB_COLS: u32 = 32u;\nconst SUB_ROWS: u32 = 16u;\n\n\nvar<workgroup> tile_A: array<f16, 32 * 32>;\nvar<workgroup> tile_B: array<f16, 64 * 32>;\n\n\nvar<workgroup> scratch: array<array<array<f32, 64>, 4>, 4>;\n\n\n\nfn loadSHMA(tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let a_global = tile_base + row;\n  let col = c_idx * 8u;\n  for (var col_offset = 0u; col_offset < 8u; col_offset = col_offset + 1u) {\n    let k = k_idx + col + col_offset;\n    if (a_global < M && k < K) {\n\n\n      tile_A[row * TILE_K + col + col_offset] = f16(w[a_global * K + k]);\n\n    } else {\n\n      tile_A[row * TILE_K + col + col_offset] = 0.0h;\n\n    }\n  }\n}\n\nfn loadSHMB(b_base: u32, tile_base: u32, k_idx: u32, row: u32, c_idx: u32) {\n  let b_col = tile_base + row;\n  let col = c_idx * 16u;\n\n  // One output position per tile column, so its window origin is loop-invariant.\n\n  let ih0 = i32((b_col / CONV_OUT_W) * CONV_STRIDE_H) - CONV_PAD_TOP;\n\n  let iw0 = i32((b_col % CONV_OUT_W) * CONV_STRIDE_W) - CONV_PAD_LEFT;\n  let in_column = b_col < N;\n  // k advances by exactly one per element, so the (in-channel, tap-row, tap-col)\n  // decomposition is CARRIED across the loop instead of recomputed: two divisions\n  // and two moduli per loaded element become one increment and one compare, with\n  // the source coordinates advanced by the dilation in step. Only the entry values\n  // divide, and their divisors are compile-time literals.\n  var k = k_idx + col;\n  var ic = k / CONV_KSIZE;\n  var kq = k % CONV_KSIZE;\n\n  var kh = kq / CONV_KERNEL_W;\n  var kw = kq % CONV_KERNEL_W;\n\n  var ih = ih0 + i32(kh * CONV_DILATION_H);\n  var iw = iw0 + i32(kw * CONV_DILATION_W);\n  // A tile column whose whole kernel window and K span are in bounds cannot\n  // take any of the element guards below. Hoist them into one uniform test so\n  // the interior loop carries a plain address instead of recomputing coordinates.\n  let interior = in_column\n    && k_idx + col + 16u <= K\n\n    && ih0 >= 0 && ih0 + i32((CONV_KERNEL_H - 1u) * CONV_DILATION_H) < CONV_IN_H\n    && iw0 >= 0 && iw0 + i32((CONV_KERNEL_W - 1u) * CONV_DILATION_W) < CONV_IN_W;\n  if (interior) {\n    let colStep = i32(CONV_DILATION_W);\n    let rowStep = i32(CONV_DILATION_H) * CONV_IN_W;\n\n    let planeStep = CONV_IN_H * CONV_IN_W;\n\n    // Advancing k already added one colStep, so each wrap rewinds that plus the taps it walked.\n    let kwWrap = colStep * i32(CONV_KERNEL_W) - rowStep;\n\n    let khWrap = rowStep * i32(CONV_KERNEL_H) - planeStep;\n    var addr = i32(b_base) + i32(ic) * planeStep + ih * CONV_IN_W + iw;\n\n    for (var i = 0u; i < 16u; i = i + 1u) {\n      tile_B[row * TILE_K + col + i] = f16(xm[u32(addr)]);\n      addr = addr + colStep;\n      kw = kw + 1u;\n      if (kw == CONV_KERNEL_W) {\n        kw = 0u;\n        addr = addr - kwWrap;\n        kh = kh + 1u;\n        if (kh == CONV_KERNEL_H) {\n          kh = 0u;\n          addr = addr - khWrap;\n\n        }\n      }\n    }\n    return;\n  }\n  for (var i = 0u; i < 16u; i = i + 1u) {\n    var value = f16(0.0);\n    // The K and N tails read as exact zeros, exactly as the materialized padded\n    // cols buffer does, so they contribute nothing to the dot product.\n    if (in_column && k < K && ih >= 0 && ih < CONV_IN_H && iw >= 0 && iw < CONV_IN_W) {\n\n      value = f16(xm[b_base + (ic * u32(CONV_IN_H) + u32(ih)) * u32(CONV_IN_W) + u32(iw)]);\n\n    }\n    tile_B[row * TILE_K + col + i] = value;\n    k = k + 1u;\n    kw = kw + 1u;\n    iw = iw + i32(CONV_DILATION_W);\n    if (kw == CONV_KERNEL_W) {\n      kw = 0u;\n      iw = iw0;\n      kh = kh + 1u;\n      ih = ih + i32(CONV_DILATION_H);\n      if (kh == CONV_KERNEL_H) {\n        kh = 0u;\n        ih = ih0;\n\n        ic = ic + 1u;\n\n      }\n    }\n  }\n\n}\n\n\n\n\n\n\nfn storeOutput(offset: u32, row_base: u32, row: u32, col: u32, src_slot: u32, row_limit: i32, col_anchor: u32) {\n  if (row_limit > 0 && row < u32(row_limit)) {\n    let col2 = col + 1u;\n\n    var bv = 0.0; if (params.has_bias != 0u) { bv = f32(bias[row_base + row]); }\n\n\n    // Padded GEMM: the last column tile runs past the logical N; only write\n    // columns inside the real output. Each subgroup-matrix column maps to a\n    // distinct y column (anchor + local), so the guards are independent.\n    if (col_anchor + col +  0u < N) { y[offset + row * N + col]        = \n\nf16(scratch[src_slot][0][row * 8u + col] + bv); }\n    if (col_anchor + col +  8u < N) { y[offset + row * N + col +  8u]  = \n\nf16(scratch[src_slot][1][row * 8u + col] + bv); }\n    if (col_anchor + col + 16u < N) { y[offset + row * N + col + 16u]  = \n\nf16(scratch[src_slot][2][row * 8u + col] + bv); }\n    if (col_anchor + col + 24u < N) { y[offset + row * N + col + 24u]  = \n\nf16(scratch[src_slot][3][row * 8u + col] + bv); }\n    if (col_anchor + col2 +  0u < N) { y[offset + row * N + col2]       = \n\nf16(scratch[src_slot][0][row * 8u + col2] + bv); }\n    if (col_anchor + col2 +  8u < N) { y[offset + row * N + col2 +  8u] = \n\nf16(scratch[src_slot][1][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 16u < N) { y[offset + row * N + col2 + 16u] = \n\nf16(scratch[src_slot][2][row * 8u + col2] + bv); }\n    if (col_anchor + col2 + 24u < N) { y[offset + row * N + col2 + 24u] = \n\nf16(scratch[src_slot][3][row * 8u + col2] + bv); }\n\n  }\n}\n\n\n@compute @workgroup_size(128, 1, 1) @subgroup_size(32)\nfn main(\n  @builtin(workgroup_id) workgroup_id: vec3<u32>,\n  @builtin(local_invocation_index) local_idx: u32,\n\n  @builtin(subgroup_invocation_id) sg_id: u32,\n\n  @builtin(subgroup_size) sg_size: u32\n) {\n\n  let batch = workgroup_id.z;\n  let b_base = batch * B_BATCH_STRIDE;\n  let c_base = batch * C_BATCH_STRIDE;\n\n  let a_global_base = workgroup_id.y * TILE_ROWS;\n  let b_global_base = workgroup_id.x * TILE_COLS;\n  let subtile_id = local_idx / sg_size;\n  let subtile_idx = subtile_id / 2u;\n  let subtile_idy = subtile_id % 2u;\n  let base_A = subtile_idy * SUB_ROWS;\n  let base_B = subtile_idx * SUB_COLS;\n\n  var matC00: subgroup_matrix_result<f32, 8, 8>;\n  var matC01: subgroup_matrix_result<f32, 8, 8>;\n  var matC02: subgroup_matrix_result<f32, 8, 8>;\n  var matC03: subgroup_matrix_result<f32, 8, 8>;\n  var matC10: subgroup_matrix_result<f32, 8, 8>;\n  var matC11: subgroup_matrix_result<f32, 8, 8>;\n  var matC12: subgroup_matrix_result<f32, 8, 8>;\n  var matC13: subgroup_matrix_result<f32, 8, 8>;\n\n\n  for (var kidx = 0u; kidx < K_LOOP; kidx = kidx + TILE_K) {\n\n\n    loadSHMA(a_global_base, kidx, local_idx / 4u, local_idx % 4u);\n    loadSHMB(b_base, b_global_base, kidx, local_idx / 2u, local_idx % 2u);\n    workgroupBarrier();\n\n\n    for (var step = 0u; step < TILE_K; step = step + 8u) {\n\n      let matrix_a_offset = subtile_idy * SUB_ROWS * TILE_K + step;\n\n      var matA0: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&tile_A, matrix_a_offset, TILE_K);\n\n      var matA1: subgroup_matrix_left<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_left<f16, 8, 8>, row_major>(&tile_A, matrix_a_offset + 8u * TILE_K, TILE_K);\n\n\n      let matrix_b_offset = subtile_idx * SUB_COLS * TILE_K + step;\n\n      var matB0: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset, TILE_K);\n\n      var matB1: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 8u * TILE_K, TILE_K);\n\n      var matB2: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 16u * TILE_K, TILE_K);\n\n      var matB3: subgroup_matrix_right<f16, 8, 8> = subgroupMatrixLoad<subgroup_matrix_right<f16, 8, 8>, col_major>(&tile_B, matrix_b_offset + 24u * TILE_K, TILE_K);\n\n\n      matC00 = subgroupMatrixMultiplyAccumulate(matA0, matB0, matC00);\n      matC01 = subgroupMatrixMultiplyAccumulate(matA0, matB1, matC01);\n      matC02 = subgroupMatrixMultiplyAccumulate(matA0, matB2, matC02);\n      matC03 = subgroupMatrixMultiplyAccumulate(matA0, matB3, matC03);\n      matC10 = subgroupMatrixMultiplyAccumulate(matA1, matB0, matC10);\n      matC11 = subgroupMatrixMultiplyAccumulate(matA1, matB1, matC11);\n      matC12 = subgroupMatrixMultiplyAccumulate(matA1, matB2, matC12);\n      matC13 = subgroupMatrixMultiplyAccumulate(matA1, matB3, matC13);\n    }\n\n    workgroupBarrier();\n\n  }\n\n\n\n  // The four scratch banks are reused across the two row-groups, and each is written\n  // by a collective subgroupMatrixStore then read CROSS-LANE by storeOutput. Barriers\n  // give the reads visibility of the store AND stop the second row-group's store from\n  // clobbering the first's still-in-flight readback when a partial final M-tile\n  // diverges storeOutput's guard. Without both barriers the last valid row can be corrupted.\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC00, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC01, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC02, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC03, 8u);\n  workgroupBarrier();\n  let row = sg_id / 4u;\n  let col = (sg_id % 4u) * 2u;\n  let row_base = a_global_base + base_A;\n  var matrix_c_offset = c_base + row_base * N + b_global_base + base_B;\n  var row_limit = i32(M) - i32(row_base);\n  storeOutput(matrix_c_offset, row_base, row, col, subtile_id, row_limit, b_global_base + base_B);\n  workgroupBarrier();\n\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][0], 0u, matC10, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][1], 0u, matC11, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][2], 0u, matC12, 8u);\n  subgroupMatrixStore<row_major>(&scratch[subtile_id][3], 0u, matC13, 8u);\n  workgroupBarrier();\n  matrix_c_offset = matrix_c_offset + 8u * N;\n  row_limit = i32(M) - i32(row_base + 8u);\n  storeOutput(matrix_c_offset, row_base + 8u, row, col, subtile_id, row_limit, b_global_base + base_B);\n\n}"
+  }
+}
diff --git a/utils/benchmark/huggingface/metadata.json b/utils/benchmark/huggingface/metadata.json
new file mode 100644
index 0000000..925e656
--- /dev/null
+++ b/utils/benchmark/huggingface/metadata.json
@@ -0,0 +1,174 @@
+{
+  "name": "ai.onnx.Conv",
+  "id": "_ai_onnx_conv_webgpu_425dc7b",
+  "version": 1,
+  "license": "Apache-2.0",
+  "backend": { "type": "webgpu" },
+  "digest": {
+    "algorithm": "sha256",
+    "files": {
+      "bench.json": "qQlQzLmos636YZMqlseiLZNw3VMjVExXhvQhIkhNmso=",
+      "conv-1x1-channel-reduce.wgsl.jinja": "Ug2iTybBtLS8dnr7KOGbxUYKidE0/sb7LGLeAP3xka8=",
+      "conv-1x1-gemm-tiled-reg.wgsl.jinja": "fqy1AlbukRB6+EsP4NT8IsBbiAYWtxE7o8z87QN7nHI=",
+      "conv-1x1-gemm-tiled.wgsl.jinja": "mQWnnhk9Xlj20YcMc+6sQBuy67ZhdkgPUSdYgtauDaY=",
+      "conv-1x1-subgroup-matrix.wgsl.jinja": "/M/DUaLDk2rBCojLxieYQxQhpMei79mv4iM0shwJbl8=",
+      "conv-direct-nd.wgsl.jinja": "qooloadvj03r5vD7sSuCe1xGrWeuCxNx7B4lUjilOGQ=",
+      "conv-direct-unrolled.wgsl.jinja": "GsmGTy9UvercDDC0vNc3OOve9xcRtg2Hj9rSpx9YOSc=",
+      "conv-im2col-ncdhw.wgsl.jinja": "vQtnzeEKC2wm23+kwcaWoX3VSaJSqno18ACe3w3trhI=",
+      "conv-im2col-nchw.wgsl.jinja": "IRpmtpeVQsLE6ud+Sf1230XaZVS1dxDtTZuSDwU3P8s=",
+      "conv-splitk-reduce.wgsl.jinja": "jPCiZlPWzoQEoa9+ZwfZdSOHH+/hSYknvRFHKMvgkKM=",
+      "conv1d-tiled-reg.wgsl.jinja": "HvWuECHIzxqPrIyvfdlljhdOXpwzZo0jvAYuYDY+3kM=",
+      "conv2d-grouped-large-w4.wgsl.jinja": "mt2+nqnbFfJMac9s3sAsjTZlySD9VJFE+gHnkToVwt8=",
+      "manifest.json": "RtFRWBQdJ7bpJaP2G26O3a2GIKy1QaRpfZQqTFFmoYs=",
+      "test.json": "Y5+ejG2R11fFhIYo5ExoKSNeCtn278UgO3/JQgG1bY0="
+    }
+  },
+  "provenance": { "kernel": { "sha": "6fdf6301e2bbcc2f03bf1eaf493b7ad55ef33afc", "dirty": false } },
+  "webgpu": {
+    "manifestSpec": "2.1",
+    "variants": {
+      "ncw1d": ["conv-direct-nd.wgsl.jinja"],
+      "ncw1d_bias": ["conv-direct-nd.wgsl.jinja"],
+      "ncdhw3d": ["conv-direct-nd.wgsl.jinja"],
+      "ncdhw3d_bias": ["conv-direct-nd.wgsl.jinja"],
+      "nchw2d": ["conv-direct-nd.wgsl.jinja"],
+      "nchw2d_bias": ["conv-direct-nd.wgsl.jinja"],
+      "grouped_large_kernel_w4": ["conv2d-grouped-large-w4.wgsl.jinja"],
+      "grouped_large_kernel_w4_bias": ["conv2d-grouped-large-w4.wgsl.jinja"],
+      "grouped_large_kernel_w4_tail": ["conv2d-grouped-large-w4.wgsl.jinja"],
+      "grouped_large_kernel_w4_tail_bias": ["conv2d-grouped-large-w4.wgsl.jinja"],
+      "grouped_large_kernel_w4_dilated_lanes": ["conv2d-grouped-large-w4.wgsl.jinja"],
+      "grouped_large_kernel_w4_dilated_lanes_bias": ["conv2d-grouped-large-w4.wgsl.jinja"],
+      "pointwise_channel_reduce": ["conv-1x1-channel-reduce.wgsl.jinja"],
+      "pointwise_channel_reduce_bias": ["conv-1x1-channel-reduce.wgsl.jinja"],
+      "gemm_1x1_subgroup_matrix": ["conv-1x1-subgroup-matrix.wgsl.jinja"],
+      "gemm_1x1_subgroup_matrix_bias": ["conv-1x1-subgroup-matrix.wgsl.jinja"],
+      "im2col_gemm_subgroup_matrix": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_subgroup_matrix_bias": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_direct_f32_subgroup_matrix": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_direct_f16_subgroup_matrix": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_direct_f32_subgroup_matrix_bias": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_direct_f16_subgroup_matrix_bias": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "implicit_im2col_subgroup_matrix": ["conv-1x1-subgroup-matrix.wgsl.jinja"],
+      "implicit_im2col_subgroup_matrix_bias": ["conv-1x1-subgroup-matrix.wgsl.jinja"],
+      "implicit_im2col_subgroup_matrix_splitk": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "implicit_im2col_subgroup_matrix_bias_splitk": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "im2col3d_gemm_subgroup_matrix": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-ncdhw.wgsl.jinja"
+      ],
+      "im2col3d_gemm_subgroup_matrix_bias": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-ncdhw.wgsl.jinja"
+      ],
+      "im2col3d_gemm_tiled_reg": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-im2col-ncdhw.wgsl.jinja"
+      ],
+      "im2col3d_gemm_tiled": ["conv-1x1-gemm-tiled.wgsl.jinja", "conv-im2col-ncdhw.wgsl.jinja"],
+      "im2col3d_gemm_tiled_bias_reg": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-im2col-ncdhw.wgsl.jinja"
+      ],
+      "im2col3d_gemm_tiled_bias": [
+        "conv-1x1-gemm-tiled.wgsl.jinja",
+        "conv-im2col-ncdhw.wgsl.jinja"
+      ],
+      "im2col_gemm_subgroup_matrix_padded": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_subgroup_matrix_padded_bias": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_subgroup_matrix_padded_splitk": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "im2col_gemm_subgroup_matrix_padded_bias_splitk": [
+        "conv-1x1-subgroup-matrix.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "implicit_im2col_tiled_bias_reg_m32": ["conv-1x1-gemm-tiled-reg.wgsl.jinja"],
+      "implicit_im2col_tiled_reg": ["conv-1x1-gemm-tiled-reg.wgsl.jinja"],
+      "implicit_im2col_tiled_bias_reg": ["conv-1x1-gemm-tiled-reg.wgsl.jinja"],
+      "implicit_im2col_tiled_reg_splitk": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "implicit_im2col_tiled_bias_reg_splitk": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "im2col_gemm_tiled_reg": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_tiled": ["conv-1x1-gemm-tiled.wgsl.jinja", "conv-im2col-nchw.wgsl.jinja"],
+      "im2col_gemm_tiled_bias_reg": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_tiled_bias": ["conv-1x1-gemm-tiled.wgsl.jinja", "conv-im2col-nchw.wgsl.jinja"],
+      "im2col_gemm_tiled_reg_f16_columns": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_tiled_f16_columns": [
+        "conv-1x1-gemm-tiled.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_tiled_bias_reg_f16_columns": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "im2col_gemm_tiled_bias_f16_columns": [
+        "conv-1x1-gemm-tiled.wgsl.jinja",
+        "conv-im2col-nchw.wgsl.jinja"
+      ],
+      "gemm_1x1_tiled_reg": ["conv-1x1-gemm-tiled-reg.wgsl.jinja"],
+      "gemm_1x1_tiled_bias_reg": ["conv-1x1-gemm-tiled-reg.wgsl.jinja"],
+      "gemm_1x1_tiled": ["conv-1x1-gemm-tiled.wgsl.jinja"],
+      "gemm_1x1_tiled_bias": ["conv-1x1-gemm-tiled.wgsl.jinja"],
+      "gemm_1x1_tiled_reg_splitk": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "gemm_1x1_tiled_bias_reg_splitk": [
+        "conv-1x1-gemm-tiled-reg.wgsl.jinja",
+        "conv-splitk-reduce.wgsl.jinja"
+      ],
+      "direct_unrolled": ["conv-direct-unrolled.wgsl.jinja"],
+      "direct_unrolled_bias": ["conv-direct-unrolled.wgsl.jinja"],
+      "conv1d_tiled_reg": ["conv1d-tiled-reg.wgsl.jinja"],
+      "conv1d_tiled_bias_reg": ["conv1d-tiled-reg.wgsl.jinja"]
+    }
+  }
+}
diff --git a/utils/benchmark/interior-results.json b/utils/benchmark/interior-results.json
new file mode 100644
index 0000000..315c18a
--- /dev/null
+++ b/utils/benchmark/interior-results.json
@@ -0,0 +1,582 @@
+{
+  "baseline": "a62eb22",
+  "candidate": "Dense tiled 3x3 convolution: precompute a nine-bit validity mask per spatial column; fill interior masks with 0x1ff; retain generic bounds checks for other kernels.",
+  "scope": "Convolution shader changes only; input/output shapes, graph, weights, FP16 arithmetic and accumulation order are preserved. Four private u32 masks per invocation; no extra GPU buffer or dispatch.",
+  "method": "Unchanged model graphs, same device and inputs, recorded once outside timed loops. Each measurement calls submit then awaits sync. Times cover graph execution and input/output buffer copies, excluding camera crop/upload, depth postprocessing and canvas presentation.",
+  "browserRepeatReason": "The initial 51-sample browser run was inconclusive for DepthART FP16. Repeated with 101 samples and deterministically shuffled pair order to reduce scheduling/order effects. Both complete runs are retained.",
+  "comparisonCheck": "All recorded model outputs match the baseline exactly (maxDelta=0).",
+  "native": {
+    "baseline": "a62eb22",
+    "warmups": 10,
+    "samples": 51,
+    "results": [
+      {
+        "model": "depthart",
+        "dtype": "float32",
+        "beforeMs": 15.858041999999841,
+        "afterMs": 15.006792000000132,
+        "speedup": 1.0567243152300438,
+        "maxDelta": 0,
+        "samples": [
+          [
+            15.98762499999998, 15.875915999999961, 15.804750000000013, 15.843833000000132,
+            15.797166999999945, 15.843415999999934, 15.788000000000011, 15.858041999999841,
+            15.807416999999987, 16.03125, 15.910791000000017, 16.078917000000047, 16.16995799999995,
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+        }
+      ],
+      "errors": []
+    },
+    {
+      "baseline": "a62eb22",
+      "gpu": {
+        "vendor": "apple",
+        "architecture": "metal-3"
+      },
+      "browser": "Mozilla/5.0 (Macintosh; Intel Mac OS X 10_15_7) AppleWebKit/537.36 (KHTML, like Gecko) HeadlessChrome/155.0.0.0 Safari/537.36",
+      "warmups": 20,
+      "measuredSubmissions": 101,
+      "order": "deterministically shuffled pairs",
+      "results": [
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+              12, 12.200000047683716, 28.600000023841858, 14, 12.099999904632568,
+              12.200000047683716, 15.899999976158142, 12.800000071525574, 11.399999976158142,
+              11.399999976158142, 12.100000023841858, 18.200000047683716, 13.899999976158142,
+              13.100000023841858, 12.899999976158142, 12.799999952316284, 14.799999952316284,
+              15.200000047683716, 14.899999976158142, 15, 15.5, 14.899999976158142,
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+              15.100000023841858, 11.600000023841858, 12.600000023841858, 12.800000071525574
+            ]
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+        },
+        {
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+          "dtype": "float32",
+          "beforeMs": 15.199999928474426,
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+              14.5
+            ]
+          ]
+        },
+        {
+          "model": "yolo26n",
+          "dtype": "float16",
+          "beforeMs": 11.900000095367432,
+          "afterMs": 11.100000023841858,
+          "speedup": 1.0720720783610127,
+          "maxDelta": 0,
+          "samples": [
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+              11.600000023841858, 12, 12.100000023841858, 11.099999904632568, 12.599999904632568,
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+              11.199999928474426, 12.299999952316284
+            ],
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+              13.799999952316284, 14, 10.700000047683716, 13.5, 11.100000023841858,
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+              10.799999952316284, 10.700000047683716, 11.100000023841858, 10.799999952316284,
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+              10.800000071525574, 10.600000023841858, 10.700000047683716, 10.800000071525574,
+              11.700000047683716, 10.600000023841858, 11.600000023841858, 13.800000071525574,
+              16.299999952316284, 13.5, 13.700000047683716, 13.899999976158142, 14.100000023841858,
+              10.799999952316284, 13.800000071525574, 11.100000023841858, 13.700000047683716,
+              11.600000023841858, 12, 14.799999952316284, 10.899999976158142, 13.600000023841858,
+              10.899999976158142, 12.100000023841858, 10.899999976158142, 11.100000023841858,
+              12.299999952316284, 11, 12.100000023841858, 12.200000047683716, 11.700000047683716,
+              10.900000095367432, 11.600000023841858, 12.199999928474426, 11, 11.800000071525574,
+              12.200000047683716, 10.899999976158142
+            ]
+          ]
+        }
+      ],
+      "errors": []
+    }
+  ],
+  "reproduce": "WGPU_MODEL_BASELINE=a62eb22 WGPU_MODEL_RESULTS=/tmp/model-results.json npx vitest run tests/bench-models.test.ts --disableConsoleIntercept",
+  "rejectedCandidate": "A separate fast gather branch within each K tile showed regressions on several shapes and was discarded."
+}
diff --git a/utils/benchmark/main.ts b/utils/benchmark/main.ts
index ee74d5a..7244030 100644
--- a/utils/benchmark/main.ts
+++ b/utils/benchmark/main.ts
@@ -355,17 +355,20 @@ async function run() {
 
   // 2. Batched Matrix Multiplication (BMM)
   const bmmConfigs = [
-    [4, 64, 64, 30],
-    [8, 128, 128, 20],
+    [4, 64, 64, 64, 30],
+    [8, 128, 128, 128, 20],
+    // Attention shapes taken directly from the YOLO graph.
+    [2, 400, 32, 400, 20],
+    [2, 64, 400, 400, 20],
   ] as const;
 
-  for (const [B, M, N, iters] of bmmConfigs) {
-    statusEl.innerText = `Benchmarking BMM [${B}, ${M}, ${N}]...`;
+  for (const [B, M, K, N, iters] of bmmConfigs) {
+    statusEl.innerText = `Benchmarking BMM [${B}, ${M}, ${K}] x [${B}, ${K}, ${N}]...`;
 
     // Baseline
     const baseCtx = new BaselineContext(device);
-    const ba = baseCtx.tensor('float32', [B, M, N]).setData(makeF32(B * M * N));
-    const bb = baseCtx.tensor('float32', [B, N, N]).setData(makeF32(B * N * N));
+    const ba = baseCtx.tensor('float32', [B, M, K]).setData(makeF32(B * M * K));
+    const bb = baseCtx.tensor('float32', [B, K, N]).setData(makeF32(B * K * N));
     const bout = baseCtx.tensor('float32', [B, M, N]);
     baseCtx.recordShader(baselineShaders.bmm, [ba, bb, bout]);
     const baseStats = await measureBatchedStatsMs(baseCtx, iters);
@@ -373,8 +376,8 @@ async function run() {
 
     // Optimized FP32
     const ctx32 = new WgpuExecutionContext(device);
-    const a32 = ctx32.tensor('float32', [B, M, N]).setData(makeF32(B * M * N));
-    const b32 = ctx32.tensor('float32', [B, N, N]).setData(makeF32(B * N * N));
+    const a32 = ctx32.tensor('float32', [B, M, K]).setData(makeF32(B * M * K));
+    const b32 = ctx32.tensor('float32', [B, K, N]).setData(makeF32(B * K * N));
     const out32 = ctx32.tensor('float32', [B, M, N]);
     ctx32.recordShader(shaders.bmm, [a32, b32, out32]);
     const fp32Stats = await measureBatchedStatsMs(ctx32, iters);
@@ -384,8 +387,8 @@ async function run() {
     let fp16Stats: Stats | null = null;
     if (hasF16) {
       const ctx16 = new WgpuExecutionContext(device);
-      const a16 = ctx16.tensor('float16', [B, M, N]).setData(makeF16(B * M * N));
-      const b16 = ctx16.tensor('float16', [B, N, N]).setData(makeF16(B * N * N));
+      const a16 = ctx16.tensor('float16', [B, M, K]).setData(makeF16(B * M * K));
+      const b16 = ctx16.tensor('float16', [B, K, N]).setData(makeF16(B * K * N));
       const out16 = ctx16.tensor('float16', [B, M, N]);
       ctx16.recordShader(shaders.bmm, [a16, b16, out16]);
       fp16Stats = await measureBatchedStatsMs(ctx16, iters);
@@ -402,7 +405,7 @@ async function run() {
     addRow({
       category: 'Linear Algebra',
       name: 'Batch MatMul (BMM)',
-      shape: `[${B}, ${M}, ${N}] * [${B}, ${N}, ${N}]`,
+      shape: `[${B}, ${M}, ${K}] * [${B}, ${K}, ${N}]`,
       baselineMs,
       baselineStd: baseStats.std,
       fp32Ms,
@@ -421,6 +424,39 @@ async function run() {
 
   // 3. Convolutions (Tile64 3x3, Pointwise 1x1, Depthwise, ConvWithClamp)
   const convConfigs = [
+    {
+      shader: shaders.convolution,
+      category: 'Convolution',
+      label: 'DepthART deep 3x3 reduction',
+      inShape: [1, 960, 14, 14],
+      wShape: [48, 960, 3, 3],
+      groups: 1,
+      stride: [1, 1],
+      pad: [1, 1],
+      iters: 10,
+    },
+    {
+      shader: shaders.convolution,
+      category: 'Convolution',
+      label: 'YOLO dense 3x3 (Tile32)',
+      inShape: [1, 32, 40, 40],
+      wShape: [32, 32, 3, 3],
+      groups: 1,
+      stride: [1, 1],
+      pad: [1, 1],
+      iters: 20,
+    },
+    {
+      shader: shaders.convolution,
+      category: 'Convolution',
+      label: 'YOLO dense 3x3 stride 2',
+      inShape: [1, 64, 80, 80],
+      wShape: [64, 64, 3, 3],
+      groups: 1,
+      stride: [2, 2],
+      pad: [1, 1],
+      iters: 20,
+    },
     {
       shader: shaders.convWithClamp,
       category: 'Convolution',
@@ -494,7 +530,12 @@ async function run() {
 
     const inNumel = c.inShape.reduce((a, b) => a * b, 1);
     const wNumel = c.wShape.reduce((a, b) => a * b, 1);
-    const outShape = [c.inShape[0], c.wShape[0], c.inShape[2], c.inShape[3]];
+    const outShape = [
+      c.inShape[0],
+      c.wShape[0],
+      Math.floor((c.inShape[2] + 2 * c.pad[0] - c.wShape[2]) / c.stride[0]) + 1,
+      Math.floor((c.inShape[3] + 2 * c.pad[1] - c.wShape[3]) / c.stride[1]) + 1,
+    ];
 
     // Baseline
     const baseCtx = new BaselineContext(device);
diff --git a/utils/benchmark/narrow-results.json b/utils/benchmark/narrow-results.json
new file mode 100644
index 0000000..495b2ee
--- /dev/null
+++ b/utils/benchmark/narrow-results.json
@@ -0,0 +1,2957 @@
+{
+  "baseline": "308cc40",
+  "selection": "Dense non-transposed 3x3 convolution; groups=1; 8<=OC<=16; IC divisible by 4; B*OH*OW>=4096. Shape-based selection, no vendor checks.",
+  "notes": [
+    "Only nine YOLO convolutions select this kernel. DepthART selects none.",
+    "Smaller grids regressed in raw comparisons and retain the existing path.",
+    "Model timings measure the recorded graph, excluding camera, preprocessing and presentation."
+  ],
+  "runs": [
+    {
+      "environment": "Node WebGPU / Metal",
+      "kernels": {
+        "baseline": "308cc40",
+        "gpu": {
+          "vendor": "apple",
+          "architecture": "metal-3"
+        },
+        "method": "8\u2013512 recorded dispatches per submit, scaled by operation count; submit + await sync; 3 warmups, 11 alternating samples per version; median milliseconds per dispatch; GPU timestamps",
+        "results": [
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [16, 16, 80, 3, 1, 1],
+            "repeats": 136,
+            "beforeMs": 0.07951058823529411,
+            "afterMs": 0.052043294117647056,
+            "speedup": 1.5277777777777777,
+            "samples": [
+              [
+                0.0756555294117647, 0.07999247058823529, 0.08770258823529412, 0.11613364705882354,
+                0.07951058823529411, 0.07806494117647059, 0.07902870588235295, 0.07902870588235295,
+                0.10215905882352941, 0.08384752941176471, 0.07902870588235295
+              ],
+              [
+                0.05059764705882353, 0.051079529411764704, 0.053488941176470586, 0.049152,
+                0.05059764705882353, 0.09203952941176471, 0.06939105882352942, 0.052043294117647056,
+                0.051079529411764704, 0.07420988235294118, 0.06023529411764706
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [32, 16, 40, 3, 1, 1],
+            "repeats": 272,
+            "beforeMs": 0.07083670588235294,
+            "afterMs": 0.06047623529411764,
+            "speedup": 1.1713147410358566,
+            "samples": [
+              [
+                0.07420988235294118, 0.05903058823529411, 0.07854682352941177, 0.08023341176470589,
+                0.07083670588235294, 0.059994352941176464, 0.07975152941176471, 0.06939105882352942,
+                0.06312658823529413, 0.07854682352941177, 0.05903058823529411
+              ],
+              [
+                0.06047623529411764, 0.07830588235294117, 0.07686023529411765, 0.06047623529411764,
+                0.06384941176470588, 0.07613741176470588, 0.05951247058823529, 0.06023529411764706,
+                0.06023529411764706, 0.05975341176470589, 0.06264470588235294
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [8, 16, 80, 3, 1, 1],
+            "repeats": 272,
+            "beforeMs": 0.06698164705882352,
+            "afterMs": 0.03300894117647059,
+            "speedup": 2.0291970802919708,
+            "samples": [
+              [
+                0.06890917647058824, 0.049392941176470584, 0.06818635294117648, 0.06264470588235294,
+                0.04770635294117647, 0.04794729411764706, 0.06987294117647058, 0.06842729411764706,
+                0.06698164705882352, 0.06915011764705882, 0.04794729411764706
+              ],
+              [
+                0.032768, 0.04770635294117647, 0.043369411764705885, 0.03662305882352941,
+                0.03252705882352941, 0.05469364705882353, 0.03300894117647059, 0.032286117647058826,
+                0.03204517647058824, 0.03300894117647059, 0.03517741176470588
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [16, 8, 80, 3, 1, 1],
+            "repeats": 272,
+            "beforeMs": 0.08336564705882353,
+            "afterMs": 0.05758494117647059,
+            "speedup": 1.4476987447698746,
+            "samples": [
+              [
+                0.07324611764705882, 0.09493082352941176, 0.09468988235294118, 0.09734023529411764,
+                0.07686023529411765, 0.09107576470588236, 0.07445082352941176, 0.0922804705882353,
+                0.08336564705882353, 0.077824, 0.07951058823529411
+              ],
+              [
+                0.06915011764705882, 0.049152, 0.049152, 0.06939105882352942, 0.06023529411764706,
+                0.04818823529411765, 0.05758494117647059, 0.054934588235294124, 0.049152,
+                0.06818635294117648, 0.07131858823529412
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [16, 16, 160, 3, 2, 1],
+            "repeats": 136,
+            "beforeMs": 0.07854682352941177,
+            "afterMs": 0.049152,
+            "speedup": 1.5980392156862746,
+            "samples": [
+              [
+                0.11131482352941177, 0.07613741176470588, 0.07276423529411766, 0.08047435294117647,
+                0.07854682352941177, 0.07517364705882353, 0.08481129411764705, 0.073728,
+                0.10986917647058825, 0.07613741176470588, 0.09348517647058824
+              ],
+              [
+                0.049152, 0.04867011764705882, 0.04867011764705882, 0.07420988235294118,
+                0.05011576470588235, 0.04818823529411765, 0.07661929411764705, 0.049152,
+                0.05059764705882353, 0.04867011764705882, 0.05927152941176471
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [32, 16, 20, 3, 1, 1],
+            "repeats": 512,
+            "beforeMs": 0.050688,
+            "afterMs": 0.062848,
+            "speedup": 0.8065173116089612,
+            "samples": [
+              [
+                0.051328, 0.046848, 0.05184, 0.04928, 0.043008, 0.046976, 0.050688, 0.051328,
+                0.051456, 0.052864, 0.045696
+              ],
+              [
+                0.061568, 0.056064, 0.063744, 0.061952, 0.062848, 0.067456, 0.063616, 0.063104,
+                0.062848, 0.06336, 0.061824
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [4, 13, 17, 3, 1, 1],
+            "repeats": 512,
+            "beforeMs": 0.01344,
+            "afterMs": 0.016384,
+            "speedup": 0.8203125000000001,
+            "samples": [
+              [
+                0.01344, 0.022912, 0.013056, 0.013184, 0.013312, 0.013184, 0.02304, 0.018432,
+                0.014848, 0.013184, 0.013568
+              ],
+              [
+                0.016, 0.015744, 0.016256, 0.024832, 0.021248, 0.01664, 0.017536, 0.015872,
+                0.016384, 0.02048, 0.015744
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float32",
+            "shape": [24, 16, 448, 3, 1, 1],
+            "repeats": 8,
+            "beforeMs": 2.818048,
+            "afterMs": 1.72032,
+            "speedup": 1.638095238095238,
+            "samples": [
+              [
+                2.818048, 2.859008, 2.82624, 2.78528, 3.104768, 3.260416, 2.760704, 3.342336,
+                2.78528, 2.818048, 2.736128
+              ],
+              [
+                1.671168, 1.957888, 2.064384, 1.703936, 1.695744, 1.695744, 2.154496, 1.72032,
+                1.671168, 2.146304, 2.162688
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [16, 16, 80, 3, 1, 1],
+            "repeats": 136,
+            "beforeMs": 0.061680941176470584,
+            "afterMs": 0.04385129411764706,
+            "speedup": 1.4065934065934065,
+            "samples": [
+              [
+                0.09493082352941176, 0.05975341176470589, 0.09685835294117648, 0.06071717647058823,
+                0.061680941176470584, 0.08336564705882353, 0.06601788235294118, 0.098304,
+                0.05927152941176471, 0.06023529411764706, 0.06119905882352941
+              ],
+              [
+                0.04240564705882353, 0.04433317647058824, 0.04385129411764706, 0.041923764705882355,
+                0.042887529411764706, 0.04240564705882353, 0.04529694117647059,
+                0.041923764705882355, 0.04433317647058824, 0.06987294117647058, 0.065536
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [32, 16, 40, 3, 1, 1],
+            "repeats": 272,
+            "beforeMs": 0.052043294117647056,
+            "afterMs": 0.06144,
+            "speedup": 0.8470588235294116,
+            "samples": [
+              [
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+                0.051320470588235294, 0.06625882352941177, 0.052043294117647056, 0.0677044705882353,
+                0.052043294117647056, 0.052043294117647056, 0.06481317647058824
+              ],
+              [
+                0.05613929411764706, 0.0715595294117647, 0.05517552941176471, 0.06312658823529413,
+                0.06144, 0.06023529411764706, 0.073728, 0.055657411764705886, 0.0652950588235294,
+                0.06649976470588236, 0.05589835294117647
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [8, 16, 80, 3, 1, 1],
+            "repeats": 272,
+            "beforeMs": 0.053488941176470586,
+            "afterMs": 0.028190117647058824,
+            "speedup": 1.8974358974358974,
+            "samples": [
+              [
+                0.053488941176470586, 0.05927152941176471, 0.057344000000000006,
+                0.05686211764705882, 0.03855058823529412, 0.05854870588235294, 0.03806870588235294,
+                0.039032470588235293, 0.052284235294117645, 0.039755294117647055,
+                0.05445270588235294
+              ],
+              [
+                0.02722635294117647, 0.02891294117647059, 0.026744470588235293,
+                0.029394823529411765, 0.028190117647058824, 0.027949176470588234,
+                0.027949176470588234, 0.0469835294117647, 0.028190117647058824, 0.04553788235294118,
+                0.026744470588235293
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [16, 8, 80, 3, 1, 1],
+            "repeats": 272,
+            "beforeMs": 0.07686023529411765,
+            "afterMs": 0.043369411764705885,
+            "speedup": 1.7722222222222221,
+            "samples": [
+              [
+                0.06674070588235294, 0.07975152941176471, 0.07686023529411765, 0.05951247058823529,
+                0.07902870588235295, 0.06649976470588236, 0.08529317647058823, 0.07710117647058824,
+                0.07830588235294117, 0.0657769411764706, 0.06240376470588235
+              ],
+              [
+                0.04770635294117647, 0.04312847058823529, 0.04312847058823529, 0.05951247058823529,
+                0.04240564705882353, 0.065536, 0.04240564705882353, 0.043369411764705885,
+                0.043369411764705885, 0.06264470588235294, 0.04626070588235294
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [16, 16, 160, 3, 2, 1],
+            "repeats": 136,
+            "beforeMs": 0.06505411764705882,
+            "afterMs": 0.04481505882352941,
+            "speedup": 1.4516129032258065,
+            "samples": [
+              [
+                0.09348517647058824, 0.07806494117647059, 0.06312658823529413, 0.09444894117647058,
+                0.05878964705882353, 0.07420988235294118, 0.06505411764705882, 0.06023529411764706,
+                0.06071717647058823, 0.06071717647058823, 0.07613741176470588
+              ],
+              [
+                0.042887529411764706, 0.04481505882352941, 0.04240564705882353, 0.04385129411764706,
+                0.04481505882352941, 0.05927152941176471, 0.041923764705882355, 0.06698164705882352,
+                0.08240188235294119, 0.042887529411764706, 0.04577882352941177
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [32, 16, 20, 3, 1, 1],
+            "repeats": 512,
+            "beforeMs": 0.04608,
+            "afterMs": 0.059264,
+            "speedup": 0.777537796976242,
+            "samples": [
+              [
+                0.046848, 0.04608, 0.03776, 0.045568, 0.0384, 0.047232, 0.046464, 0.03776, 0.047104,
+                0.046592, 0.044288
+              ],
+              [
+                0.0672, 0.05184, 0.058496, 0.059264, 0.060288, 0.061568, 0.059008, 0.059264,
+                0.05952, 0.059904, 0.05248
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [4, 13, 17, 3, 1, 1],
+            "repeats": 512,
+            "beforeMs": 0.013568,
+            "afterMs": 0.018304,
+            "speedup": 0.7412587412587412,
+            "samples": [
+              [
+                0.022528, 0.013568, 0.015616, 0.012416, 0.022016, 0.018432, 0.01472, 0.013184,
+                0.012544, 0.012544, 0.012672
+              ],
+              [
+                0.01536, 0.018304, 0.020224, 0.016256, 0.016896, 0.016256, 0.016512, 0.022144,
+                0.018944, 0.0192, 0.022272
+              ]
+            ]
+          },
+          {
+            "maxDelta": 0,
+            "category": "convolution",
+            "dtype": "float16",
+            "shape": [24, 16, 448, 3, 1, 1],
+            "repeats": 8,
+            "beforeMs": 2.039808,
+            "afterMs": 1.302528,
+            "speedup": 1.5660377358490567,
+            "samples": [
+              [
+                2.433024, 1.974272, 2.465792, 1.949696, 2.506752, 2.00704, 2.187264, 2.039808,
+                1.96608, 2.490368, 1.974272
+              ],
+              [
+                1.302528, 1.67936, 1.31072, 1.343488, 1.302528, 1.26976, 1.302528, 1.39264,
+                1.302528, 1.294336, 1.343488
+              ]
+            ]
+          }
+        ]
+      },
+      "models": {
+        "baseline": "308cc40",
+        "warmups": 10,
+        "samples": 51,
+        "results": [
+          {
+            "model": "depthart",
+            "dtype": "float32",
+            "beforeMs": 14.985584000000017,
+            "afterMs": 14.936333999999988,
+            "speedup": 1.0032973285144822,
+            "maxDelta": 0,
+            "samples": [
+              [
+                14.985584000000017, 15.059374999999818, 15.024082999999791, 15.033042000000023,
+                14.979832999999871, 14.9965830000001, 14.864583000000039, 14.91358299999979,
+                14.872000000000071, 14.84354200000007, 14.86262499999998, 14.909542000000101,
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+        "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
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+    }
+  ]
+}
diff --git a/utils/benchmark/pipeline-results.json b/utils/benchmark/pipeline-results.json
new file mode 100644
index 0000000..f26b0c8
--- /dev/null
+++ b/utils/benchmark/pipeline-results.json
@@ -0,0 +1,8632 @@
+{
+  "baseline": "6673d3d870e1ce86ddb363c1c21a7de6fbde9172",
+  "method": "Instrument actual example loops with CPU clocks and GPU pass timestamps. Synthetic video; no camera permissions. Warmup frames excluded. Configurations run sequentially; model clock variation prevents interpreting total frame differences as presentation speedups.",
+  "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
+  "results": [
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+      "precision": "float32",
+      "presentation": "current",
+      "warmups": 30,
+      "samples": 80,
+      "gpu": {
+        "vendor": "apple",
+        "architecture": "metal-3"
+      },
+      "browser": "Mozilla/5.0 (Macintosh; Intel Mac OS X 10_15_7) AppleWebKit/537.36 (KHTML, like Gecko) HeadlessChrome/155.0.0.0 Safari/537.36",
+      "source": "1280x720 animated canvas captured as a 30fps HTMLVideoElement",
+      "timing": "GPU timestamps on the actual three compute passes; CPU clocks for crop/upload calls, encoding and frame-fence completion. One additional timestamp readback alongside the existing frame fence adds profiling overhead. Medians are not additive because CPU and GPU work can overlap.",
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+      ],
+      "note": "outsideComputeSpanWallMs includes crop, upload/conversion, presentation, queue scheduling and browser callback latency; it is not all postprocessing work.",
+      "errors": []
+    }
+  ]
+}
diff --git a/utils/benchmark/pointwise-results.json b/utils/benchmark/pointwise-results.json
new file mode 100644
index 0000000..bef2de0
--- /dev/null
+++ b/utils/benchmark/pointwise-results.json
@@ -0,0 +1,25008 @@
+{
+  "baseline": "1c0bb98",
+  "decision": "Retain existing production kernels and dispatch rules. No tested candidate demonstrated a repeatable full-YOLO improvement large enough to justify replacing them.",
+  "findings": [
+    "Larger K tiles reduced barriers but were mixed or slower across shapes; FP16 K=64 substantially regressed several common cases.",
+    "The 128-thread 8x4 layout did not improve full-model performance.",
+    "Existing 32x64 tiles improved several late/small or channel-tail microbenchmarks, but whole-model results varied: Node YOLO FP16 10.424->10.282 ms, Chrome 11.1->11.6 ms; the unchanged DepthART control also shifted in some comparisons.",
+    "Two subgroup prototypes were correct but slower on most tested shapes; this does not rule out better subgroup algorithms or benefits on other hardware/operators.",
+    "All recorded successful comparisons had finite outputs and maxDelta=0. Early prototype sweeps checked validation errors at the end; later runs checked them per pipeline and used NaN output sentinels.",
+    "Raw kernel timings use fixed recorded repeated dispatches and GPU timestamps. Model timings use recorded graphs, submit plus sync wall time; excludes camera and pre/post/presentation. Raw-kernel speedups are not model speedups.",
+    "Single-machine Apple M1 Pro / Metal observations do not establish cross-hardware performance."
+  ],
+  "runs": [
+    {
+      "experiment": "larger reduction tiles",
+      "configuration": "Flattened workgroup arrays; original workgroup sizes. Raw candidates use K=16/32, plus 64 in FP16; model candidates use the flattened K=16 implementation for plain and clamped operators.",
+      "report": {
+        "baseline": "1c0bb98",
+        "method": "Compare pointwise reduction tiles against archived source; see per-run details.",
+        "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
+        "results": [
+          {
+            "precision": "float32",
+            "warmups": 4,
+            "samples": 31,
+            "gpu": {
+              "vendor": "apple",
+              "architecture": "metal-3"
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+            "browser": "Mozilla/5.0 (Macintosh; Intel Mac OS X 10_15_7) AppleWebKit/537.36 (KHTML, like Gecko) HeadlessChrome/155.0.0.0 Safari/537.36",
+            "method": "Same-device alternating baseline/candidate measurements; Configured warmups/samples, alternating baseline and candidate. Kernels: recorded repeated dispatches, GPU timestamps per dispatch. Models: unchanged graphs and identical inputs, submit + sync wall clock. Model baseline is archived source; raw kernel comparisons sweep reduction sizes 16/32 and 64 for FP16 against archived pointwise kernels. All outputs must match bitwise.",
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+        "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
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+        "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
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+        "method": "Compare pointwise reduction tiles against archived source; see per-run details.",
+        "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
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+      "report": {
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+        "method": "Compare pointwise reduction tiles against archived source; see per-run details.",
+        "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
+        "results": [
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+    "direct": {
+      "src/shaders/convolution/conv2d-1x1-subgroup-f16.wgsl.ts": "/**\n * Subgroup pointwise convolution prototype: a 32x128 output tile, eight rows\n * per subgroup and four spatial elements per lane. No workgroup scratch/barriers.\n * Uses reported subgroup IDs/sizes; it does not infer lane layout from local IDs.\n * Source: https://github.com/barhanc/wgpu-executorch\n * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)\n */\nexport const SHADER_CONV2D_1X1_SUBGROUP_F16 = /* wgsl */ `\nrequires subgroup_id;\nenable subgroups;\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> out: array<vec4<f16>>;\n@group(0) @binding(1) var<storage, read> input: array<vec4<f16>>;\n@group(0) @binding(2) var<storage, read> weight: array<vec4<f16>>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\n\nstruct Params {\n  B: u32, IC: u32, IH: u32, IW: u32,\n  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,\n  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,\n  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,\n}\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n@compute @workgroup_size(128)\nfn main(\n  @builtin(workgroup_id) group: vec3<u32>,\n  @builtin(subgroup_id) subgroup: u32,\n  @builtin(num_subgroups) subgroup_count: u32,\n  @builtin(subgroup_invocation_id) lane: u32,\n  @builtin(subgroup_size) lanes: u32,\n) {\n  let M = params.OC;\n  let N_vecs = (params.OH * params.OW) >> 2u;\n  let K_vecs = params.IC >> 2u;\n  let k_groups = ((params.IC + 15u) >> 4u) * 4u;\n  for (var row_block = 0u; row_block < 32u; row_block += subgroup_count * 8u) {\n    let row_relative = row_block + subgroup * 8u;\n    let row_base = group.y * 32u + row_relative;\n    for (var col_block = 0u; col_block < 32u; col_block += lanes) {\n      let col = group.x * 32u + col_block + lane;\n      let valid_col = col_block + lane < 32u && col < N_vecs;\n      var acc0 = vec4<f16>(0.0h);\n      var acc1 = vec4<f16>(0.0h);\n      var acc2 = vec4<f16>(0.0h);\n      var acc3 = vec4<f16>(0.0h);\n      var acc4 = vec4<f16>(0.0h);\n      var acc5 = vec4<f16>(0.0h);\n      var acc6 = vec4<f16>(0.0h);\n      var acc7 = vec4<f16>(0.0h);\n      for (var k4 = 0u; k4 < k_groups; k4++) {\n        var weight0 = vec4<f16>(0.0h);\n        var weight1 = vec4<f16>(0.0h);\n        if (lane < 4u && k4 < K_vecs) {\n          if (row_relative + lane < 32u && row_base + lane < M) {\n            weight0 = weight[(row_base + lane) * K_vecs + k4];\n          }\n          if (row_relative + lane + 4u < 32u && row_base + lane + 4u < M) {\n            weight1 = weight[(row_base + lane + 4u) * K_vecs + k4];\n          }\n        }\n        let a0 = subgroupBroadcast(weight0, 0u);\n        let a1 = subgroupBroadcast(weight0, 1u);\n        let a2 = subgroupBroadcast(weight0, 2u);\n        let a3 = subgroupBroadcast(weight0, 3u);\n        let a4 = subgroupBroadcast(weight1, 0u);\n        let a5 = subgroupBroadcast(weight1, 1u);\n        let a6 = subgroupBroadcast(weight1, 2u);\n        let a7 = subgroupBroadcast(weight1, 3u);\n        var b0 = vec4<f16>(0.0h);\n        var b1 = vec4<f16>(0.0h);\n        var b2 = vec4<f16>(0.0h);\n        var b3 = vec4<f16>(0.0h);\n        if (valid_col && k4 < K_vecs) {\n          b0 = input[(k4 * 4u + 0u) * N_vecs + col];\n          b1 = input[(k4 * 4u + 1u) * N_vecs + col];\n          b2 = input[(k4 * 4u + 2u) * N_vecs + col];\n          b3 = input[(k4 * 4u + 3u) * N_vecs + col];\n        }\n        acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;\n        acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;\n        acc2 = acc2 + b0 * a2.x + b1 * a2.y + b2 * a2.z + b3 * a2.w;\n        acc3 = acc3 + b0 * a3.x + b1 * a3.y + b2 * a3.z + b3 * a3.w;\n        acc4 = acc4 + b0 * a4.x + b1 * a4.y + b2 * a4.z + b3 * a4.w;\n        acc5 = acc5 + b0 * a5.x + b1 * a5.y + b2 * a5.z + b3 * a5.w;\n        acc6 = acc6 + b0 * a6.x + b1 * a6.y + b2 * a6.z + b3 * a6.w;\n        acc7 = acc7 + b0 * a7.x + b1 * a7.y + b2 * a7.z + b3 * a7.w;\n      }\n      if (valid_col) {\n        if (row_relative + 0u < 32u && row_base + 0u < M) {\n          var value = acc0;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 0u]); }\n          out[(row_base + 0u) * N_vecs + col] = value;\n        }\n        if (row_relative + 1u < 32u && row_base + 1u < M) {\n          var value = acc1;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 1u]); }\n          out[(row_base + 1u) * N_vecs + col] = value;\n        }\n        if (row_relative + 2u < 32u && row_base + 2u < M) {\n          var value = acc2;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 2u]); }\n          out[(row_base + 2u) * N_vecs + col] = value;\n        }\n        if (row_relative + 3u < 32u && row_base + 3u < M) {\n          var value = acc3;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 3u]); }\n          out[(row_base + 3u) * N_vecs + col] = value;\n        }\n        if (row_relative + 4u < 32u && row_base + 4u < M) {\n          var value = acc4;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 4u]); }\n          out[(row_base + 4u) * N_vecs + col] = value;\n        }\n        if (row_relative + 5u < 32u && row_base + 5u < M) {\n          var value = acc5;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 5u]); }\n          out[(row_base + 5u) * N_vecs + col] = value;\n        }\n        if (row_relative + 6u < 32u && row_base + 6u < M) {\n          var value = acc6;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 6u]); }\n          out[(row_base + 6u) * N_vecs + col] = value;\n        }\n        if (row_relative + 7u < 32u && row_base + 7u < M) {\n          var value = acc7;\n          if (params.has_bias != 0u) { value += vec4<f16>(bias[row_base + 7u]); }\n          out[(row_base + 7u) * N_vecs + col] = value;\n        }\n      }\n    }\n  }\n}\n`;\n",
+      "src/shaders/convolution/conv2d-1x1-subgroup.wgsl.ts": "/**\n * Subgroup pointwise convolution prototype: a 32x128 output tile, eight rows\n * per subgroup and four spatial elements per lane. No workgroup scratch/barriers.\n * Uses reported subgroup IDs/sizes; it does not infer lane layout from local IDs.\n * Source: https://github.com/barhanc/wgpu-executorch\n * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)\n */\nexport const SHADER_CONV2D_1X1_SUBGROUP = /* wgsl */ `\nrequires subgroup_id;\nenable subgroups;\n\n@group(0) @binding(0) var<storage, read_write> out: array<vec4<f32>>;\n@group(0) @binding(1) var<storage, read> input: array<vec4<f32>>;\n@group(0) @binding(2) var<storage, read> weight: array<vec4<f32>>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\n\nstruct Params {\n  B: u32, IC: u32, IH: u32, IW: u32,\n  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,\n  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,\n  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,\n}\n@group(0) @binding(4) var<uniform> params: Params;\n\n\n@compute @workgroup_size(128)\nfn main(\n  @builtin(workgroup_id) group: vec3<u32>,\n  @builtin(subgroup_id) subgroup: u32,\n  @builtin(num_subgroups) subgroup_count: u32,\n  @builtin(subgroup_invocation_id) lane: u32,\n  @builtin(subgroup_size) lanes: u32,\n) {\n  let M = params.OC;\n  let N_vecs = (params.OH * params.OW) >> 2u;\n  let K_vecs = params.IC >> 2u;\n  let k_groups = ((params.IC + 15u) >> 4u) * 4u;\n  for (var row_block = 0u; row_block < 32u; row_block += subgroup_count * 8u) {\n    let row_relative = row_block + subgroup * 8u;\n    let row_base = group.y * 32u + row_relative;\n    for (var col_block = 0u; col_block < 32u; col_block += lanes) {\n      let col = group.x * 32u + col_block + lane;\n      let valid_col = col_block + lane < 32u && col < N_vecs;\n      var acc0 = vec4<f32>(0.0);\n      var acc1 = vec4<f32>(0.0);\n      var acc2 = vec4<f32>(0.0);\n      var acc3 = vec4<f32>(0.0);\n      var acc4 = vec4<f32>(0.0);\n      var acc5 = vec4<f32>(0.0);\n      var acc6 = vec4<f32>(0.0);\n      var acc7 = vec4<f32>(0.0);\n      for (var k4 = 0u; k4 < k_groups; k4++) {\n        var weight0 = vec4<f32>(0.0);\n        var weight1 = vec4<f32>(0.0);\n        if (lane < 4u && k4 < K_vecs) {\n          if (row_relative + lane < 32u && row_base + lane < M) {\n            weight0 = weight[(row_base + lane) * K_vecs + k4];\n          }\n          if (row_relative + lane + 4u < 32u && row_base + lane + 4u < M) {\n            weight1 = weight[(row_base + lane + 4u) * K_vecs + k4];\n          }\n        }\n        let a0 = subgroupBroadcast(weight0, 0u);\n        let a1 = subgroupBroadcast(weight0, 1u);\n        let a2 = subgroupBroadcast(weight0, 2u);\n        let a3 = subgroupBroadcast(weight0, 3u);\n        let a4 = subgroupBroadcast(weight1, 0u);\n        let a5 = subgroupBroadcast(weight1, 1u);\n        let a6 = subgroupBroadcast(weight1, 2u);\n        let a7 = subgroupBroadcast(weight1, 3u);\n        var b0 = vec4<f32>(0.0);\n        var b1 = vec4<f32>(0.0);\n        var b2 = vec4<f32>(0.0);\n        var b3 = vec4<f32>(0.0);\n        if (valid_col && k4 < K_vecs) {\n          b0 = input[(k4 * 4u + 0u) * N_vecs + col];\n          b1 = input[(k4 * 4u + 1u) * N_vecs + col];\n          b2 = input[(k4 * 4u + 2u) * N_vecs + col];\n          b3 = input[(k4 * 4u + 3u) * N_vecs + col];\n        }\n        acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;\n        acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;\n        acc2 = acc2 + b0 * a2.x + b1 * a2.y + b2 * a2.z + b3 * a2.w;\n        acc3 = acc3 + b0 * a3.x + b1 * a3.y + b2 * a3.z + b3 * a3.w;\n        acc4 = acc4 + b0 * a4.x + b1 * a4.y + b2 * a4.z + b3 * a4.w;\n        acc5 = acc5 + b0 * a5.x + b1 * a5.y + b2 * a5.z + b3 * a5.w;\n        acc6 = acc6 + b0 * a6.x + b1 * a6.y + b2 * a6.z + b3 * a6.w;\n        acc7 = acc7 + b0 * a7.x + b1 * a7.y + b2 * a7.z + b3 * a7.w;\n      }\n      if (valid_col) {\n        if (row_relative + 0u < 32u && row_base + 0u < M) {\n          var value = acc0;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 0u]); }\n          out[(row_base + 0u) * N_vecs + col] = value;\n        }\n        if (row_relative + 1u < 32u && row_base + 1u < M) {\n          var value = acc1;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 1u]); }\n          out[(row_base + 1u) * N_vecs + col] = value;\n        }\n        if (row_relative + 2u < 32u && row_base + 2u < M) {\n          var value = acc2;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 2u]); }\n          out[(row_base + 2u) * N_vecs + col] = value;\n        }\n        if (row_relative + 3u < 32u && row_base + 3u < M) {\n          var value = acc3;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 3u]); }\n          out[(row_base + 3u) * N_vecs + col] = value;\n        }\n        if (row_relative + 4u < 32u && row_base + 4u < M) {\n          var value = acc4;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 4u]); }\n          out[(row_base + 4u) * N_vecs + col] = value;\n        }\n        if (row_relative + 5u < 32u && row_base + 5u < M) {\n          var value = acc5;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 5u]); }\n          out[(row_base + 5u) * N_vecs + col] = value;\n        }\n        if (row_relative + 6u < 32u && row_base + 6u < M) {\n          var value = acc6;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 6u]); }\n          out[(row_base + 6u) * N_vecs + col] = value;\n        }\n        if (row_relative + 7u < 32u && row_base + 7u < M) {\n          var value = acc7;\n          if (params.has_bias != 0u) { value += vec4<f32>(bias[row_base + 7u]); }\n          out[(row_base + 7u) * N_vecs + col] = value;\n        }\n      }\n    }\n  }\n}\n`;\n"
+    },
+    "hybrid": {
+      "src/shaders/convolution/conv2d-1x1-subgroup-f16.wgsl.ts": "/**\n * WGSL compute shader for 64x64 register-tiled 1x1 convolution in float16 (B = 1, 4x4 per thread across 256 threads).\n * Shares inputs through workgroup memory and weights through subgroup shuffles.\n * Requires subgroup sizes divisible by 16; other devices retain the existing kernel.\n *\n * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)\n * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)\n */\nexport const SHADER_CONV2D_1X1_SUBGROUP_F16 = /* wgsl */ `\nrequires subgroup_id;\nenable subgroups;\n\nenable f16;\n\n@group(0) @binding(0) var<storage, read_write> out: array<vec4<f16>>;\n@group(0) @binding(1) var<storage, read> input: array<vec4<f16>>;\n@group(0) @binding(2) var<storage, read> weight: array<vec4<f16>>;\n@group(0) @binding(3) var<storage, read> bias: array<f16>;\n\nstruct Params {\n  B: u32, IC: u32, IH: u32, IW: u32,\n  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,\n  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,\n  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,\n}\n@group(0) @binding(4) var<uniform> params: Params;\n\n// 64 rows x 16 K elements (4 vec4s) = 256 vec4s (2 KB)\n\n// 16 K rows x 64 N elements (16 vec4s) = 256 vec4s (2 KB)\nvar<workgroup> b_sub: array<array<vec4<f16>, 16>, 16>;\n\n@compute @workgroup_size(16, 16, 1)\nfn main(\n  @builtin(workgroup_id) wg_id: vec3<u32>,\n  @builtin(local_invocation_id) local_id: vec3<u32>,\n  @builtin(subgroup_id) subgroup: u32,\n  @builtin(subgroup_invocation_id) lane: u32,\n  @builtin(subgroup_size) lanes: u32\n) {\n  let M = params.OC;\n  let N = params.OH * params.OW;\n  let K = params.IC;\n  let K_vecs = K >> 2u;\n  let N_vecs = N >> 2u;\n\n  let tile_row0 = wg_id.y * 64u;\n  let tile_col0_4 = wg_id.x * 16u;\n  let tid = local_id.y * 16u + local_id.x; // 0..255\n\n  var acc0 = vec4<f16>(0.0h);\n  var acc1 = vec4<f16>(0.0h);\n  var acc2 = vec4<f16>(0.0h);\n  var acc3 = vec4<f16>(0.0h);\n\n  // Load coordinates for 256 threads (each thread loads 1 vec4 of A/weight and 1 vec4 of B/input)\n  let rows_per_subgroup = lanes >> 2u;\n  let subgroup_row = subgroup * rows_per_subgroup;\n  let weight_row = tile_row0 + subgroup_row + lane;\n  let weight_lane_valid = lane < rows_per_subgroup && weight_row < M;\n\n  let b_r = tid >> 4u;      // 0..15\n  let b_c = tid & 15u;      // 0..15\n  let b_n4 = tile_col0_4 + b_c;\n  let b_c_valid = b_n4 < N_vecs;\n\n  let num_tiles = (K + 15u) >> 4u;\n  for (var t: u32 = 0u; t < num_tiles; t = t + 1u) {\n    let k4_start = t << 2u;\n    let k_start = t << 4u;\n\n    let bk = k_start + b_r;\n    if (bk < K && b_c_valid) {\n      b_sub[b_r][b_c] = input[bk * N_vecs + b_n4];\n    } else {\n      b_sub[b_r][b_c] = vec4<f16>(0.0h);\n    }\n    workgroupBarrier();\n\n    let thread_r = subgroup_row + ((lane >> 4u) << 2u); // 0..60 (step 4)\n    let thread_c4 = lane & 15u;      // 0..15\n\n    for (var k4: u32 = 0u; k4 < 4u; k4 = k4 + 1u) {\n      let b0 = b_sub[k4 * 4u + 0u][thread_c4];\n      let b1 = b_sub[k4 * 4u + 1u][thread_c4];\n      let b2 = b_sub[k4 * 4u + 2u][thread_c4];\n      let b3 = b_sub[k4 * 4u + 3u][thread_c4];\n\n      var weight_value = vec4<f16>(0.0h);\n      if (weight_lane_valid && k4_start + k4 < K_vecs) {\n        weight_value = weight[weight_row * K_vecs + k4_start + k4];\n      }\n      let source_row = (lane >> 4u) << 2u;\n      let a0 = subgroupShuffle(weight_value, source_row + 0u);\n      let a1 = subgroupShuffle(weight_value, source_row + 1u);\n      let a2 = subgroupShuffle(weight_value, source_row + 2u);\n      let a3 = subgroupShuffle(weight_value, source_row + 3u);\n\n      acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;\n      acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;\n      acc2 = acc2 + b0 * a2.x + b1 * a2.y + b2 * a2.z + b3 * a2.w;\n      acc3 = acc3 + b0 * a3.x + b1 * a3.y + b2 * a3.z + b3 * a3.w;\n    }\n    workgroupBarrier();\n  }\n\n  let thread_r = subgroup_row + ((lane >> 4u) << 2u);\n  let out_r0 = tile_row0 + thread_r;\n  let out_c4 = tile_col0_4 + (lane & 15u);\n\n  if (out_c4 < N_vecs) {\n    if (out_r0 + 0u < M) {\n      var v0 = acc0;\n      if (params.has_bias != 0u) { v0 = v0 + vec4<f16>(bias[out_r0 + 0u]); }\n      out[(out_r0 + 0u) * N_vecs + out_c4] = v0;\n    }\n    if (out_r0 + 1u < M) {\n      var v1 = acc1;\n      if (params.has_bias != 0u) { v1 = v1 + vec4<f16>(bias[out_r0 + 1u]); }\n      out[(out_r0 + 1u) * N_vecs + out_c4] = v1;\n    }\n    if (out_r0 + 2u < M) {\n      var v2 = acc2;\n      if (params.has_bias != 0u) { v2 = v2 + vec4<f16>(bias[out_r0 + 2u]); }\n      out[(out_r0 + 2u) * N_vecs + out_c4] = v2;\n    }\n    if (out_r0 + 3u < M) {\n      var v3 = acc3;\n      if (params.has_bias != 0u) { v3 = v3 + vec4<f16>(bias[out_r0 + 3u]); }\n      out[(out_r0 + 3u) * N_vecs + out_c4] = v3;\n    }\n  }\n}\n`;\n",
+      "src/shaders/convolution/conv2d-1x1-subgroup.wgsl.ts": "/**\n * WGSL compute shader for 64x64 register-tiled 1x1 convolution (B = 1, 4x4 per thread across 256 threads).\n * Shares inputs through workgroup memory and weights through subgroup shuffles.\n * Requires subgroup sizes divisible by 16; other devices retain the existing kernel.\n *\n * Source: wgpu-executorch (https://github.com/barhanc/wgpu-executorch)\n * License: MIT (Copyright (c) 2026 Bartosz Hanc <bartosz.hanc02@gmail.com>)\n */\nexport const SHADER_CONV2D_1X1_SUBGROUP = /* wgsl */ `\nrequires subgroup_id;\nenable subgroups;\n\n@group(0) @binding(0) var<storage, read_write> out: array<vec4<f32>>;\n@group(0) @binding(1) var<storage, read> input: array<vec4<f32>>;\n@group(0) @binding(2) var<storage, read> weight: array<vec4<f32>>;\n@group(0) @binding(3) var<storage, read> bias: array<f32>;\n\nstruct Params {\n  B: u32, IC: u32, IH: u32, IW: u32,\n  OC: u32, OH: u32, OW: u32, KH: u32, KW: u32,\n  sH: u32, sW: u32, pH: u32, pW: u32, dH: u32, dW: u32,\n  groups: u32, has_bias: u32, _p0: u32, _p1: u32, _p2: u32,\n}\n@group(0) @binding(4) var<uniform> params: Params;\n\n// 64 rows x 16 K elements (4 vec4s) = 256 vec4s (4 KB)\n\n// 16 K rows x 64 N elements (16 vec4s) = 256 vec4s (4 KB)\nvar<workgroup> b_sub: array<array<vec4<f32>, 16>, 16>;\n\n@compute @workgroup_size(16, 16, 1)\nfn main(\n  @builtin(workgroup_id) wg_id: vec3<u32>,\n  @builtin(local_invocation_id) local_id: vec3<u32>,\n  @builtin(subgroup_id) subgroup: u32,\n  @builtin(subgroup_invocation_id) lane: u32,\n  @builtin(subgroup_size) lanes: u32\n) {\n  let M = params.OC;\n  let N = params.OH * params.OW;\n  let K = params.IC;\n  let K_vecs = K >> 2u;\n  let N_vecs = N >> 2u;\n\n  let tile_row0 = wg_id.y * 64u;\n  let tile_col0_4 = wg_id.x * 16u;\n  let tid = local_id.y * 16u + local_id.x; // 0..255\n\n  var acc0 = vec4<f32>(0.0);\n  var acc1 = vec4<f32>(0.0);\n  var acc2 = vec4<f32>(0.0);\n  var acc3 = vec4<f32>(0.0);\n\n  // Load coordinates for 256 threads (each thread loads 1 vec4 of A/weight and 1 vec4 of B/input)\n  let rows_per_subgroup = lanes >> 2u;\n  let subgroup_row = subgroup * rows_per_subgroup;\n  let weight_row = tile_row0 + subgroup_row + lane;\n  let weight_lane_valid = lane < rows_per_subgroup && weight_row < M;\n\n  let b_r = tid >> 4u;      // 0..15\n  let b_c = tid & 15u;      // 0..15\n  let b_n4 = tile_col0_4 + b_c;\n  let b_c_valid = b_n4 < N_vecs;\n\n  let num_tiles = (K + 15u) >> 4u;\n  for (var t: u32 = 0u; t < num_tiles; t = t + 1u) {\n    let k4_start = t << 2u;\n    let k_start = t << 4u;\n\n    let bk = k_start + b_r;\n    if (bk < K && b_c_valid) {\n      b_sub[b_r][b_c] = input[bk * N_vecs + b_n4];\n    } else {\n      b_sub[b_r][b_c] = vec4<f32>(0.0);\n    }\n    workgroupBarrier();\n\n    let thread_r = subgroup_row + ((lane >> 4u) << 2u); // 0..60 (step 4)\n    let thread_c4 = lane & 15u;      // 0..15\n\n    for (var k4: u32 = 0u; k4 < 4u; k4 = k4 + 1u) {\n      let b0 = b_sub[k4 * 4u + 0u][thread_c4];\n      let b1 = b_sub[k4 * 4u + 1u][thread_c4];\n      let b2 = b_sub[k4 * 4u + 2u][thread_c4];\n      let b3 = b_sub[k4 * 4u + 3u][thread_c4];\n\n      var weight_value = vec4<f32>(0.0);\n      if (weight_lane_valid && k4_start + k4 < K_vecs) {\n        weight_value = weight[weight_row * K_vecs + k4_start + k4];\n      }\n      let source_row = (lane >> 4u) << 2u;\n      let a0 = subgroupShuffle(weight_value, source_row + 0u);\n      let a1 = subgroupShuffle(weight_value, source_row + 1u);\n      let a2 = subgroupShuffle(weight_value, source_row + 2u);\n      let a3 = subgroupShuffle(weight_value, source_row + 3u);\n\n      acc0 = acc0 + b0 * a0.x + b1 * a0.y + b2 * a0.z + b3 * a0.w;\n      acc1 = acc1 + b0 * a1.x + b1 * a1.y + b2 * a1.z + b3 * a1.w;\n      acc2 = acc2 + b0 * a2.x + b1 * a2.y + b2 * a2.z + b3 * a2.w;\n      acc3 = acc3 + b0 * a3.x + b1 * a3.y + b2 * a3.z + b3 * a3.w;\n    }\n    workgroupBarrier();\n  }\n\n  let thread_r = subgroup_row + ((lane >> 4u) << 2u);\n  let out_r0 = tile_row0 + thread_r;\n  let out_c4 = tile_col0_4 + (lane & 15u);\n\n  if (out_c4 < N_vecs) {\n    if (out_r0 + 0u < M) {\n      var v0 = acc0;\n      if (params.has_bias != 0u) { v0 = v0 + vec4<f32>(bias[out_r0 + 0u]); }\n      out[(out_r0 + 0u) * N_vecs + out_c4] = v0;\n    }\n    if (out_r0 + 1u < M) {\n      var v1 = acc1;\n      if (params.has_bias != 0u) { v1 = v1 + vec4<f32>(bias[out_r0 + 1u]); }\n      out[(out_r0 + 1u) * N_vecs + out_c4] = v1;\n    }\n    if (out_r0 + 2u < M) {\n      var v2 = acc2;\n      if (params.has_bias != 0u) { v2 = v2 + vec4<f32>(bias[out_r0 + 2u]); }\n      out[(out_r0 + 2u) * N_vecs + out_c4] = v2;\n    }\n    if (out_r0 + 3u < M) {\n      var v3 = acc3;\n      if (params.has_bias != 0u) { v3 = v3 + vec4<f32>(bias[out_r0 + 3u]); }\n      out[(out_r0 + 3u) * N_vecs + out_c4] = v3;\n    }\n  }\n}\n`;\n"
+    }
+  }
+}
diff --git a/utils/benchmark/profile-hf.browser.mjs b/utils/benchmark/profile-hf.browser.mjs
new file mode 100644
index 0000000..38159ca
--- /dev/null
+++ b/utils/benchmark/profile-hf.browser.mjs
@@ -0,0 +1,392 @@
+// Compare pinned HF shader adaptations with this runtime on identical buffers.
+export async function profileHuggingFace(options) {
+  const { WgpuExecutionContext, shaders } = await import('/@fs' + options.repo + '/src/index.ts');
+  const { WgpuExecutionContext: BaselineContext, shaders: baselineShaders } = await import(
+    '/@fs' + options.baselineRepo + '/src/index.ts'
+  );
+  const { KernelTimingContext } = await import(
+    '/@fs' + options.repo + '/tests/helpers/kernel-timing.ts'
+  );
+  const { recordHfConvolution } = await import(
+    '/@fs' + options.repo + '/utils/benchmark/hf-convolution.ts'
+  );
+  const { recordHfMatrix } = await import('/@fs' + options.repo + '/utils/benchmark/hf-matrix.ts');
+  const adapter = await navigator.gpu.requestAdapter();
+  const half = options.precision === 'float16';
+  const matrixFeatures = [
+    'subgroups',
+    'subgroup-size-control',
+    'chromium-experimental-subgroup-matrix',
+  ];
+  const matrixAvailable =
+    matrixFeatures.every((name) => adapter.features.has(name)) &&
+    adapter.info.subgroupMinSize <= 32 &&
+    adapter.info.subgroupMaxSize >= 32 &&
+    Array.from(adapter.info.subgroupMatrixConfigs ?? []).some(
+      (c) => c.componentType === (half ? 'f16' : 'f32') && c.M === 8 && c.N === 8 && c.K === 8
+    );
+  const device = await adapter.requestDevice({
+    requiredLimits: {
+      maxComputeWorkgroupStorageSize: Math.min(
+        adapter.limits.maxComputeWorkgroupStorageSize,
+        32768
+      ),
+    },
+    requiredFeatures: [
+      'timestamp-query',
+      ...(half ? ['shader-f16'] : []),
+      ...(matrixAvailable ? matrixFeatures : []),
+    ],
+  });
+  const errors = [];
+  device.addEventListener('uncapturederror', (event) => errors.push(event.error.message));
+  const array = half ? Float16Array : Float32Array;
+  const fill = (length) =>
+    new array(Array.from({ length }, (_, i) => (((i * 17 + 11) % 61) - 30) / 64));
+  const median = (values) => [...values].sort((a, b) => a - b)[values.length >> 1];
+  async function measure(contexts, repeats = 1, gpu = false) {
+    const samples = contexts.map(() => []);
+    const warmups = options.warmups ?? 8,
+      count = options.samples ?? 51;
+    for (let i = -warmups; i < count; i++) {
+      // Rotate and reverse so each variant occupies every position repeatedly.
+      const order = contexts.map((_, j) => (j + i + warmups) % contexts.length);
+      if (i & 1) order.reverse();
+      for (const version of order) {
+        const start = performance.now();
+        contexts[version].submit();
+        await contexts[version].sync();
+        if (i >= 0)
+          samples[version].push(
+            (gpu ? contexts[version].gpuMs : performance.now() - start) / repeats
+          );
+      }
+    }
+    const medians = samples.map(median);
+    return { medians, samples, speedups: medians.map((ms) => medians[0] / ms), repeats };
+  }
+  const results = [];
+  try {
+    const matrixOracleChecks = [];
+    if (matrixAvailable) {
+      // Independent CPU oracle: batches, partial M/N/K tiles and absent bias.
+      for (const kernel of [1, 3]) {
+        const batch = 2,
+          ic = kernel === 1 ? 32 : 3,
+          oc = 17;
+        const h = kernel === 1 ? 8 : 9,
+          w = kernel === 1 ? 8 : 11;
+        const stride = kernel === 1 ? 1 : 2,
+          pad = kernel === 1 ? 0 : 1;
+        const oh = Math.floor((h + 2 * pad - kernel) / stride) + 1;
+        const ow = Math.floor((w + 2 * pad - kernel) / stride) + 1;
+        const ctx = new WgpuExecutionContext(device);
+        const xv = fill(batch * ic * h * w),
+          wv = fill(oc * ic * kernel * kernel);
+        const x = ctx.tensor(options.precision, [batch, ic, h, w]).setData(xv);
+        const weight = ctx.tensor(options.precision, [oc, ic, kernel, kernel]).setData(wv);
+        const y = ctx
+          .tensor(options.precision, [batch, oc, oh, ow])
+          .setData(new array(batch * oc * oh * ow).fill(NaN));
+        device.pushErrorScope('validation');
+        if (
+          !recordHfMatrix(ctx, [
+            x,
+            weight,
+            undefined,
+            [stride, stride],
+            [pad, pad],
+            [1, 1],
+            false,
+            [0, 0],
+            1,
+            y,
+          ])
+        )
+          throw new Error('Matrix oracle route unavailable');
+        const compileError = await device.popErrorScope();
+        if (compileError) throw new Error(compileError.message);
+        ctx.submit();
+        await ctx.sync();
+        const actual = new array(await y.getData());
+        let maxAbs = 0;
+        for (let b = 0; b < batch; b++)
+          for (let o = 0; o < oc; o++)
+            for (let iy = 0; iy < oh; iy++)
+              for (let ix = 0; ix < ow; ix++) {
+                let sum = 0;
+                for (let c = 0; c < ic; c++)
+                  for (let ky = 0; ky < kernel; ky++)
+                    for (let kx = 0; kx < kernel; kx++) {
+                      const sy = iy * stride - pad + ky,
+                        sx = ix * stride - pad + kx;
+                      if (sy >= 0 && sy < h && sx >= 0 && sx < w)
+                        sum +=
+                          xv[((b * ic + c) * h + sy) * w + sx] *
+                          wv[((o * ic + c) * kernel + ky) * kernel + kx];
+                    }
+                const value = actual[((b * oc + o) * oh + iy) * ow + ix];
+                if (!Number.isFinite(value))
+                  throw new Error('Nonfinite/missing matrix oracle output');
+                maxAbs = Math.max(maxAbs, Math.abs(value - new array([sum])[0]));
+              }
+        if (maxAbs > 1e-5) throw new Error(`Matrix CPU oracle error: ${maxAbs}`);
+        matrixOracleChecks.push({ kernel, batch, ic, oc, h, w, stride, pad, maxAbs });
+        ctx.destroy();
+      }
+    }
+    const cases = [
+      [48, 64, 160, 1, 1, 0],
+      [64, 64, 80, 1, 1, 0],
+      [96, 128, 80, 1, 1, 0],
+      [192, 128, 40, 1, 1, 0],
+      [256, 256, 20, 1, 1, 0],
+      [384, 256, 20, 1, 1, 0],
+      [80, 80, 80, 1, 1, 0],
+      [80, 80, 20, 1, 1, 0],
+      [32, 16, 80, 1, 1, 0],
+      [3, 16, 640, 3, 2, 1],
+      [16, 32, 320, 3, 2, 1],
+      [16, 8, 160, 3, 1, 1],
+      [32, 32, 40, 3, 1, 1],
+      [64, 64, 80, 3, 2, 1],
+      [128, 128, 40, 3, 2, 1],
+    ];
+    for (const shape of cases) {
+      const [ic, oc, h, kernel, stride, pad] = shape;
+      const oh = Math.floor((h + 2 * pad - kernel) / stride) + 1;
+      const owner = new WgpuExecutionContext(device);
+      const inputValues = fill(ic * h * h),
+        weightValues = fill(oc * ic * kernel * kernel),
+        biasValues = fill(oc);
+      const input = owner.tensor(options.precision, [1, ic, h, h]).setData(inputValues);
+      const weight = owner
+        .tensor(options.precision, [oc, ic, kernel, kernel])
+        .setData(weightValues);
+      const bias = owner.tensor(options.precision, [oc]).setData(biasValues);
+      const out = owner.tensor(options.precision, [1, oc, oh, oh]);
+      const args = [
+        input,
+        weight,
+        bias,
+        [stride, stride],
+        [pad, pad],
+        [1, 1],
+        false,
+        [0, 0],
+        1,
+        out,
+      ];
+      const repeats = Math.min(
+        128,
+        Math.max(4, Math.ceil(2e8 / (out.numel * ic * kernel * kernel)))
+      );
+      class RepeatedContext extends KernelTimingContext {
+        addDispatch(dispatch) {
+          for (let i = 0; i < repeats; i++) super.addDispatch(dispatch);
+        }
+      }
+      const contexts = Array.from(
+        { length: kernel === 3 ? 3 : 2 },
+        () => new RepeatedContext(device)
+      );
+      device.pushErrorScope('validation');
+      contexts[0].recordShader(baselineShaders.convolution, args);
+      if (!recordHfConvolution(contexts[1], args))
+        throw new Error('Unsupported HF benchmark shape');
+      if (kernel === 3) recordHfConvolution(contexts[2], args, 'both', 32);
+      const variants = kernel === 3 ? ['baseline', 'hf-m64', 'hf-m32'] : ['baseline', 'hf-m64'];
+      if (matrixAvailable) {
+        const matrixContext = new RepeatedContext(device);
+        if (recordHfMatrix(matrixContext, args)) {
+          contexts.push(matrixContext);
+          variants.push('hf-matrix');
+        } else matrixContext.destroy();
+      }
+      const compileError = await device.popErrorScope();
+      if (compileError) throw new Error(compileError.message);
+      const timing = await measure(contexts, repeats, true);
+      const values = [];
+      for (const ctx of contexts) {
+        out.setData(new array(out.numel).fill(NaN));
+        ctx.submit();
+        await ctx.sync();
+        values.push(new array(await out.getData()));
+      }
+      // Same rounded inputs, F32 arithmetic: tests the mixed-precision HF path
+      // independently of the baseline's FP16 accumulation differences.
+      const x32 = owner.tensor('float32', [1, ic, h, h]).setData(new Float32Array(inputValues));
+      const w32 = owner
+        .tensor('float32', [oc, ic, kernel, kernel])
+        .setData(new Float32Array(weightValues));
+      const b32 = owner.tensor('float32', [oc]).setData(new Float32Array(biasValues));
+      const y32 = owner.tensor('float32', [1, oc, oh, oh]);
+      owner.recordShader(shaders.convolution, [
+        x32,
+        w32,
+        b32,
+        [stride, stride],
+        [pad, pad],
+        [1, 1],
+        false,
+        [0, 0],
+        1,
+        y32,
+      ]);
+      owner.submit();
+      await owner.sync();
+      const reference = new array(new Float32Array(await y32.getData()));
+      const errorsVsReference = values.map((value) => {
+        let maxAbs = 0;
+        for (let i = 0; i < value.length; i++) {
+          if (!Number.isFinite(value[i])) throw new Error(`Nonfinite/missing output for ${shape}`);
+          maxAbs = Math.max(maxAbs, Math.abs(value[i] - reference[i]));
+        }
+        return maxAbs;
+      });
+      if (errorsVsReference.slice(1).some((error) => error > 1e-5))
+        throw new Error(`HF reference error for ${shape}: ${errorsVsReference[1]}`);
+      results.push({
+        category: 'kernel',
+        shape,
+        variants,
+        ...timing,
+        errorsVsFloat32Reference: errorsVsReference,
+      });
+      contexts.forEach((ctx) => ctx.destroy());
+      owner.destroy();
+    }
+    const suffix = half ? '-fp16' : '';
+    const [programResponse, weightsResponse, referenceResponse] = await Promise.all([
+      fetch(`/assets/yolo26n/program${suffix}.json`),
+      fetch(`/assets/yolo26n/weights${suffix}.bin`),
+      fetch(`/@fs${options.repo}/tests/fixtures/yolo26n/reference-output.f32`),
+    ]);
+    if (![programResponse, weightsResponse, referenceResponse].every((r) => r.ok))
+      throw new Error('Missing model artifacts/reference');
+    const program = await programResponse.json(),
+      weights = await weightsResponse.arrayBuffer();
+    const reference = new Float32Array(await referenceResponse.arrayBuffer());
+    class HfContext extends WgpuExecutionContext {
+      constructor(device, route) {
+        super(device);
+        this.route = route;
+        this.replaced = 0;
+      }
+      recordShader(shader, args) {
+        if (
+          shader.name === 'aten.convolution.default' &&
+          (this.route === 'matrix'
+            ? recordHfMatrix(this, args)
+            : recordHfConvolution(
+                this,
+                args,
+                this.route.replace('-m32', ''),
+                this.route.endsWith('-m32') ? 32 : 64
+              ))
+        ) {
+          this.replaced++;
+          return this;
+        }
+        return super.recordShader(shader, args);
+      }
+    }
+    const routes = [
+      'baseline',
+      '1x1',
+      '3x3',
+      'both',
+      '3x3-m32',
+      'both-m32',
+      ...(matrixAvailable ? ['matrix'] : []),
+    ];
+    const outputs = [];
+    const contexts = routes.map((route) => {
+      const ctx = route === 'baseline' ? new BaselineContext(device) : new HfContext(device, route);
+      const input = ctx.tensor(options.precision, program.values[program.inputIds[0]].shape);
+      input.setData(
+        new array(Array.from({ length: input.numel }, (_, i) => (i % 251) / 250 - 0.5))
+      );
+      const out = ctx.tensor(options.precision, program.values[program.outputIds[0]].shape);
+      out.setData(new array(out.numel).fill(NaN));
+      outputs.push(out);
+      ctx.recordProgram(program, weights, [input, out]);
+      return ctx;
+    });
+    const timing = await measure(contexts);
+    const validation = [];
+    for (let version = 0; version < contexts.length; version++) {
+      contexts[version].submit();
+      await contexts[version].sync();
+      const actual = new array(await outputs[version].getData());
+      let maxAbs = 0,
+        sumAbs = 0,
+        beyondTolerance = 0;
+      const tolerance = half ? 0.5 : 0.01;
+      for (let i = 0; i < actual.length; i++) {
+        if (!Number.isFinite(actual[i])) throw new Error('Nonfinite model output');
+        const delta = Math.abs(actual[i] - reference[i]);
+        maxAbs = Math.max(maxAbs, delta);
+        sumAbs += delta;
+        if (delta > tolerance) beyondTolerance++;
+      }
+      validation.push({
+        maxAbs,
+        meanAbs: sumAbs / actual.length,
+        beyondTolerance,
+        tolerance,
+        allowedBeyondTolerance: half ? Math.floor(actual.length * 0.05) : 0,
+        passesProjectReferenceTolerance: half
+          ? beyondTolerance <= actual.length * 0.05
+          : beyondTolerance === 0,
+      });
+    }
+    if (validation.some((v) => !v.passesProjectReferenceTolerance))
+      throw new Error('HF model variant failed the project PyTorch reference tolerance');
+    results.push({
+      category: 'model',
+      name: 'yolo26n',
+      routes,
+      replacedConvolutions: contexts.map((ctx) => ctx.replaced ?? 0),
+      ...timing,
+      validation,
+    });
+    contexts.forEach((ctx) => ctx.destroy());
+    if (errors.length) throw new Error(errors.join('\n'));
+    const result = {
+      precision: options.precision,
+      upstreamRevision: '7b19a1ea4fd2abef3203991ca933405f12cfcc62',
+      gpu: { vendor: adapter.info.vendor, architecture: adapter.info.architecture },
+      matrixAvailable,
+      matrixOracleChecks,
+      maxComputeWorkgroupStorageSize: device.limits.maxComputeWorkgroupStorageSize,
+      subgroupInfo: {
+        min: adapter.info.subgroupMinSize,
+        max: adapter.info.subgroupMaxSize,
+        matrixConfigs: Array.from(adapter.info.subgroupMatrixConfigs ?? [], (c) => ({
+          componentType: c.componentType,
+          resultComponentType: c.resultComponentType,
+          M: c.M,
+          N: c.N,
+          K: c.K,
+        })),
+      },
+      availableFeatures: [...adapter.features],
+      browser: navigator.userAgent,
+      method:
+        'Pinned HF register-tiled Conv template, 64x64 and 32x64/8x4 register layouts, carried implicit gathering (published default mode=1), K=32 when reduction divisible by 32 else 16; FP32 accumulation preserved. Bindings and geometry pipeline constants adapted. This is not the full HF loader/route-selection policy; split-K excluded. Aligned 1x1 and implicit 3x3 subgroup-matrix routes measured separately when experimental features are available; published f32 wide/f16 narrow tiles, direct inputs when aligned, subgroup size pinned to 32. Identical buffers/graphs, commands recorded once. Kernel timings: repeated dispatches, GPU timestamps. Model timings: rotated alternating submit+sync wall clock, no camera/pre/post/presentation. CPU-oracle tests cover the adapters; raw shaders compared to F32 arithmetic; models validated against project PyTorch fixtures.',
+      warmups: options.warmups ?? 8,
+      samples: options.samples ?? 51,
+      results,
+    };
+    const response = await fetch(options.reportEndpoint, {
+      method: 'POST',
+      headers: { 'Content-Type': 'application/json' },
+      body: JSON.stringify(result),
+    });
+    if (!response.ok) throw new Error(`Results upload failed: ${response.status}`);
+    return result;
+  } finally {
+    device.destroy();
+  }
+}
diff --git a/utils/benchmark/profile-live.browser.mjs b/utils/benchmark/profile-live.browser.mjs
new file mode 100644
index 0000000..0d67c4a
--- /dev/null
+++ b/utils/benchmark/profile-live.browser.mjs
@@ -0,0 +1,344 @@
+// Runs only inside a dedicated profiling page. Hooks are restored after each run;
+// the example and runtime do not acquire profiling overhead or new API contracts.
+export async function profileLivePipeline(options) {
+  const frames = [];
+  const pending = [];
+  const resources = [];
+  let frame = null;
+  let state = null;
+  let encoding = false;
+  let stop;
+  let timer;
+  let stream;
+  const errors = [];
+  const originals = {
+    requestDevice: GPUAdapter.prototype.requestDevice,
+    createEncoder: GPUDevice.prototype.createCommandEncoder,
+    createTexture: GPUDevice.prototype.createTexture,
+    configure: GPUCanvasContext.prototype.configure,
+    copyTexture: GPUCommandEncoder.prototype.copyTextureToTexture,
+    drawImage: OffscreenCanvasRenderingContext2D.prototype.drawImage,
+    upload: GPUQueue.prototype.copyExternalImageToTexture,
+    map: GPUBuffer.prototype.mapAsync,
+  };
+  const { WgpuExecutionContext } = await import('/@fs' + options.repo + '/src/index.ts');
+  originals.submit = WgpuExecutionContext.prototype.submit;
+  originals.recordShader = WgpuExecutionContext.prototype.recordShader;
+  const preferred = options.presentation === 'preferred';
+  let presentation;
+  try {
+    GPUAdapter.prototype.requestDevice = async function (descriptor = {}) {
+      if (!this.features.has('timestamp-query'))
+        throw new Error('timestamp-query is required for GPU breakdowns');
+      const device = await originals.requestDevice.call(this, {
+        ...descriptor,
+        requiredFeatures: [...new Set([...(descriptor.requiredFeatures ?? []), 'timestamp-query'])],
+      });
+      device.addEventListener('uncapturederror', (event) => errors.push(event.error.message));
+      state = {
+        device,
+        gpu: { vendor: this.info.vendor, architecture: this.info.architecture },
+        queries: device.createQuerySet({ type: 'timestamp', count: 6 }),
+        resolve: device.createBuffer({
+          size: 48,
+          usage: GPUBufferUsage.QUERY_RESOLVE | GPUBufferUsage.COPY_SRC,
+        }),
+        readback: device.createBuffer({
+          size: 48,
+          usage: GPUBufferUsage.COPY_DST | GPUBufferUsage.MAP_READ,
+        }),
+        passes: 0,
+      };
+      resources.push(state);
+      return device;
+    };
+    GPUDevice.prototype.createCommandEncoder = function (descriptor) {
+      const encoder = originals.createEncoder.call(this, descriptor);
+      if (!encoding) return encoder;
+      const current = state;
+      const begin = encoder.beginComputePass.bind(encoder);
+      const finish = encoder.finish.bind(encoder);
+      encoder.beginComputePass = (descriptor = {}) => {
+        const slot = current.passes++;
+        if (slot >= 3)
+          throw new Error('Unexpected compute pass layout; update profiler phase labels');
+        return begin({
+          ...descriptor,
+          timestampWrites: {
+            querySet: current.queries,
+            beginningOfPassWriteIndex: slot * 2,
+            endOfPassWriteIndex: slot * 2 + 1,
+          },
+        });
+      };
+      encoder.finish = (descriptor) => {
+        if (current.passes !== 3)
+          throw new Error('Expected preprocess / model / postprocess compute passes');
+        encoder.resolveQuerySet(current.queries, 0, 6, current.resolve, 0);
+        encoder.copyBufferToBuffer(current.resolve, 0, current.readback, 0, 48);
+        return finish(descriptor);
+      };
+      return encoder;
+    };
+    if (preferred) {
+      GPUCanvasContext.prototype.configure = function (descriptor) {
+        return originals.configure.call(this, {
+          ...descriptor,
+          format: navigator.gpu.getPreferredCanvasFormat(),
+          usage: GPUTextureUsage.RENDER_ATTACHMENT,
+        });
+      };
+      GPUDevice.prototype.createTexture = function (descriptor) {
+        const usage =
+          descriptor.usage & GPUTextureUsage.STORAGE_BINDING
+            ? descriptor.usage | GPUTextureUsage.TEXTURE_BINDING
+            : descriptor.usage;
+        return originals.createTexture.call(this, { ...descriptor, usage });
+      };
+      GPUCommandEncoder.prototype.copyTextureToTexture = function (source, destination, size) {
+        // Only the example's final result-to-canvas copy is replaced.
+        if (!(source.texture.usage & GPUTextureUsage.STORAGE_BINDING)) {
+          return originals.copyTexture.call(this, source, destination, size);
+        }
+        if (!presentation) {
+          const device = state.device;
+          const module = device.createShaderModule({
+            code: `
+            @group(0) @binding(0) var image: texture_2d<f32>;
+            @vertex fn vertex(@builtin(vertex_index) i: u32) -> @builtin(position) vec4<f32> {
+              let positions = array<vec2<f32>, 3>(vec2(-1., -1.), vec2(3., -1.), vec2(-1., 3.));
+              return vec4(positions[i], 0., 1.);
+            }
+            @fragment fn fragment(@builtin(position) p: vec4<f32>) -> @location(0) vec4<f32> {
+              return textureLoad(image, vec2<i32>(p.xy), 0);
+            }`,
+          });
+          const pipeline = device.createRenderPipeline({
+            layout: 'auto',
+            vertex: { module, entryPoint: 'vertex' },
+            fragment: {
+              module,
+              entryPoint: 'fragment',
+              targets: [{ format: destination.texture.format }],
+            },
+          });
+          const bindGroup = device.createBindGroup({
+            layout: pipeline.getBindGroupLayout(0),
+            entries: [{ binding: 0, resource: source.texture.createView() }],
+          });
+          presentation = { pipeline, bindGroup };
+        }
+        const pass = this.beginRenderPass({
+          colorAttachments: [
+            { view: destination.texture.createView(), loadOp: 'clear', storeOp: 'store' },
+          ],
+        });
+        pass.setPipeline(presentation.pipeline);
+        pass.setBindGroup(0, presentation.bindGroup);
+        pass.draw(3);
+        pass.end();
+      };
+    }
+    OffscreenCanvasRenderingContext2D.prototype.drawImage = function (...args) {
+      if (!(args[0] instanceof HTMLVideoElement)) return originals.drawImage.apply(this, args);
+      const start = performance.now();
+      frame = { startMs: start };
+      const result = originals.drawImage.apply(this, args);
+      frame.cropCpuMs = performance.now() - start;
+      frames.push(frame);
+      return result;
+    };
+    GPUQueue.prototype.copyExternalImageToTexture = function (...args) {
+      const start = performance.now();
+      const result = originals.upload.apply(this, args);
+      if (frame) frame.uploadCallCpuMs = performance.now() - start;
+      return result;
+    };
+    WgpuExecutionContext.prototype.submit = function () {
+      const currentFrame = frame;
+      const current = state;
+      const start = performance.now();
+      current.passes = 0;
+      encoding = true;
+      try {
+        originals.submit.call(this);
+      } finally {
+        encoding = false;
+      }
+      currentFrame.encodeCpuMs = performance.now() - start;
+      const read = current.readback.mapAsync(GPUMapMode.READ).then(() => {
+        const t = [...new BigUint64Array(current.readback.getMappedRange())];
+        current.readback.unmap();
+        currentFrame.preprocessGpuMs = Number(t[1] - t[0]) / 1e6;
+        currentFrame.modelGpuMs = Number(t[3] - t[2]) / 1e6;
+        currentFrame.postprocessGpuMs = Number(t[5] - t[4]) / 1e6;
+        currentFrame.modelCopyAndPassGapGpuMs = Number(t[2] - t[1] + (t[4] - t[3])) / 1e6;
+        currentFrame.computeSpanGpuMs = Number(t[5] - t[0]) / 1e6;
+      });
+      pending.push(read);
+    };
+    GPUBuffer.prototype.mapAsync = function (...args) {
+      const currentFrame = frame;
+      const start = performance.now();
+      const result = originals.map.apply(this, args);
+      if (this.size !== 16 || !currentFrame) return result;
+      currentFrame.cpuBeforeFenceMs = start - currentFrame.startMs;
+      return result.then((value) => {
+        currentFrame.frameMs = performance.now() - currentFrame.startMs;
+        currentFrame.fenceWaitWallMs = performance.now() - start;
+        return value;
+      });
+    };
+    if (options.detections !== undefined) {
+      WgpuExecutionContext.prototype.recordShader = function (shader, args) {
+        if (shader.name === 'yolo.draw_detections') {
+          originals.recordShader.call(
+            this,
+            {
+              name: 'profile.force_detections',
+              code: '',
+              recordIn(ctx) {
+                const module = ctx.device.createShaderModule({
+                  code: `
+              @group(0) @binding(0) var<storage, read_write> counter: array<u32>;
+              @group(0) @binding(1) var<storage, read_write> dets: array<f32>;
+              @compute @workgroup_size(64) fn main(@builtin(local_invocation_id) tid: vec3<u32>) {
+                if (tid.x == 0u) { counter[0] = ${options.detections}u; }
+                if (tid.x >= ${options.detections}u) { return; }
+                let i = tid.x; let b = i * 6u;
+                dets[b] = f32(16u + (i % 8u) * 64u); dets[b+1u] = f32(16u + (i / 8u) * 64u);
+                dets[b+2u] = dets[b] + 100.; dets[b+3u] = dets[b+1u] + 120.;
+                dets[b+4u] = .9; dets[b+5u] = f32(i);
+              }`,
+                });
+                const pipeline = ctx.device.createComputePipeline({
+                  layout: 'auto',
+                  compute: { module, entryPoint: 'main' },
+                });
+                const bindGroup = ctx.device.createBindGroup({
+                  layout: pipeline.getBindGroupLayout(0),
+                  entries: [
+                    { binding: 0, resource: { buffer: args[2] } },
+                    { binding: 1, resource: { buffer: args[3] } },
+                  ],
+                });
+                ctx.addDispatch({ pipeline, bindGroup, workgroupCountX: 1, workgroupCountY: 1 });
+              },
+            },
+            []
+          );
+        }
+        return originals.recordShader.call(this, shader, args);
+      };
+    }
+    const source = document.createElement('canvas');
+    source.width = 1280;
+    source.height = 720;
+    const paint = source.getContext('2d');
+    let tick = 0;
+    timer = setInterval(() => {
+      paint.fillStyle = 'white';
+      paint.fillRect(0, 0, 1280, 720);
+      paint.fillStyle = 'black';
+      paint.beginPath();
+      paint.arc(640 + Math.sin(tick++ / 20) * 20, 360, 120, 0, Math.PI * 2);
+      paint.fill();
+    }, 33);
+    stream = source.captureStream(30);
+    const video = document.createElement('video');
+    video.muted = true;
+    video.autoplay = true;
+    video.playsInline = true;
+    video.srcObject = stream;
+    const canvas = document.createElement('canvas');
+    document.body.replaceChildren(video, canvas);
+    await video.play();
+    const { startFrameLoop } = await import(`/src/tasks/${options.task}/loop.ts`);
+    let finish;
+    const completed = new Promise((resolve) => {
+      finish = resolve;
+    });
+    const total = (options.warmups ?? 30) + (options.samples ?? 80);
+    let count = 0;
+    stop = await startFrameLoop(
+      video,
+      canvas,
+      () => {
+        if (++count >= total) finish();
+      },
+      options.precision
+    );
+    let timeout;
+    try {
+      await Promise.race([
+        completed,
+        new Promise((resolve, reject) => {
+          timeout = setTimeout(
+            () => reject(new Error(`Only ${count}/${total} frames completed`)),
+            30000
+          );
+        }),
+      ]);
+    } finally {
+      clearTimeout(timeout);
+    }
+    stop();
+    stop = null;
+    await Promise.all(pending);
+    if (errors.length) throw new Error(errors.join('\n'));
+    const measured = frames
+      .slice(options.warmups ?? 30)
+      .filter((item) => item.frameMs !== undefined && item.computeSpanGpuMs !== undefined);
+    for (const item of measured)
+      item.outsideComputeSpanWallMs = item.frameMs - item.computeSpanGpuMs;
+    const median = (values) => [...values].sort((a, b) => a - b)[values.length >> 1];
+    const keys = Object.keys(measured[0]).filter((key) => key !== 'startMs');
+    const configuration = { ...options };
+    delete configuration.repo;
+    delete configuration.reportEndpoint;
+    const result = {
+      ...configuration,
+      gpu: state.gpu,
+      browser: navigator.userAgent,
+      source: '1280x720 animated canvas captured as a 30fps HTMLVideoElement',
+      timing:
+        'GPU timestamps on the actual three compute passes; CPU clocks for crop/upload calls, encoding and frame-fence completion. One additional timestamp readback alongside the existing frame fence adds profiling overhead. Medians are not additive because CPU and GPU work can overlap.',
+      medians: Object.fromEntries(
+        keys.map((key) => [key, median(measured.map((item) => item[key]))])
+      ),
+      frames: measured,
+      note: 'outsideComputeSpanWallMs includes crop, upload/conversion, presentation, queue scheduling and browser callback latency; it is not all postprocessing work.',
+      errors,
+    };
+    if (options.reportEndpoint) {
+      const response = await fetch(options.reportEndpoint, {
+        method: 'POST',
+        headers: { 'Content-Type': 'application/json' },
+        body: JSON.stringify(result),
+      });
+      if (!response.ok) throw new Error(`Result upload failed: ${response.status}`);
+    }
+    return result;
+  } finally {
+    stop?.();
+    clearInterval(timer);
+    stream?.getTracks().forEach((track) => track.stop());
+    await Promise.allSettled(pending);
+    GPUAdapter.prototype.requestDevice = originals.requestDevice;
+    GPUDevice.prototype.createCommandEncoder = originals.createEncoder;
+    GPUDevice.prototype.createTexture = originals.createTexture;
+    GPUCanvasContext.prototype.configure = originals.configure;
+    GPUCommandEncoder.prototype.copyTextureToTexture = originals.copyTexture;
+    OffscreenCanvasRenderingContext2D.prototype.drawImage = originals.drawImage;
+    GPUQueue.prototype.copyExternalImageToTexture = originals.upload;
+    GPUBuffer.prototype.mapAsync = originals.map;
+    WgpuExecutionContext.prototype.submit = originals.submit;
+    WgpuExecutionContext.prototype.recordShader = originals.recordShader;
+    for (const resource of resources) {
+      resource.queries.destroy();
+      resource.resolve.destroy();
+      resource.readback.destroy();
+      resource.device.destroy();
+    }
+  }
+}
diff --git a/utils/benchmark/profile-live.mjs b/utils/benchmark/profile-live.mjs
new file mode 100644
index 0000000..86b2080
--- /dev/null
+++ b/utils/benchmark/profile-live.mjs
@@ -0,0 +1,300 @@
+// Usage: node utils/benchmark/profile-live.mjs [--controlled | --narrow | --hf | --runntime | --specialized] [--no-timestamps] [results.json]
+// Narrow comparison: WGPU_KERNEL_BASELINE=<commit> npm run benchmark:narrow
+// Starts its own local Vite server and dedicated headless Chrome profile. It
+// never attaches to, closes, or changes an existing browser process/profile.
+import { execFileSync, spawn } from 'node:child_process';
+import { access, mkdtemp, readFile, rm, writeFile } from 'node:fs/promises';
+import { tmpdir } from 'node:os';
+import { dirname, join, resolve } from 'node:path';
+import { fileURLToPath } from 'node:url';
+import { createServer } from 'vite';
+import { profileLivePipeline } from './profile-live.browser.mjs';
+import { profilePipelineStages } from './profile-stages.browser.mjs';
+import { profileNarrowConvolution } from './profile-narrow.browser.mjs';
+import { profileHuggingFace } from './profile-hf.browser.mjs';
+import { profileConvolutionSpecializations } from './profile-specialized.browser.mjs';
+import { profileRunntime } from './profile-runntime.browser.mjs';
+import { prepareRunntimeAssets } from './runntime/setup.mjs';
+
+const repo = resolve(dirname(fileURLToPath(import.meta.url)), '../..');
+const controlled = process.argv.includes('--controlled');
+const narrow = process.argv.includes('--narrow');
+const hf = process.argv.includes('--hf');
+const specialized = process.argv.includes('--specialized');
+const runntime = process.argv.includes('--runntime');
+let runntimeAssets;
+if (runntime) {
+  try {
+    await access(join(repo, 'utils/benchmark/runntime/node_modules/runntime/package.json'));
+  } catch {
+    throw new Error(
+      'Install isolated benchmark dependencies: npm ci --prefix utils/benchmark/runntime'
+    );
+  }
+  runntimeAssets = await prepareRunntimeAssets();
+}
+const baseline =
+  process.env.WGPU_KERNEL_BASELINE ??
+  execFileSync('git', ['rev-parse', 'HEAD'], { cwd: repo, encoding: 'utf8' }).trim();
+let baselineRepo;
+const timestamps = !process.argv.includes('--no-timestamps');
+if (!controlled && !timestamps) throw new Error('--no-timestamps requires --controlled');
+const outputPath = process.argv.slice(2).find((arg) => !arg.startsWith('--'));
+const output = resolve(
+  outputPath ??
+    join(
+      repo,
+      `utils/benchmark/${specialized ? 'specialized' : runntime ? 'runntime' : hf ? 'hf' : narrow ? 'narrow' : controlled ? 'stage' : 'pipeline'}-results.json`
+    )
+);
+const candidates = process.env.WGPU_CHROME
+  ? [process.env.WGPU_CHROME]
+  : process.platform === 'darwin'
+    ? ['/Applications/Google Chrome.app/Contents/MacOS/Google Chrome']
+    : process.platform === 'win32'
+      ? [
+          join(process.env.PROGRAMFILES ?? '', 'Google/Chrome/Application/chrome.exe'),
+          join(process.env.LOCALAPPDATA ?? '', 'Google/Chrome/Application/chrome.exe'),
+        ]
+      : ['/usr/bin/google-chrome', '/usr/bin/chromium', '/usr/bin/chromium-browser'];
+let executable;
+for (const candidate of candidates) {
+  try {
+    await access(candidate);
+    executable = candidate;
+    break;
+  } catch {}
+}
+if (!executable) throw new Error('Chrome not found; set WGPU_CHROME to its executable path');
+const profile = await mkdtemp(join(tmpdir(), 'wgpu-pipeline-chrome-'));
+let server;
+let browser;
+let ws;
+const report = {
+  baseline,
+  method: specialized
+    ? 'Shape-specialized convolution candidates vs archived production baseline; see per-case bitwise parity and timing.'
+    : runntime
+      ? 'Published ruNNtime 0.1.0 vs our unchanged graphs; paired pixels-to-CPU-results and separate GPU compute times. See per-case model equivalence and numerical validation.'
+      : hf
+        ? 'Pinned Hugging Face Conv adaptation against archived baseline; see per-run method and numerical validation.'
+        : narrow
+          ? 'Compare raw 16-row/32-row convolutions and unchanged full model graphs against archived source. See per-run timing details.'
+          : controlled
+            ? 'Single-page controlled stage ablation; shuffled paired rounds, same device and model inputs. When enabled, GPU timestamp readback occurs outside wall timer. Additional sustained ABBA blocks compare continuous submissions and video-paced presentation.'
+            : 'Instrument actual example loops with CPU clocks and GPU pass timestamps. Synthetic video; no camera permissions. Warmup frames excluded. Configurations run sequentially; model clock variation prevents interpreting total frame differences as presentation speedups.',
+  warning: specialized
+    ? 'Measurements cover one adapter/browser; shape-based routing avoids GPU identifiers but does not establish universal speedups. Model timings exclude preprocessing, postprocessing and rendering.'
+    : runntime
+      ? 'DepthART backbones differ (ours MNV4-S, ruNNtime TinyViM-S); DepthART is a workload comparison, not an isolated runtime benchmark. YOLO26-N uses the same task/variant and input size.'
+      : hf
+        ? 'Results are from one adapter/browser. Each variant is paired within a run; do not interpret between-run clock changes as kernel speedups. These adapters force selected templates and do not implement the full HF routing policy.'
+        : 'Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.',
+  results: [],
+};
+try {
+  if (narrow || hf || specialized) {
+    baselineRepo = await mkdtemp(join(tmpdir(), 'wgpu-narrow-baseline-'));
+    const archive = execFileSync('git', ['archive', baseline, 'src'], { cwd: repo });
+    execFileSync('tar', ['-x', '-C', baselineRepo], { input: archive });
+  }
+  server = await createServer({
+    root: join(repo, 'example'),
+    ...(runntime
+      ? {
+          optimizeDeps: {
+            entries: [join(repo, 'utils/benchmark/runntime/entry.mjs')],
+            include: [
+              join(
+                repo,
+                'utils/benchmark/runntime/node_modules/runntime/dist/wgpu-benchmark-internals.mjs'
+              ),
+            ],
+          },
+        }
+      : {}),
+    configFile: join(repo, 'example/vite.config.ts'),
+    server: {
+      host: '127.0.0.1',
+      port: 0,
+      strictPort: true,
+      fs: {
+        allow: [
+          repo,
+          ...(baselineRepo ? [baselineRepo] : []),
+          ...(runntimeAssets ? [runntimeAssets.directory] : []),
+        ],
+      },
+    },
+    plugins: [
+      {
+        name: 'live-profile-results',
+        configureServer(server) {
+          server.middlewares.use('/api/results', async (request, response) => {
+            if (request.method !== 'POST') {
+              response.writeHead(405).end();
+              return;
+            }
+            try {
+              let body = '';
+              for await (const chunk of request) body += chunk;
+              report.results.push(JSON.parse(body));
+              await writeFile(output, JSON.stringify(report, null, 2) + '\n');
+              response.writeHead(200).end('ok');
+            } catch (error) {
+              response.writeHead(500).end(String(error));
+            }
+          });
+        },
+      },
+    ],
+  });
+  await server.listen();
+  const url = server.resolvedUrls.local[0];
+  browser = spawn(
+    executable,
+    [
+      '--headless=new',
+      `--user-data-dir=${profile}`,
+      '--remote-debugging-port=0',
+      '--enable-unsafe-webgpu',
+      '--disable-background-networking',
+      '--no-first-run',
+      '--no-default-browser-check',
+      'about:blank',
+    ],
+    { stdio: ['ignore', 'ignore', 'pipe'] }
+  );
+  let browserErrors = '';
+  browser.stderr.on('data', (data) => {
+    browserErrors = (browserErrors + data).slice(-4000);
+  });
+  let port;
+  for (let attempt = 0; attempt < 400; attempt++) {
+    if (browser.exitCode !== null) throw new Error(`Owned Chrome exited: ${browserErrors}`);
+    try {
+      port = (await readFile(join(profile, 'DevToolsActivePort'), 'utf8')).split('\n')[0];
+      break;
+    } catch {}
+    await new Promise((resolve) => setTimeout(resolve, 50));
+  }
+  if (!port) throw new Error(`Chrome did not start: ${browserErrors}`);
+  const targets = await (await fetch(`http://127.0.0.1:${port}/json`)).json();
+  const page = targets.find((target) => target.type === 'page');
+  ws = new WebSocket(page.webSocketDebuggerUrl);
+  await new Promise((resolve, reject) => {
+    ws.addEventListener('open', resolve, { once: true });
+    ws.addEventListener('error', reject, { once: true });
+  });
+  let sequence = 0;
+  const pending = new Map();
+  ws.addEventListener('message', (event) => {
+    const response = JSON.parse(event.data);
+    if (response.id) {
+      pending.get(response.id)?.(response);
+      pending.delete(response.id);
+    }
+  });
+  const call = (method, params = {}) =>
+    new Promise((resolve, reject) => {
+      const id = ++sequence;
+      pending.set(id, (response) =>
+        response.error
+          ? reject(new Error(JSON.stringify(response.error)))
+          : resolve(response.result)
+      );
+      ws.send(JSON.stringify({ id, method, params }));
+    });
+  await call('Runtime.enable');
+  const configurations = [];
+  for (const task of narrow || hf || specialized
+    ? ['yolo26-detection']
+    : ['depth-estimation', 'yolo26-detection'])
+    for (const precision of runntime ? ['float16'] : ['float32', 'float16'])
+      configurations.push({ task, precision, presentation: 'current' });
+  if (!controlled && !narrow && !hf && !runntime && !specialized)
+    configurations.push({
+      task: 'yolo26-detection',
+      precision: 'float16',
+      presentation: 'current',
+      detections: 64,
+    });
+  if (!controlled && !narrow && !hf && !runntime && !specialized)
+    for (const task of ['depth-estimation', 'yolo26-detection'])
+      configurations.push({ task, precision: 'float16', presentation: 'preferred' });
+  for (const config of configurations) {
+    await call('Page.navigate', { url });
+    await new Promise((resolve) => setTimeout(resolve, 1000));
+    const options = {
+      fractionalInputs: process.env.WGPU_KERNEL_DATA === 'fractional',
+      runntimeAssets,
+      reportEndpoint: '/api/results',
+      baselineRepo: baselineRepo?.replaceAll('\\', '/'),
+      ...config,
+      repo: repo.replaceAll('\\', '/'),
+      warmups: specialized
+        ? 8
+        : runntime
+          ? Number(process.env.WGPU_BENCH_WARMUPS ?? 12)
+          : hf
+            ? 8
+            : controlled
+              ? 8
+              : 30,
+      samples: specialized
+        ? 51
+        : runntime
+          ? Number(process.env.WGPU_BENCH_SAMPLES ?? 61)
+          : hf
+            ? 51
+            : controlled
+              ? 61
+              : 80,
+      timestamps,
+    };
+    const response = await call('Runtime.evaluate', {
+      expression: `(${(specialized ? profileConvolutionSpecializations : runntime ? profileRunntime : hf ? profileHuggingFace : narrow ? profileNarrowConvolution : controlled ? profilePipelineStages : profileLivePipeline).toString()})(${JSON.stringify(options)})`,
+      awaitPromise: true,
+      returnByValue: true,
+    });
+    if (response.exceptionDetails)
+      throw new Error(
+        response.exceptionDetails.exception?.description ??
+          JSON.stringify(response.exceptionDetails)
+      );
+    const result = response.result.value;
+    console.log(
+      JSON.stringify({
+        results: runntime
+          ? result.results.map(
+              ({ name, wallMs, gpuComputeMs, runntimeOverOursWall, runntimeOverOursGpu }) => ({
+                name,
+                wallMs: wallMs.map((x) => x.median),
+                gpuComputeMs: gpuComputeMs.map((x) => x.median),
+                runntimeOverOursWall,
+                runntimeOverOursGpu,
+              })
+            )
+          : result.results?.map(({ samples, ...summary }) => summary),
+        task: result.task,
+        precision: result.precision,
+        presentation: result.presentation,
+        detections: result.detections,
+        medians: result.medians,
+        pairedDeltas: result.pairedDeltas,
+        sustained: result.sustained?.map(({ name, medians }) => ({ name, medians })),
+      })
+    );
+  }
+  console.log(`Saved ${output}`);
+} finally {
+  ws?.close();
+  if (browser && browser.exitCode === null) {
+    const exited = new Promise((resolve) => browser.once('exit', resolve));
+    browser.kill('SIGTERM'); // Only the process spawned above, with its unique profile.
+    await Promise.race([exited, new Promise((resolve) => setTimeout(resolve, 5000))]);
+  }
+  await server?.close();
+  if (baselineRepo) await rm(baselineRepo, { recursive: true, force: true });
+  await rm(profile, { recursive: true, force: true, maxRetries: 10, retryDelay: 100 });
+}
diff --git a/utils/benchmark/profile-narrow.browser.mjs b/utils/benchmark/profile-narrow.browser.mjs
new file mode 100644
index 0000000..d5e6ea1
--- /dev/null
+++ b/utils/benchmark/profile-narrow.browser.mjs
@@ -0,0 +1,160 @@
+// Compare the new narrow convolution with the existing 32-row tile, then
+// compare unchanged model graphs against a complete archived source baseline.
+export async function profileNarrowConvolution(options) {
+  const { WgpuExecutionContext, createComputeBundle } = await import(
+    '/@fs' + options.repo + '/src/index.ts'
+  );
+  const { WgpuExecutionContext: BaselineContext } = await import(
+    '/@fs' + options.baselineRepo + '/src/index.ts'
+  );
+  const { KernelTimingContext } = await import(
+    '/@fs' + options.repo + '/tests/helpers/kernel-timing.ts'
+  );
+  const adapter = await navigator.gpu.requestAdapter();
+  const half = options.precision === 'float16';
+  const device = await adapter.requestDevice({
+    requiredFeatures: ['timestamp-query', ...(half ? ['shader-f16'] : [])],
+  });
+  device.pushErrorScope('validation');
+  const suffix = half ? '-f16' : '';
+  const array = half ? Float16Array : Float32Array;
+  const fill = (length) =>
+    new array(Array.from({ length }, (_, i) => (((i * 17 + 11) % 61) - 30) / 64));
+  const code = [];
+  for (const height of [32, 16]) {
+    const module = await import(
+      `/@fs${height === 32 ? options.baselineRepo : options.repo}/src/shaders/convolution/conv2d-tile${height}${suffix}.wgsl.ts`
+    );
+    code.push(Object.values(module)[0]);
+  }
+  const results = [];
+  const median = (values) => [...values].sort((a, b) => a - b)[values.length >> 1];
+  async function compare(contexts, repeats, outputs, gpu) {
+    const samples = [[], []];
+    for (let i = -8; i < 51; i++)
+      for (const version of i & 1 ? [1, 0] : [0, 1]) {
+        const start = performance.now();
+        contexts[version].submit();
+        await contexts[version].sync();
+        if (i >= 0)
+          samples[version].push(
+            (gpu ? contexts[version].gpuMs : performance.now() - start) / repeats
+          );
+      }
+    const values = [];
+    for (let i = 0; i < 2; i++) {
+      contexts[i].submit();
+      await contexts[i].sync();
+      values.push(new array(await outputs[i].getData()));
+    }
+    let maxDelta = 0;
+    for (let i = 0; i < values[0].length; i++) {
+      if (!Number.isFinite(values[0][i]) || !Number.isFinite(values[1][i]))
+        throw new Error('Nonfinite output');
+      maxDelta = Math.max(maxDelta, Math.abs(values[0][i] - values[1][i]));
+    }
+    if (maxDelta !== 0) throw new Error(`Output mismatch: ${maxDelta}`);
+    const beforeMs = median(samples[0]),
+      afterMs = median(samples[1]);
+    return { beforeMs, afterMs, speedup: beforeMs / afterMs, maxDelta, repeats, samples };
+  }
+  try {
+    const shapes = [
+      [16, 8, 160, 1],
+      [8, 16, 160, 1],
+      [32, 16, 80, 1],
+      [64, 16, 80, 1],
+      [16, 16, 64, 1],
+      [16, 16, 80, 1],
+      [8, 16, 80, 1],
+      [16, 8, 80, 1],
+      [16, 16, 160, 2],
+      [32, 16, 40, 1],
+      [32, 16, 20, 1],
+      [4, 13, 17, 1],
+      [24, 16, 448, 1],
+    ];
+    for (const shape of shapes) {
+      const [ic, oc, h, stride] = shape;
+      const oh = Math.floor((h - 1) / stride) + 1;
+      const ctx = new WgpuExecutionContext(device);
+      const input = ctx.tensor(options.precision, [1, ic, h, h]).setData(fill(ic * h * h));
+      const weight = ctx.tensor(options.precision, [oc, ic, 3, 3]).setData(fill(oc * ic * 9));
+      const bias = ctx.tensor(options.precision, [oc]).setData(fill(oc));
+      const out = ctx.tensor(options.precision, [1, oc, oh, oh]);
+      const params = new Uint32Array(20);
+      params.set([1, ic, h, h, oc, oh, oh, 3, 3, stride, stride, 1, 1, 1, 1, 1, 1]);
+      const uniform = ctx.uniformBuffer(params);
+      const bindings = [out, input, weight, bias].map((tensor, binding) => ({
+        binding,
+        buffer: tensor.buffer,
+      }));
+      bindings.push({ binding: 4, buffer: uniform });
+      const repeats = Math.min(256, Math.max(8, Math.ceil(1e9 / (out.numel * ic * 9))));
+      const contexts = code.map((shader) => {
+        const timing = new KernelTimingContext(device);
+        const bundle = createComputeBundle(device, shader, bindings, { kernel_h: 3, kernel_w: 3 });
+        for (let i = 0; i < repeats; i++)
+          timing.addDispatch({
+            pipeline: bundle.pipeline,
+            bindGroup: bundle.bindGroup,
+            workgroupCountX: Math.ceil((oh * oh) / 64),
+            workgroupCountY: 1,
+          });
+        return timing;
+      });
+      results.push({
+        category: 'kernel',
+        shape,
+        selected: oh * oh >= 4096,
+        ...(await compare(contexts, repeats, [out, out], true)),
+      });
+      contexts.forEach((context) => context.destroy());
+      ctx.destroy();
+    }
+    for (const name of ['yolo26n', 'depthart']) {
+      const base = `/assets/${name}/`;
+      const responses = await Promise.all([
+        fetch(`${base}program${half ? '-fp16' : ''}.json`),
+        fetch(`${base}weights${half ? '-fp16' : ''}.bin`),
+      ]);
+      if (responses.some((response) => !response.ok))
+        throw new Error('Model artifacts unavailable');
+      const program = await responses[0].json(),
+        weights = await responses[1].arrayBuffer();
+      const outputs = [];
+      const contexts = [BaselineContext, WgpuExecutionContext].map((Context) => {
+        const ctx = new Context(device);
+        const input = ctx.tensor(options.precision, program.values[program.inputIds[0]].shape);
+        input.setData(
+          new array(Array.from({ length: input.numel }, (_, i) => (i % 251) / 250 - 0.5))
+        );
+        const output = ctx.tensor(options.precision, program.values[program.outputIds[0]].shape);
+        ctx.recordProgram(program, weights, [input, output]);
+        outputs.push(output);
+        return ctx;
+      });
+      results.push({ category: 'model', name, ...(await compare(contexts, 1, outputs, false)) });
+      contexts.forEach((ctx) => ctx.destroy());
+    }
+    const error = await device.popErrorScope();
+    if (error) throw error;
+    const result = {
+      precision: options.precision,
+      gpu: { vendor: adapter.info.vendor, architecture: adapter.info.architecture },
+      browser: navigator.userAgent,
+      method:
+        'Same-device alternating baseline/candidate measurements; 8 warmups, 51 samples. Kernels: recorded repeated dispatches, GPU timestamps per dispatch. Models: unchanged graphs and identical inputs, submit + sync wall clock. Model baseline is archived source; raw kernel comparison uses the unchanged 32-row tile. selected marks the conservative spatial threshold. All outputs must match bitwise.',
+      results,
+    };
+    const response = await fetch(options.reportEndpoint, {
+      method: 'POST',
+      headers: { 'Content-Type': 'application/json' },
+      body: JSON.stringify(result),
+    });
+    if (!response.ok) throw new Error(`Results upload failed: ${response.status}`);
+    return result;
+  } finally {
+    device.destroy();
+  }
+}
diff --git a/utils/benchmark/profile-runntime.browser.mjs b/utils/benchmark/profile-runntime.browser.mjs
new file mode 100644
index 0000000..35a45ce
--- /dev/null
+++ b/utils/benchmark/profile-runntime.browser.mjs
@@ -0,0 +1,436 @@
+// Compare unmodified published ruNNtime APIs with this runtime on one device.
+export async function profileRunntime(options) {
+  const { WgpuExecutionContext } = await import('/@fs' + options.repo + '/src/index.ts');
+  const {
+    tgpu,
+    initRunntime,
+    createObjectDetector,
+    createDepthEstimator,
+    imageBuffer,
+    models,
+    kernelInternals,
+  } = await import('/@fs' + options.repo + '/utils/benchmark/runntime/entry.mjs');
+  const depth = options.task === 'depth-estimation';
+  const extent = depth ? 448 : 640;
+  const modelName = depth ? 'depthart' : 'yolo26n';
+  const modelAsset = options.runntimeAssets.provenance.find(
+    (p) => p.model === (depth ? 'depthart' : 'yolo26')
+  );
+  const adapter = await navigator.gpu.requestAdapter();
+  const device = await adapter.requestDevice({
+    requiredFeatures: [
+      'shader-f16',
+      'timestamp-query',
+      ...(adapter.features.has('subgroups') ? ['subgroups'] : []),
+    ],
+  });
+  const errors = [];
+  device.addEventListener('uncapturederror', (event) => errors.push(event.error.message));
+  const root = tgpu.initFromDevice({ device });
+  initRunntime(root);
+  let runner;
+  const owned = [];
+  const originalEncoder = device.createCommandEncoder.bind(device);
+  let instrument = false,
+    queryCount = 0;
+  const queries = device.createQuerySet({ type: 'timestamp', count: 128 });
+  const queryResolve = device.createBuffer({
+    size: 128 * 8,
+    usage: GPUBufferUsage.QUERY_RESOLVE | GPUBufferUsage.COPY_SRC,
+  });
+  const queryRead = device.createBuffer({
+    size: 128 * 8,
+    usage: GPUBufferUsage.MAP_READ | GPUBufferUsage.COPY_DST,
+  });
+  device.createCommandEncoder = function (descriptor) {
+    const encoder = originalEncoder(descriptor);
+    if (!instrument) return encoder;
+    const begin = encoder.beginComputePass.bind(encoder);
+    encoder.beginComputePass = (descriptor = {}) => {
+      const first = queryCount;
+      queryCount += 2;
+      if (queryCount > 128) throw new Error('Too many compute passes for GPU timing');
+      return begin({
+        ...descriptor,
+        timestampWrites: {
+          querySet: queries,
+          beginningOfPassWriteIndex: first,
+          endOfPassWriteIndex: first + 1,
+        },
+      });
+    };
+    return encoder;
+  };
+  const median = (a) => [...a].sort((x, y) => x - y)[a.length >> 1];
+  const summarize = (a) => ({
+    median: median(a),
+    p10: [...a].sort((x, y) => x - y)[Math.floor(a.length * 0.1)],
+    p90: [...a].sort((x, y) => x - y)[Math.floor(a.length * 0.9)],
+    samples: a,
+  });
+  try {
+    const loadStart = performance.now();
+    const config = {
+      ...(depth ? models.depthEstimation.DEPTHART.S : models.objectDetection.YOLO26.N),
+      modelPath: '/@fs' + modelAsset.path,
+      resizeMode: 'crop',
+    };
+    runner = depth ? await createDepthEstimator(config) : await createObjectDetector(config);
+    const runntimeLoadMs = performance.now() - loadStart;
+    const shaders = await import(`/src/tasks/${options.task}/shaders.ts`);
+    const resources = await Promise.all(
+      ['program-fp16.json', 'weights-fp16.bin', 'program.json', 'weights.bin'].map((name) =>
+        fetch(`/assets/${modelName}/${name}`)
+      )
+    );
+    if (resources.some((r) => !r.ok)) throw new Error('Missing local model artifacts');
+    const [program, weights, program32, weights32] = await Promise.all([
+      resources[0].json(),
+      resources[1].arrayBuffer(),
+      resources[2].json(),
+      resources[3].arrayBuffer(),
+    ]);
+    const oursLoadStart = performance.now();
+    const context = new WgpuExecutionContext(device);
+    const oracle = new WgpuExecutionContext(device);
+    owned.push(context, oracle);
+    const input = context.tensor('float16', [1, 3, extent, extent]);
+    const output = context.tensor('float16', depth ? [1, 1, extent, extent] : [1, 84, 8400]);
+    const x32 = oracle.tensor('float32', input.shape),
+      y32 = oracle.tensor('float32', output.shape);
+    const texture = device.createTexture({
+      size: [extent, extent],
+      format: 'rgba8unorm',
+      usage:
+        GPUTextureUsage.COPY_DST |
+        GPUTextureUsage.TEXTURE_BINDING |
+        GPUTextureUsage.RENDER_ATTACHMENT,
+    });
+    context
+      .recordShader(shaders.preprocessF16, [texture, input])
+      .recordProgram(program, weights, [input, output]);
+    oracle
+      .recordShader(shaders.preprocess, [texture, x32])
+      .recordProgram(program32, weights32, [x32, y32]);
+    const oursRecordMs = performance.now() - oursLoadStart;
+    const crop = new OffscreenCanvas(extent, extent),
+      cropContext = crop.getContext('2d');
+    const sourceCanvas = new OffscreenCanvas(1280, 720),
+      sourceContext = sourceCanvas.getContext('2d');
+    const photograph = await createImageBitmap(
+      await (await fetch('/@fs' + options.runntimeAssets.image.path)).blob()
+    );
+    function makeImage(width, height, gradient = false) {
+      const canvas = new OffscreenCanvas(width, height),
+        ctx = canvas.getContext('2d');
+      if (gradient) {
+        const image = ctx.createImageData(width, height);
+        for (let i = 0; i < width * height; i++) {
+          image.data[4 * i] = ((i % width) * 255) / width;
+          image.data[4 * i + 1] = (Math.floor(i / width) * 255) / height;
+          image.data[4 * i + 2] = (i % 47) * 5;
+          image.data[4 * i + 3] = 255;
+        }
+        ctx.putImageData(image, 0, 0);
+      } else ctx.drawImage(photograph, 0, 0, width, height);
+      const imageData = ctx.getImageData(0, 0, width, height);
+      return {
+        imageData,
+        buffer: imageBuffer(imageData.data, width, height, 'rgba'),
+        width,
+        height,
+      };
+    }
+    const images = [
+      { name: 'photograph-native', ...makeImage(extent, extent) },
+      { name: 'photograph-1280x720-crop', ...makeImage(1280, 720) },
+      { name: 'gradient-native', ...makeImage(extent, extent, true) },
+    ];
+    photograph.close();
+    function upload(image) {
+      if (image.width === extent && image.height === extent) {
+        device.queue.writeTexture({ texture }, image.imageData.data, { bytesPerRow: extent * 4 }, [
+          extent,
+          extent,
+        ]);
+      } else {
+        sourceContext.putImageData(image.imageData, 0, 0);
+        const side = Math.min(image.width, image.height);
+        cropContext.drawImage(
+          sourceCanvas,
+          (image.width - side) / 2,
+          (image.height - side) / 2,
+          side,
+          side,
+          0,
+          0,
+          extent,
+          extent
+        );
+        device.queue.copyExternalImageToTexture({ source: crop }, { texture }, [extent, extent]);
+      }
+    }
+    function decode(predictions, image) {
+      const count = 8400,
+        hits = [],
+        scale = Math.min(image.width, image.height) / extent;
+      const offsetX = (image.width - Math.min(image.width, image.height)) / 2;
+      const offsetY = (image.height - Math.min(image.width, image.height)) / 2;
+      for (let i = 0; i < count; i++) {
+        let confidence = -Infinity,
+          classId = 0;
+        for (let c = 0; c < 80; c++) {
+          const score = predictions[(4 + c) * count + i];
+          if (score > confidence) {
+            confidence = score;
+            classId = c;
+          }
+        }
+        if (confidence < 0.35) continue;
+        const box = {
+          format: 'xyxy',
+          xmin: Math.max(0, Math.min(image.width, predictions[i] * scale + offsetX)),
+          ymin: Math.max(0, Math.min(image.height, predictions[count + i] * scale + offsetY)),
+          xmax: Math.max(0, Math.min(image.width, predictions[2 * count + i] * scale + offsetX)),
+          ymax: Math.max(0, Math.min(image.height, predictions[3 * count + i] * scale + offsetY)),
+        };
+        hits.push({ classId, label: runner.labels[classId], confidence, box });
+      }
+      return hits.sort((a, b) => b.confidence - a.confidence).slice(0, 64);
+    }
+    const inferenceOptions = { confidenceThreshold: 0.35, maxDetections: 64 };
+    const execute = [
+      async (image) => {
+        upload(image);
+        context.submit();
+        const values = new Float16Array(await output.getData());
+        return depth
+          ? { width: extent, height: extent, data: new Float32Array(values) }
+          : decode(values, image);
+      },
+      async (image) =>
+        depth
+          ? runner.estimateDepth(image.buffer)
+          : runner.detectObjects(image.buffer, inferenceOptions),
+    ];
+    const cases = [];
+    for (const image of images) {
+      const samples = [[], []],
+        outputs = [];
+      for (let i = -options.warmups; i < options.samples; i++) {
+        for (const engine of i & 1 ? [1, 0] : [0, 1]) {
+          const start = performance.now();
+          outputs[engine] = await execute[engine](image);
+          if (i >= 0) samples[engine].push(performance.now() - start);
+        }
+      }
+      const gpuSamples = [[], []],
+        diagnosticWall = [[], []],
+        residuals = [[], []],
+        passCounts = [[], []];
+      // Instrument in a separate phase, leaving the primary wall clock untouched.
+      for (let i = 0; i < 15; i++)
+        for (const engine of i & 1 ? [1, 0] : [0, 1]) {
+          queryCount = 0;
+          instrument = true;
+          const phaseStart = performance.now();
+          await execute[engine](image);
+          const phaseMs = performance.now() - phaseStart;
+          instrument = false;
+          const encoder = originalEncoder();
+          encoder.resolveQuerySet(queries, 0, queryCount, queryResolve, 0);
+          encoder.copyBufferToBuffer(queryResolve, 0, queryRead, 0, queryCount * 8);
+          device.queue.submit([encoder.finish()]);
+          await queryRead.mapAsync(GPUMapMode.READ);
+          const times = new BigUint64Array(queryRead.getMappedRange());
+          let total = 0;
+          for (let q = 0; q < queryCount; q += 2) total += Number(times[q + 1] - times[q]) / 1e6;
+          queryRead.unmap();
+          gpuSamples[engine].push(total);
+          diagnosticWall[engine].push(phaseMs);
+          residuals[engine].push(phaseMs - total);
+          passCounts[engine].push(queryCount / 2);
+        }
+      upload(image);
+      oracle.submit();
+      const referenceRaw = new Float32Array(await y32.getData());
+      const reference = depth
+        ? { width: extent, height: extent, data: referenceRaw }
+        : decode(referenceRaw, image);
+      function iou(a, b) {
+        const overlap =
+          Math.max(0, Math.min(a.xmax, b.xmax) - Math.max(a.xmin, b.xmin)) *
+          Math.max(0, Math.min(a.ymax, b.ymax) - Math.max(a.ymin, b.ymin));
+        return (
+          overlap /
+          Math.max(
+            1e-9,
+            (a.xmax - a.xmin) * (a.ymax - a.ymin) + (b.xmax - b.xmin) * (b.ymax - b.ymin) - overlap
+          )
+        );
+      }
+      function validate(result, engine) {
+        if (depth) {
+          if (result.data.length !== extent * extent) throw new Error('Invalid depth shape');
+          let min = Infinity,
+            max = -Infinity,
+            sum = 0,
+            sumSq = 0,
+            sumRef = 0,
+            sumRefSq = 0,
+            cross = 0,
+            abs = 0;
+          for (let i = 0; i < result.data.length; i++) {
+            const x = result.data[i],
+              y = reference.data[i];
+            if (!Number.isFinite(x)) throw new Error('Nonfinite depth result');
+            min = Math.min(min, x);
+            max = Math.max(max, x);
+            sum += x;
+            sumSq += x * x;
+            sumRef += y;
+            sumRefSq += y * y;
+            cross += x * y;
+            abs += Math.abs(x - y);
+          }
+          const n = result.data.length;
+          return {
+            min,
+            max,
+            mean: sum / n,
+            meanAbsoluteDifferenceToOursF32: engine === 0 ? abs / n : undefined,
+            correlationToOursF32:
+              (cross - (sum * sumRef) / n) /
+              Math.sqrt((sumSq - (sum * sum) / n) * (sumRefSq - (sumRef * sumRef) / n)),
+          };
+        }
+        for (const d of result)
+          if (
+            ![d.confidence, ...Object.values(d.box).filter((v) => typeof v === 'number')].every(
+              Number.isFinite
+            )
+          )
+            throw new Error('Nonfinite detection');
+        const used = new Set();
+        const matches = reference.map((r) => {
+          let best = -1,
+            overlap = 0;
+          for (let j = 0; j < result.length; j++)
+            if (
+              !used.has(j) &&
+              r.classId === result[j].classId &&
+              iou(r.box, result[j].box) > overlap
+            ) {
+              best = j;
+              overlap = iou(r.box, result[j].box);
+            }
+          if (best >= 0 && overlap >= 0.8) used.add(best);
+          return {
+            classId: r.classId,
+            confidence: r.confidence,
+            bestIoU: overlap,
+            confidenceDifference:
+              best >= 0 ? Math.abs(r.confidence - result[best].confidence) : null,
+          };
+        });
+        const passesReferenceCheck =
+          used.size === reference.length &&
+          result.length === used.size &&
+          matches.every((m) => m.confidenceDifference <= 0.05);
+        if (!passesReferenceCheck)
+          throw new Error('YOLO outputs failed detection agreement with local FP32 reference');
+        return {
+          passesReferenceCheck,
+          detections: result,
+          referenceDetections: reference.length,
+          matchedAtIoU08: used.size,
+          matches,
+          unmatchedResults: result.length - used.size,
+        };
+      }
+      const wall = samples.map(summarize),
+        gpu = gpuSamples.map(summarize);
+      cases.push({
+        name: image.name,
+        width: image.width,
+        height: image.height,
+        engines: ['wgpu-executorch-fp16', 'runntime-0.1.0'],
+        wallMs: wall,
+        gpuComputeMs: gpu,
+        computePassCounts: passCounts,
+        diagnosticWallMs: diagnosticWall.map(summarize),
+        nonComputeResidualMs: residuals.map(summarize),
+        runntimeOverOursWall: wall[1].median / wall[0].median,
+        runntimeOverOursGpu: gpu[1].median / gpu[0].median,
+        validation: outputs.map(validate),
+        modelEquivalence: depth
+          ? 'Different backbones: ours MNV4-S, ruNNtime TinyViM-S. Workload comparison only, not a runtime speedup claim.'
+          : 'Both YOLO26-N one-to-one head; same input size and detection options. ruNNtime decodes raw distances/logits on CPU; our export decodes boxes/scores on GPU.',
+      });
+    }
+    let nativeKernels;
+    if (!depth) {
+      const { compareRunntimeKernels } = await import(
+        '/@fs' + options.repo + '/utils/benchmark/runntime/kernels.browser.mjs'
+      );
+      nativeKernels = await compareRunntimeKernels({
+        repo: options.repo,
+        device,
+        root,
+        lib: kernelInternals,
+        gpuTime: async (submit) => {
+          queryCount = 0;
+          instrument = true;
+          submit();
+          instrument = false;
+          const encoder = originalEncoder();
+          encoder.resolveQuerySet(queries, 0, queryCount, queryResolve, 0);
+          encoder.copyBufferToBuffer(queryResolve, 0, queryRead, 0, queryCount * 8);
+          device.queue.submit([encoder.finish()]);
+          await queryRead.mapAsync(GPUMapMode.READ);
+          const times = new BigUint64Array(queryRead.getMappedRange());
+          let total = 0;
+          for (let q = 0; q < queryCount; q += 2) total += Number(times[q + 1] - times[q]) / 1e6;
+          queryRead.unmap();
+          return total;
+        },
+      });
+    }
+    if (errors.length) throw new Error(errors.join('\n'));
+    const result = {
+      nativeKernels,
+      task: options.task,
+      precision: 'float16',
+      gpu: { vendor: adapter.info.vendor, architecture: adapter.info.architecture },
+      browser: navigator.userAgent,
+      features: [...device.features],
+      runntimeLoadMs,
+      oursRecordMs,
+      packages: { runntime: '0.1.0', typegpu: '0.12.8' },
+      assets: options.runntimeAssets,
+      method:
+        'One adapter/device; published ruNNtime APIs unmodified. Alternating wall-clock measurements: RGBA CPU bytes in -> CPU boxes/depth out, includes preprocessing/upload/inference/readback/CPU decode, excludes downloads/compilation/image decode/camera acquisition/rendering. Ours uses existing GPU preprocess shaders and model graphs; CPU crop for non-native sizes. Separate GPU timestamp phase measures summed compute pass durations; excludes CPU and copies, includes model/input conversion kernels. No extra timestamps in primary wall-clock samples. Both paths cache their command lists before measurement. DepthART backbones differ.',
+      warmups: options.warmups,
+      samples: options.samples,
+      results: cases,
+    };
+    const response = await fetch(options.reportEndpoint, {
+      method: 'POST',
+      headers: { 'Content-Type': 'application/json' },
+      body: JSON.stringify(result),
+    });
+    if (!response.ok) throw new Error('Failed to save results');
+    texture.destroy();
+    return result;
+  } finally {
+    instrument = false;
+    device.createCommandEncoder = originalEncoder;
+    runner?.dispose();
+    owned.forEach((c) => c.destroy());
+    queries.destroy();
+    queryResolve.destroy();
+    queryRead.destroy();
+    root.destroy();
+    device.destroy();
+  }
+}
diff --git a/utils/benchmark/profile-specialized.browser.mjs b/utils/benchmark/profile-specialized.browser.mjs
new file mode 100644
index 0000000..6dee821
--- /dev/null
+++ b/utils/benchmark/profile-specialized.browser.mjs
@@ -0,0 +1,206 @@
+// Same-device regression mesh and unchanged full graphs against archived kernels.
+export async function profileConvolutionSpecializations(options) {
+  const { WgpuExecutionContext, shaders } = await import('/@fs' + options.repo + '/src/index.ts');
+  const { WgpuExecutionContext: BaselineContext, shaders: baselineShaders } = await import(
+    '/@fs' + options.baselineRepo + '/src/index.ts'
+  );
+  const { KernelTimingContext } = await import(
+    '/@fs' + options.repo + '/tests/helpers/kernel-timing.ts'
+  );
+  const adapter = await navigator.gpu.requestAdapter();
+  const half = options.precision === 'float16';
+  const device = await adapter.requestDevice({
+    requiredFeatures: ['timestamp-query', ...(half ? ['shader-f16'] : [])],
+  });
+  const errors = [];
+  device.addEventListener('uncapturederror', (e) => errors.push(e.error.message));
+  const array = half ? Float16Array : Float32Array;
+  const fill = (n) =>
+    new array(
+      Array.from({ length: n }, (_, i) =>
+        options.fractionalInputs
+          ? ((Math.imul(i, 1664525) + 1013904223) >>> 0) / 4294967296 - 0.5
+          : (((i * 17 + 11) % 61) - 30) / 64
+      )
+    );
+  const median = (a) => [...a].sort((x, y) => x - y)[a.length >> 1];
+  async function compare(contexts, outputs, repeats, gpu) {
+    const samples = contexts.map(() => []);
+    for (let i = -8; i < 51; i++)
+      for (const version of i & 1 ? [1, 0] : [0, 1]) {
+        const start = performance.now();
+        contexts[version].submit();
+        await contexts[version].sync();
+        if (i >= 0)
+          samples[version].push(
+            (gpu ? contexts[version].gpuMs : performance.now() - start) / repeats
+          );
+      }
+    const bytes = [];
+    const values = [];
+    for (let version = 0; version < 2; version++) {
+      outputs[version].setData(new array(outputs[version].numel).fill(NaN));
+      contexts[version].submit();
+      await contexts[version].sync();
+      const buffer = await outputs[version].getData();
+      bytes.push(new Uint8Array(buffer));
+      values.push(new array(buffer));
+    }
+    const differences = [];
+    let maxAbs = 0,
+      changed = 0;
+    for (let i = 0; i < values[0].length; i++) {
+      if (!Number.isFinite(values[0][i]) || !Number.isFinite(values[1][i]))
+        throw new Error('Nonfinite or missing convolution output');
+      const delta = Math.abs(values[0][i] - values[1][i]);
+      maxAbs = Math.max(maxAbs, delta);
+      if (delta) {
+        changed++;
+        if (differences.length < 6) differences.push([i, values[0][i], values[1][i]]);
+      }
+    }
+    const differentBytes = bytes[0].reduce((n, v, i) => n + Number(v !== bytes[1][i]), 0);
+    const medians = samples.map(median);
+    return {
+      beforeMs: medians[0],
+      afterMs: medians[1],
+      speedup: medians[0] / medians[1],
+      maxAbs,
+      differentBytes,
+      differences,
+      changed,
+      repeats,
+      samples,
+    };
+  }
+  const results = [];
+  try {
+    // [IC, OC, IH, IW, stride, dilation, batch]; 3x3 same-padding.
+    const cases = [
+      [3, 16, 640, 640, 2, 1, 1],
+      [3, 8, 640, 640, 2, 1, 1],
+      [3, 12, 448, 448, 2, 1, 1],
+      [3, 16, 320, 320, 2, 1, 1],
+      [3, 16, 128, 128, 2, 1, 1],
+      [3, 13, 137, 145, 2, 1, 1],
+      [3, 16, 64, 64, 2, 1, 1],
+      [3, 20, 640, 640, 2, 1, 1],
+      [3, 32, 448, 448, 2, 1, 1],
+      [3, 16, 128, 128, 1, 1, 1],
+      [16, 8, 160, 160, 1, 1, 1],
+      [8, 8, 80, 80, 1, 1, 1],
+      [32, 8, 80, 80, 1, 1, 1],
+      [64, 8, 80, 80, 1, 1, 1],
+      [128, 8, 80, 80, 1, 1, 1],
+      [256, 8, 80, 80, 1, 1, 1],
+      [16, 4, 80, 80, 1, 1, 1],
+      [16, 7, 80, 80, 1, 1, 1],
+      [16, 9, 80, 80, 1, 1, 1],
+      [16, 8, 40, 40, 1, 1, 1],
+      [16, 8, 160, 160, 2, 1, 1],
+      [16, 8, 80, 80, 1, 2, 1],
+      [4, 8, 65, 67, 1, 1, 2],
+      [16, 8, 80, 80, 3, 1, 6],
+      [8, 8, 80, 80, 1, 3, 1],
+      [16, 16, 80, 80, 1, 1, 1],
+      [24, 16, 448, 448, 1, 1, 1],
+    ];
+    for (const shape of cases) {
+      const [ic, oc, ih, iw, stride, dilation, batch] = shape,
+        pad = dilation;
+      const oh = Math.floor((ih - 1) / stride) + 1,
+        ow = Math.floor((iw - 1) / stride) + 1;
+      const owner = new WgpuExecutionContext(device);
+      const x = owner
+        .tensor(options.precision, [batch, ic, ih, iw])
+        .setData(fill(batch * ic * ih * iw));
+      const w = owner.tensor(options.precision, [oc, ic, 3, 3]).setData(fill(oc * ic * 9));
+      const bias = owner.tensor(options.precision, [oc]).setData(fill(oc));
+      const sharedOutput = owner.tensor(options.precision, [batch, oc, oh, ow]);
+      const outputs = [sharedOutput, sharedOutput];
+      const repeats = Math.min(128, Math.max(4, Math.ceil(2e8 / (outputs[0].numel * ic * 9))));
+      class RepeatedContext extends KernelTimingContext {
+        addDispatch(d) {
+          for (let i = 0; i < repeats; i++) super.addDispatch(d);
+        }
+      }
+      const contexts = [new RepeatedContext(device), new RepeatedContext(device)];
+      device.pushErrorScope('validation');
+      for (let version = 0; version < 2; version++)
+        contexts[version].recordShader((version ? shaders : baselineShaders).convolution, [
+          x,
+          w,
+          bias,
+          [stride, stride],
+          [pad, pad],
+          [dilation, dilation],
+          false,
+          [0, 0],
+          1,
+          outputs[version],
+        ]);
+      const error = await device.popErrorScope();
+      if (error) throw new Error(error.message);
+      const timing = await compare(contexts, outputs, repeats, true);
+      if (timing.differentBytes !== 0)
+        throw new Error(
+          `Raw convolution changed ${shape}: ${JSON.stringify({ max: timing.maxAbs, examples: timing.differences, precision: options.precision })}`
+        );
+      results.push({ category: 'kernel', shape, ...timing });
+      contexts.forEach((c) => c.destroy());
+      owner.destroy();
+    }
+    for (const name of ['yolo26n', 'depthart']) {
+      const suffix = half ? '-fp16' : '';
+      const responses = await Promise.all([
+        fetch(`/assets/${name}/program${suffix}.json`),
+        fetch(`/assets/${name}/weights${suffix}.bin`),
+      ]);
+      if (responses.some((r) => !r.ok)) throw new Error('Missing model artifacts');
+      const program = await responses[0].json(),
+        weights = await responses[1].arrayBuffer(),
+        outputs = [];
+      const contexts = [BaselineContext, WgpuExecutionContext].map((Context) => {
+        const ctx = new Context(device);
+        const x = ctx
+          .tensor(options.precision, program.values[program.inputIds[0]].shape)
+          .setData(
+            new array(
+              Array.from(
+                { length: program.values[program.inputIds[0]].shape.reduce((a, b) => a * b, 1) },
+                (_, i) => (i % 251) / 250 - 0.5
+              )
+            )
+          );
+        const y = ctx.tensor(options.precision, program.values[program.outputIds[0]].shape);
+        outputs.push(y);
+        ctx.recordProgram(program, weights, [x, y]);
+        return ctx;
+      });
+      const timing = await compare(contexts, outputs, 1, false);
+      // The candidate preserves the original reduction order; require bitwise parity.
+      if (timing.differentBytes !== 0) throw new Error(`Model changed ${name}: ${timing.maxAbs}`);
+      results.push({ category: 'model', name, ...timing });
+      contexts.forEach((c) => c.destroy());
+    }
+    if (errors.length) throw new Error(errors.join('\n'));
+    const result = {
+      inputPattern: options.fractionalInputs ? 'fractional-rounded-products' : 'dyadic',
+      precision: options.precision,
+      gpu: { vendor: adapter.info.vendor, architecture: adapter.info.architecture },
+      browser: navigator.userAgent,
+      method:
+        'Archived baseline vs current automatic convolution routing, same device. Commands recorded once. 8 warmups, 51 alternating samples. Kernels: identical input/weight/output buffers, repeated dispatches and GPU timestamps, with boundary/neighbor fallback cases. Full unchanged YOLO and DepthART graphs: submit+sync wall time on identical fixture inputs. Poisoned outputs, all outputs required bitwise equal. No pre/post/rendering in model timings.',
+      results,
+    };
+    const response = await fetch(options.reportEndpoint, {
+      method: 'POST',
+      headers: { 'Content-Type': 'application/json' },
+      body: JSON.stringify(result),
+    });
+    if (!response.ok) throw new Error('Results upload failed');
+    return result;
+  } finally {
+    device.destroy();
+  }
+}
diff --git a/utils/benchmark/profile-stages.browser.mjs b/utils/benchmark/profile-stages.browser.mjs
new file mode 100644
index 0000000..eed2c84
--- /dev/null
+++ b/utils/benchmark/profile-stages.browser.mjs
@@ -0,0 +1,354 @@
+// Controlled ablation of the example workload. Record once, then vary only
+// crop/upload, pre/post shaders, destination texture and completion mechanism.
+export async function profilePipelineStages(options) {
+  const { WgpuExecutionContext } = await import('/@fs' + options.repo + '/src/index.ts');
+  const shaders = await import(`/src/tasks/${options.task}/shaders.ts`);
+  const depth = options.task === 'depth-estimation';
+  const half = options.precision === 'float16';
+  const extent = depth ? 448 : 640;
+  const size = [extent, extent];
+  const adapter = await navigator.gpu.requestAdapter();
+  const timestamps = options.timestamps !== false;
+  const device = await adapter.requestDevice({
+    requiredFeatures: [...(half ? ['shader-f16'] : []), ...(timestamps ? ['timestamp-query'] : [])],
+  });
+  const errors = [];
+  device.addEventListener('uncapturederror', (event) => errors.push(event.error.message));
+  const contexts = [];
+  let stream;
+  let timer;
+  const createEncoder = device.createCommandEncoder.bind(device);
+  let capture = false;
+  let passCount = 0;
+  const queries = timestamps ? device.createQuerySet({ type: 'timestamp', count: 6 }) : null;
+  const resolve = timestamps
+    ? device.createBuffer({
+        size: 48,
+        usage: GPUBufferUsage.QUERY_RESOLVE | GPUBufferUsage.COPY_SRC,
+      })
+    : null;
+  const readback = timestamps
+    ? device.createBuffer({ size: 48, usage: GPUBufferUsage.MAP_READ | GPUBufferUsage.COPY_DST })
+    : null;
+  try {
+    if (timestamps)
+      device.createCommandEncoder = function (descriptor) {
+        const encoder = createEncoder(descriptor);
+        if (!capture) return encoder;
+        const begin = encoder.beginComputePass.bind(encoder);
+        const finish = encoder.finish.bind(encoder);
+        encoder.beginComputePass = (descriptor = {}) => {
+          const index = passCount++ * 2;
+          if (index >= 6) throw new Error('Unexpected compute pass count');
+          return begin({
+            ...descriptor,
+            timestampWrites: {
+              querySet: queries,
+              beginningOfPassWriteIndex: index,
+              endOfPassWriteIndex: index + 1,
+            },
+          });
+        };
+        encoder.finish = (descriptor) => {
+          encoder.resolveQuerySet(queries, 0, passCount * 2, resolve, 0);
+          encoder.copyBufferToBuffer(resolve, 0, readback, 0, passCount * 16);
+          return finish(descriptor);
+        };
+        return encoder;
+      };
+    const canvas = document.createElement('canvas');
+    canvas.width = canvas.height = extent;
+    const canvasContext = canvas.getContext('webgpu');
+    canvasContext.configure({
+      device,
+      format: 'rgba8unorm',
+      alphaMode: 'premultiplied',
+      usage: GPUTextureUsage.RENDER_ATTACHMENT | GPUTextureUsage.COPY_DST,
+    });
+    const videoTexture = device.createTexture({
+      size,
+      format: 'rgba8unorm',
+      usage:
+        GPUTextureUsage.COPY_DST |
+        GPUTextureUsage.RENDER_ATTACHMENT |
+        GPUTextureUsage.TEXTURE_BINDING,
+    });
+    const resultTexture = device.createTexture({
+      size,
+      format: 'rgba8unorm',
+      usage: GPUTextureUsage.COPY_SRC | GPUTextureUsage.STORAGE_BINDING,
+    });
+    const scratchTexture = device.createTexture({
+      size,
+      format: 'rgba8unorm',
+      usage: GPUTextureUsage.COPY_DST,
+    });
+    const fenceSource = device.createBuffer({ size: 16, usage: GPUBufferUsage.COPY_SRC });
+    const fence = device.createBuffer({
+      size: 16,
+      usage: GPUBufferUsage.COPY_DST | GPUBufferUsage.MAP_READ,
+    });
+    const crop = new OffscreenCanvas(extent, extent);
+    const cropContext = crop.getContext('2d');
+    const source = document.createElement('canvas');
+    source.width = 1280;
+    source.height = 720;
+    const paint = source.getContext('2d');
+    const draw = () => {
+      // Repaint identical pixels so every model receives the same tensor while
+      // captureStream continues delivering fresh video frames.
+      paint.fillStyle = 'white';
+      paint.fillRect(0, 0, 1280, 720);
+      paint.fillStyle = 'black';
+      paint.beginPath();
+      paint.arc(640, 360, 120, 0, 2 * Math.PI);
+      paint.fill();
+    };
+    draw();
+    timer = setInterval(draw, 33);
+    stream = source.captureStream(30);
+    const video = document.createElement('video');
+    video.muted = true;
+    video.playsInline = true;
+    video.srcObject = stream;
+    document.body.replaceChildren(video, canvas);
+    await video.play();
+    const nextFrame = () =>
+      new Promise((done, reject) => {
+        const timeout = setTimeout(() => reject(new Error('Video frame timed out')), 5000);
+        video.requestVideoFrameCallback(() => {
+          clearTimeout(timeout);
+          done();
+        });
+      });
+    await nextFrame();
+    const cropFrame = () => cropContext.drawImage(video, 280, 0, 720, 720, 0, 0, extent, extent);
+    const upload = () =>
+      device.queue.copyExternalImageToTexture({ source: crop }, { texture: videoTexture }, size);
+    cropFrame();
+    upload();
+    const model = new WgpuExecutionContext(device);
+    const full = new WgpuExecutionContext(device);
+    const init = new WgpuExecutionContext(device);
+    contexts.push(model, full, init);
+    const input = model.tensor(options.precision, [1, 3, extent, extent]);
+    const output = model.tensor(options.precision, depth ? [1, 1, extent, extent] : [1, 84, 8400]);
+    const preprocess = half ? shaders.preprocessF16 : shaders.preprocess;
+    init.recordShader(preprocess, [videoTexture, input]);
+    init.submit();
+    await init.sync();
+    const base = `/assets/${depth ? 'depthart' : 'yolo26n'}/`;
+    const suffix = half ? '-fp16' : '';
+    const responses = await Promise.all([
+      fetch(`${base}program${suffix}.json`),
+      fetch(`${base}weights${suffix}.bin`),
+    ]);
+    if (responses.some((response) => !response.ok)) throw new Error('Model artifacts unavailable');
+    const program = await responses[0].json();
+    const weights = await responses[1].arrayBuffer();
+    model.recordProgram(program, weights, [input, output]);
+    full
+      .recordShader(preprocess, [videoTexture, input])
+      .recordProgram(program, weights, [input, output]);
+    if (depth) {
+      const stats = full.storageBuffer(16);
+      full
+        .recordShader(shaders.clearStats, [stats])
+        .recordShader(half ? shaders.depthStatsF16 : shaders.depthStats, [output, stats])
+        .recordShader(half ? shaders.drawDepthF16 : shaders.drawDepth, [
+          output,
+          stats,
+          resultTexture,
+        ]);
+    } else {
+      const counter = full.storageBuffer(16);
+      const detections = full.storageBuffer(shaders.MAX_DETECTIONS * 6 * 4);
+      full
+        .recordShader(shaders.clearDetections, [counter])
+        .recordShader(half ? shaders.compactDetectionsF16 : shaders.compactDetections, [
+          output,
+          counter,
+          detections,
+        ])
+        .recordShader(shaders.drawDetections, [videoTexture, resultTexture, counter, detections]);
+    }
+    const cases = [
+      { name: 'model-sync', sync: true },
+      { name: 'model-fence' },
+      { name: 'model-paced', paced: true },
+      { name: 'crop', paced: true, crop: true },
+      { name: 'upload', paced: true, crop: true, upload: true },
+      { name: 'prepost', paced: true, crop: true, upload: true, full: true },
+      { name: 'texture-copy', paced: true, crop: true, upload: true, full: true, copy: true },
+      {
+        name: 'canvas',
+        paced: true,
+        crop: true,
+        upload: true,
+        full: true,
+        copy: true,
+        canvas: true,
+      },
+    ];
+    async function run(test) {
+      if (test.paced) await nextFrame(); // Callback wait is excluded from all timers, as in the example.
+      const start = performance.now();
+      if (test.crop) cropFrame();
+      const cropped = performance.now();
+      if (test.upload) upload();
+      const uploaded = performance.now();
+      passCount = 0;
+      capture = timestamps;
+      try {
+        (test.full ? full : model).submit();
+      } finally {
+        capture = false;
+      }
+      const submitted = performance.now();
+      if (test.sync) await model.sync();
+      else {
+        const encoder = device.createCommandEncoder();
+        if (test.copy)
+          encoder.copyTextureToTexture(
+            { texture: resultTexture },
+            { texture: test.canvas ? canvasContext.getCurrentTexture() : scratchTexture },
+            size
+          );
+        encoder.copyBufferToBuffer(fenceSource, 0, fence, 0, 16);
+        device.queue.submit([encoder.finish()]);
+        await fence.mapAsync(GPUMapMode.READ);
+        fence.unmap();
+      }
+      const end = performance.now();
+      const result = {
+        wallMs: end - start,
+        cropCpuMs: cropped - start,
+        uploadCallCpuMs: uploaded - cropped,
+        submitCpuMs: submitted - uploaded,
+        completionWallMs: end - submitted,
+      };
+      // Read timestamps AFTER the wall timer. No extra mapAsync callback is in
+      // the measured interval; the same query instrumentation is used in every case.
+      if (timestamps) {
+        await readback.mapAsync(GPUMapMode.READ);
+        const t = [...new BigUint64Array(readback.getMappedRange())];
+        readback.unmap();
+        const index = test.full ? 2 : 0;
+        result.modelGpuMs = Number(t[index + 1] - t[index]) / 1e6;
+        result.computeSpanGpuMs = Number(t[passCount * 2 - 1] - t[0]) / 1e6;
+      }
+      return result;
+    }
+    // Seeded shuffle avoids consistently assigning earlier/higher GPU clocks
+    // to the same case. Every round contributes a paired observation.
+    let seed = 479;
+    const shuffle = () => {
+      const ordered = [...cases];
+      for (let i = ordered.length - 1; i > 0; i--) {
+        seed = (Math.imul(seed, 1664525) + 1013904223) >>> 0;
+        const j = seed % (i + 1);
+        [ordered[i], ordered[j]] = [ordered[j], ordered[i]];
+      }
+      return ordered;
+    };
+    const rounds = [];
+    for (let round = -(options.warmups ?? 8); round < (options.samples ?? 61); round++) {
+      const results = {};
+      for (const test of shuffle()) results[test.name] = await run(test);
+      if (round >= 0) rounds.push(results);
+    }
+    // Sustained ABBA blocks reproduce continuous benchmark submissions and
+    // the example's repeated canvas presentation, rather than only isolated
+    // interleaved samples. This also checks presentation at its normal cadence.
+    const sustained = [];
+    for (const name of ['model-sync', 'canvas', 'canvas', 'model-sync']) {
+      const test = cases.find((item) => item.name === name);
+      const samples = [];
+      for (let i = -4; i < 31; i++) {
+        const sample = await run(test);
+        if (i >= 0) samples.push(sample);
+      }
+      sustained.push({ name, samples });
+    }
+    if (errors.length) throw new Error(errors.join('\n'));
+    const median = (values) => [...values].sort((a, b) => a - b)[values.length >> 1];
+    const comparisons = [
+      ['model-fence', 'model-sync'],
+      ['model-paced', 'model-fence'],
+      ['crop', 'model-paced'],
+      ['upload', 'crop'],
+      ['prepost', 'upload'],
+      ['texture-copy', 'prepost'],
+      ['canvas', 'texture-copy'],
+      ['canvas', 'model-sync'],
+    ];
+    const result = {
+      task: options.task,
+      precision: options.precision,
+      timestamps,
+      warmups: options.warmups ?? 8,
+      samples: rounds.length,
+      gpu: { vendor: adapter.info.vendor, architecture: adapter.info.architecture },
+      browser: navigator.userAgent,
+      source: 'Identical 1280x720 synthetic video frames at 30fps',
+      method:
+        'Single page/device; two recorded model contexts sharing input/output tensors; shuffled paired rounds. All shaders recorded outside measurement. Video callback wait excluded. Timestamp readback occurs after the wall timer. Additional sustained ABBA blocks compare continuous model submissions to video-paced canvas output. Canvas case matches example commands; wall time ends at GPU completion notification, not display scanout.',
+      interpretation:
+        'Paired deltas are medians of within-round differences, not differences of medians. They are not additive. wallMinusModelGpuDeltaMs subtracts the paired change in model GPU duration; it is a diagnostic residual, not an independently measured stage duration. Synthetic video and headless Chrome do not reproduce every camera/compositor cost.',
+      medians: Object.fromEntries(
+        cases.map(({ name }) => [
+          name,
+          Object.fromEntries(
+            Object.keys(rounds[0][name]).map((key) => [
+              key,
+              median(rounds.map((r) => r[name][key])),
+            ])
+          ),
+        ])
+      ),
+      pairedDeltas: comparisons.map(([to, from]) => ({
+        from,
+        to,
+        ...(timestamps
+          ? {
+              wallMinusModelGpuDeltaMs: median(
+                rounds.map(
+                  (r) => r[to].wallMs - r[from].wallMs - (r[to].modelGpuMs - r[from].modelGpuMs)
+                )
+              ),
+            }
+          : {}),
+        ...Object.fromEntries(
+          Object.keys(rounds[0][to]).map((key) => [
+            key,
+            median(rounds.map((r) => r[to][key] - r[from][key])),
+          ])
+        ),
+      })),
+      sustainedWarmupsPerBlock: 4,
+      sustainedSamplesPerBlock: 31,
+      sustained: sustained.map(({ name, samples }) => ({
+        name,
+        medians: Object.fromEntries(
+          Object.keys(samples[0]).map((key) => [key, median(samples.map((r) => r[key]))])
+        ),
+        samples,
+      })),
+      rounds,
+      errors,
+    };
+    const response = await fetch(options.reportEndpoint, {
+      method: 'POST',
+      headers: { 'Content-Type': 'application/json' },
+      body: JSON.stringify(result),
+    });
+    if (!response.ok) throw new Error(`Results upload failed: ${response.status}`);
+    return result;
+  } finally {
+    clearInterval(timer);
+    stream?.getTracks().forEach((track) => track.stop());
+    await device.queue.onSubmittedWorkDone();
+    contexts.reverse().forEach((ctx) => ctx.destroy());
+    device.destroy();
+  }
+}
diff --git a/utils/benchmark/runntime-results.json b/utils/benchmark/runntime-results.json
new file mode 100644
index 0000000..7c482e6
--- /dev/null
+++ b/utils/benchmark/runntime-results.json
@@ -0,0 +1,5488 @@
+{
+  "baseline": "ceb53ab",
+  "host": "Apple M1 Pro",
+  "packages": {
+    "runntime": "0.1.0",
+    "typegpu": "0.12.8"
+  },
+  "conclusions": [
+    "YOLO26-N pixels-to-CPU-boxes: ours is faster on the tested inputs. Native photograph about 11.8-12.0 ms vs ruNNtime 15.1 ms; 1280x720 crop about 13.0-13.4 ms vs 18.5-18.6 ms, across two independent runs.",
+    "YOLO GPU compute totals are closer: ruNNtime about 9-12% slower, depending on run/input. Extra wall time also occurs outside compute (CPU preprocessing/encoding/decoding, transfers/readback and browser scheduling); do not assign the whole difference to convolution kernels.",
+    "ruNNtime has useful native conv wins: first YOLO 3x3 RGB layer about 1.8x and the 16-to-8 output-channel 3x3 layer about 2.1x. Our tested YOLO attention matmuls and several larger convolutions are faster.",
+    "Other native wins include tiny-spatial split-K pointwise, matrix-vector products and a 576-channel 5x5 depthwise case. These particular benchmark shapes occur in neither current model program. They are general operator opportunities, not a demonstrated model gain.",
+    "DepthART is not the same architecture: our export is MNV4-S, while the published ruNNtime small checkpoint is TinyViM-S (source metadata relative_s_448). Our half weights are about 4.1 MB vs the 12.6 MB ruNNtime checkpoint. Timing both tasks is valid, but attributing their roughly 2x difference to the runtimes is not.",
+    "No production kernel, graph, shader registry or model artifact was changed. Native operators ran inside ruNNtime, with named exports added to a generated copy solely to access its unpublished core."
+  ],
+  "method": {
+    "primary": "Two independent Chrome runs, one shared GPU adapter/device per task, shader-f16 and subgroups enabled. 12 warmups, 61 alternating-order samples per input/engine, batch1. CPU RGBA bytes to CPU depth map or class/score/xyxy boxes, including processing/upload/inference/readback/decoding. Image decoding, model downloading/compilation, camera capture and rendering are excluded.",
+    "inputs": "Same photograph at native square model size, the photograph at 1280x720 with center crop, and a deterministic gradient at native size. This is a latency/correctness probe on three inputs, not a dataset accuracy or COCO mAP study.",
+    "imageProcessing": "ruNNtime uses its public crop preprocessor. Our helper uses the existing GPU preprocessing shaders; non-native images use the example-style canvas crop. Interpolation and FP16 casting/fusion ordering can differ. YOLO confidence .35 and maximum 64 detections on both.",
+    "gpu": "Separate 15-sample timestamp phase; primary wall samples contain no timestamps. Sum compute-pass spans, including model and input-conversion/preprocess kernels, excluding CPU and buffer/texture copies. Diagnostic wall/residual fields pair wall and GPU times in that phase. Do not subtract GPU medians from a different phase to reconstruct a latency breakdown: GPU clocks can change.",
+    "nativeOperators": "25 native-layout cases: 15 FP16 convolutions plus 5 matrix geometries in each precision. We expose native entry points from the pinned compiled package without changing implementations. Native HWC4 input/weight packing, uploads and graph recording occur outside timing. Each library caches its own kernel selection/command list. 8 warmups, 41 alternating GPU samples, 16 replays per sample; no fused activation/residual in raw conv cases.",
+    "numerics": "YOLO public outputs match local FP32 references: all expected detections match class and IoU >=.8 with confidence difference <=.05 and no extra detections on these inputs. Raw operators validate all finite outputs and relative L2 <=3% against rounded F32 references; measured errors/maxima are retained. Native FP16 matmul uses wider accumulation, improving accuracy relative to our FP16 path on these inputs. DepthART models have different scales and opposite sign conventions; cross-model correlation is descriptive, not a correctness requirement.",
+    "kernelMembership": "modelReferenceCounts counts matching operator input/weight geometry and stride (conv) or trailing matrix dimensions (mm/bmm). A zero means that exact benchmark geometry is absent from that model.",
+    "limits": "One M1 Pro and Chrome build. Timing ratios describe this hardware/browser; cross-hardware portability and gains require separate measurements. Cold-start load timings are diagnostic and not directly comparable because setup paths differ."
+  },
+  "models": [
+    {
+      "run": 1,
+      "task": "depth-estimation",
+      "input": "photograph-native",
+      "oursWallMs": 12.100000023841858,
+      "runntimeWallMs": 25.59999990463257,
+      "oursGpuComputeMs": 10.579920999999999,
+      "runntimeGpuComputeMs": 21.897791,
+      "directRuntimeComparison": false
+    },
+    {
+      "run": 1,
+      "task": "depth-estimation",
+      "input": "photograph-1280x720-crop",
+      "oursWallMs": 13.199999928474426,
+      "runntimeWallMs": 27.899999976158142,
+      "oursGpuComputeMs": 11.067746000000001,
+      "runntimeGpuComputeMs": 23.563182,
+      "directRuntimeComparison": false
+    },
+    {
+      "run": 1,
+      "task": "depth-estimation",
+      "input": "gradient-native",
+      "oursWallMs": 12.100000023841858,
+      "runntimeWallMs": 25.899999976158142,
+      "oursGpuComputeMs": 10.449466000000001,
+      "runntimeGpuComputeMs": 21.97504,
+      "directRuntimeComparison": false
+    },
+    {
+      "run": 1,
+      "task": "yolo26-detection",
+      "input": "photograph-native",
+      "oursWallMs": 11.799999952316284,
+      "runntimeWallMs": 15.099999904632568,
+      "oursGpuComputeMs": 10.488507,
+      "runntimeGpuComputeMs": 11.404368,
+      "directRuntimeComparison": true
+    },
+    {
+      "run": 1,
+      "task": "yolo26-detection",
+      "input": "photograph-1280x720-crop",
+      "oursWallMs": 13,
+      "runntimeWallMs": 18.5,
+      "oursGpuComputeMs": 9.068987,
+      "runntimeGpuComputeMs": 10.142388,
+      "directRuntimeComparison": true
+    },
+    {
+      "run": 1,
+      "task": "yolo26-detection",
+      "input": "gradient-native",
+      "oursWallMs": 13.299999952316284,
+      "runntimeWallMs": 16.299999952316284,
+      "oursGpuComputeMs": 9.088112,
+      "runntimeGpuComputeMs": 10.167303,
+      "directRuntimeComparison": true
+    },
+    {
+      "run": 2,
+      "task": "depth-estimation",
+      "input": "photograph-native",
+      "oursWallMs": 12.300000071525574,
+      "runntimeWallMs": 26,
+      "oursGpuComputeMs": 13.084551,
+      "runntimeGpuComputeMs": 27.867158,
+      "directRuntimeComparison": false
+    },
+    {
+      "run": 2,
+      "task": "depth-estimation",
+      "input": "photograph-1280x720-crop",
+      "oursWallMs": 13.700000047683716,
+      "runntimeWallMs": 29.299999952316284,
+      "oursGpuComputeMs": 10.573046,
+      "runntimeGpuComputeMs": 22.165912,
+      "directRuntimeComparison": false
+    },
+    {
+      "run": 2,
+      "task": "depth-estimation",
+      "input": "gradient-native",
+      "oursWallMs": 12.200000047683716,
+      "runntimeWallMs": 27.600000023841858,
+      "oursGpuComputeMs": 10.633505,
+      "runntimeGpuComputeMs": 23.43906,
+      "directRuntimeComparison": false
+    },
+    {
+      "run": 2,
+      "task": "yolo26-detection",
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+                    18.799999952316284, 21.700000047683716, 19.699999928474426, 19.100000023841858,
+                    18.799999952316284, 18.600000023841858, 20.600000023841858, 19.299999952316284,
+                    17.5, 17.899999976158142, 18.199999928474426, 17.90000009536743,
+                    19.899999976158142, 18.100000023841858, 17.899999976158142, 18.200000047683716,
+                    18, 18.100000023841858, 18.600000023841858, 20.299999952316284,
+                    18.09999990463257, 18.300000071525574, 17.600000023841858, 18,
+                    18.100000023841858, 18.299999952316284, 20.899999976158142, 18.299999952316284,
+                    18.90000009536743, 18.799999952316284, 18.200000047683716, 18.5,
+                    18.600000023841858, 18.699999928474426, 20.199999928474426, 19.600000023841858,
+                    19, 18.5, 19.699999928474426, 19.899999976158142, 20, 19, 18,
+                    18.300000071525574, 18.300000071525574, 18.600000023841858, 19.5,
+                    18.899999976158142, 18.600000023841858, 18, 20.100000023841858,
+                    19.100000023841858, 18.899999976158142, 19.199999928474426, 20.100000023841858,
+                    18.799999952316284, 19.59999990463257
+                  ]
+                }
+              ],
+              "gpuComputeMs": [
+                {
+                  "median": 9.553812,
+                  "p10": 9.128777999999999,
+                  "p90": 10.073053999999999,
+                  "samples": [
+                    9.933764, 9.798850999999999, 10.356048999999999, 9.80181, 10.073053999999999,
+                    9.068445, 9.128777999999999, 9.415731000000001, 9.778058000000001,
+                    9.575270999999999, 9.451521999999999, 9.535021, 9.553812, 9.491938000000001,
+                    9.389772
+                  ]
+                },
+                {
+                  "median": 10.50734,
+                  "p10": 10.091596,
+                  "p90": 10.978582,
+                  "samples": [
+                    10.762586, 10.978582, 10.585213, 10.621504, 10.133678, 10.126846, 10.091596,
+                    10.81671, 10.372676, 11.048664, 10.477382, 10.749044, 10.348967, 10.50734,
+                    10.068888
+                  ]
+                }
+              ],
+              "computePassCounts": [
+                [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2],
+                [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+              ],
+              "diagnosticWallMs": [
+                {
+                  "median": 13.5,
+                  "p10": 13,
+                  "p90": 14,
+                  "samples": [
+                    14, 13.600000023841858, 14, 13.899999976158142, 13.899999976158142,
+                    12.799999952316284, 13, 13, 13.600000023841858, 13.5, 13.200000047683716, 13.5,
+                    13.5, 13.100000023841858, 13
+                  ]
+                },
+                {
+                  "median": 18.800000071525574,
+                  "p10": 17.899999976158142,
+                  "p90": 20.299999952316284,
+                  "samples": [
+                    18.899999976158142, 21.899999976158142, 18.90000009536743, 18.700000047683716,
+                    20.299999952316284, 17.899999976158142, 18.799999952316284, 18.59999990463257,
+                    19.699999928474426, 18.700000047683716, 18.800000071525574, 19.09999990463257,
+                    20.199999928474426, 18.100000023841858, 17.800000071525574
+                  ]
+                }
+              ],
+              "nonComputeResidualMs": [
+                {
+                  "median": 3.8219420238418564,
+                  "p10": 3.608062023841857,
+                  "p90": 4.066236,
+                  "samples": [
+                    4.066236, 3.801149023841859, 3.6439510000000013, 4.098189976158142,
+                    3.826945976158143, 3.7315549523162836, 3.8712220000000013, 3.584268999999999,
+                    3.8219420238418564, 3.924729000000001, 3.748478047683717, 3.9649789999999996,
+                    3.9461879999999994, 3.608062023841857, 3.6102279999999993
+                  ]
+                },
+                {
+                  "median": 8.314787095367432,
+                  "p10": 7.651336047683715,
+                  "p90": 10.166321952316284,
+                  "samples": [
+                    8.137413976158141, 10.921417976158143, 8.314787095367432, 8.078496047683716,
+                    10.166321952316284, 7.773153976158142, 8.708403952316285, 7.783289904632568,
+                    9.327323928474426, 7.651336047683715, 8.322618071525573, 8.350955904632569,
+                    9.851032928474426, 7.592660023841859, 7.731112071525574
+                  ]
+                }
+              ],
+              "runntimeOverOursWall": 1.388059705741476,
+              "runntimeOverOursGpu": 1.0998060250714583,
+              "validation": [
+                {
+                  "passesReferenceCheck": true,
+                  "detections": [
+                    {
+                      "classId": 0,
+                      "label": "person",
+                      "confidence": 0.9072265625,
+                      "box": {
+                        "format": "xyxy",
+                        "xmin": 355.4453125,
+                        "ymin": 263.953125,
+                        "xmax": 543.8125,
+                        "ymax": 571.78125
+                      }
+                    },
+                    {
+                      "classId": 0,
+                      "label": "person",
+                      "confidence": 0.517578125,
+                      "box": {
+                        "format": "xyxy",
+                        "xmin": 279.9296875,
+                        "ymin": 331.875,
+                        "xmax": 347.32421875,
+                        "ymax": 589.5
+                      }
+                    }
+                  ],
+                  "referenceDetections": 2,
+                  "matchedAtIoU08": 2,
+                  "matches": [
+                    {
+                      "classId": 0,
+                      "confidence": 0.9058433771133423,
+                      "bestIoU": 0.9972253843672596,
+                      "confidenceDifference": 0.0013831853866577148
+                    },
+                    {
+                      "classId": 0,
+                      "confidence": 0.523906946182251,
+                      "bestIoU": 0.9879984309838513,
+                      "confidenceDifference": 0.0063288211822509766
+                    }
+                  ],
+                  "unmatchedResults": 0
+                },
+                {
+                  "passesReferenceCheck": true,
+                  "detections": [
+                    {
+                      "label": "person",
+                      "classId": 0,
+                      "confidence": 0.9053222982086733,
+                      "box": {
+                        "format": "xyxy",
+                        "xmin": 355.23437500000006,
+                        "ymin": 264.375,
+                        "xmax": 543.7421875000001,
+                        "ymax": 572.0625
+                      }
+                    },
+                    {
+                      "label": "person",
+                      "classId": 0,
+                      "confidence": 0.5292633933665886,
+                      "box": {
+                        "format": "xyxy",
+                        "xmin": 279.9296875,
+                        "ymin": 331.734375,
+                        "xmax": 347.99218750000006,
+                        "ymax": 589.8515625
+                      }
+                    }
+                  ],
+                  "referenceDetections": 2,
+                  "matchedAtIoU08": 2,
+                  "matches": [
+                    {
+                      "classId": 0,
+                      "confidence": 0.9058433771133423,
+                      "bestIoU": 0.9984447025554218,
+                      "confidenceDifference": 0.0005210789046690145
+                    },
+                    {
+                      "classId": 0,
+                      "confidence": 0.523906946182251,
+                      "bestIoU": 0.998233953637857,
+                      "confidenceDifference": 0.005356447184337587
+                    }
+                  ],
+                  "unmatchedResults": 0
+                }
+              ],
+              "modelEquivalence": "Both YOLO26-N one-to-one head; same input size and detection options. ruNNtime decodes raw distances/logits on CPU; our export decodes boxes/scores on GPU."
+            },
+            {
+              "name": "gradient-native",
+              "width": 640,
+              "height": 640,
+              "engines": ["wgpu-executorch-fp16", "runntime-0.1.0"],
+              "wallMs": [
+                {
+                  "median": 12.400000095367432,
+                  "p10": 12.199999928474426,
+                  "p90": 13.699999928474426,
+                  "samples": [
+                    12.200000047683716, 12.400000095367432, 12.099999904632568, 12.399999976158142,
+                    12.5, 12.700000047683716, 12.199999928474426, 12.200000047683716,
+                    12.299999952316284, 12.399999976158142, 14.5, 12.700000047683716,
+                    12.699999928474426, 13.300000071525574, 14.099999904632568, 15.799999952316284,
+                    13.800000071525574, 13.699999928474426, 14.600000023841858, 14.399999976158142,
+                    13.100000023841858, 12.399999976158142, 12.399999976158142, 12.899999976158142,
+                    12.600000023841858, 12.399999976158142, 12.5, 12.400000095367432,
+                    12.199999928474426, 12.700000047683716, 12.199999928474426, 12.200000047683716,
+                    12.399999976158142, 12.299999952316284, 12.300000071525574, 12.200000047683716,
+                    12.200000047683716, 12.399999976158142, 12.299999952316284, 12.100000023841858,
+                    12.099999904632568, 12.299999952316284, 12.400000095367432, 12.199999928474426,
+                    12.600000023841858, 12.199999928474426, 12.600000023841858, 12.899999976158142,
+                    12.5, 12.400000095367432, 12.299999952316284, 12.600000023841858,
+                    12.399999976158142, 12.600000023841858, 12.300000071525574, 13, 12.5, 12.5,
+                    12.399999976158142, 12.5, 12.5
+                  ]
+                },
+                {
+                  "median": 15.399999976158142,
+                  "p10": 14.799999952316284,
+                  "p90": 17.5,
+                  "samples": [
+                    16.699999928474426, 14.899999976158142, 14.900000095367432, 14.699999928474426,
+                    16.90000009536743, 15.199999928474426, 14.600000023841858, 14.899999976158142,
+                    16.800000071525574, 15, 15, 16.5, 20.800000071525574, 18.199999928474426,
+                    16.90000009536743, 19.399999976158142, 16.09999990463257, 16.40000009536743,
+                    18.600000023841858, 17.5, 15.699999928474426, 14.800000071525574,
+                    17.700000047683716, 15.600000023841858, 15.599999904632568, 15.700000047683716,
+                    17.600000023841858, 15.299999952316284, 15.100000023841858, 14.899999976158142,
+                    14.700000047683716, 17.399999976158142, 14.899999976158142, 15.100000023841858,
+                    14.799999952316284, 16.899999976158142, 15.299999952316284, 14.700000047683716,
+                    14.899999976158142, 14.800000071525574, 16.800000071525574, 14.899999976158142,
+                    14.899999976158142, 15.100000023841858, 15.200000047683716, 15.5, 17, 15.5,
+                    15.600000023841858, 14.799999952316284, 16.899999976158142, 15,
+                    15.399999976158142, 17, 17.09999990463257, 15.600000023841858, 15,
+                    15.300000071525574, 14.899999976158142, 16.799999952316284, 14.5
+                  ]
+                }
+              ],
+              "gpuComputeMs": [
+                {
+                  "median": 9.455481,
+                  "p10": 9.2289,
+                  "p90": 9.565187,
+                  "samples": [
+                    9.2289, 9.504647, 9.455814, 9.398022999999998, 9.574313, 9.427897999999999,
+                    9.489314, 9.090110000000001, 9.401398, 9.455481, 9.565187, 9.429939, 9.564604,
+                    9.388564, 9.543938
+                  ]
+                },
+                {
+                  "median": 10.291509,
+                  "p10": 10.250428,
+                  "p90": 10.388883,
+                  "samples": [
+                    10.377675, 10.291509, 10.213636, 10.252968, 10.362466, 10.266177, 10.28401,
+                    10.278343, 10.330592, 10.449216, 10.300427, 10.250428, 10.278135, 10.388883,
+                    10.324676
+                  ]
+                }
+              ],
+              "computePassCounts": [
+                [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2],
+                [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+              ],
+              "diagnosticWallMs": [
+                {
+                  "median": 12.599999904632568,
+                  "p10": 12.300000071525574,
+                  "p90": 13,
+                  "samples": [
+                    12.5, 12.599999904632568, 12.600000023841858, 12.799999952316284,
+                    13.200000047683716, 12.600000023841858, 13, 12.300000071525574, 12.5,
+                    12.600000023841858, 12.5, 12.5, 12.799999952316284, 12.299999952316284,
+                    12.399999976158142
+                  ]
+                },
+                {
+                  "median": 15.300000071525574,
+                  "p10": 14.800000071525574,
+                  "p90": 17.299999952316284,
+                  "samples": [
+                    15.100000023841858, 14.800000071525574, 17.299999952316284, 15.399999976158142,
+                    15.299999952316284, 15.5, 14.799999952316284, 17.299999952316284,
+                    14.800000071525574, 15.300000071525574, 14.899999976158142, 17.100000023841858,
+                    15.399999976158142, 15.200000047683716, 15.399999976158142
+                  ]
+                }
+              ],
+              "nonComputeResidualMs": [
+                {
+                  "median": 3.144519023841857,
+                  "p10": 2.9114359523162836,
+                  "p90": 3.5106859999999998,
+                  "samples": [
+                    3.2711000000000006, 3.095352904632568, 3.1441860238418577, 3.4019769523162857,
+                    3.6256870476837157, 3.172102023841859, 3.5106859999999998, 3.2098900715255727,
+                    3.0986019999999996, 3.144519023841857, 2.934813, 3.070061000000001,
+                    3.235395952316285, 2.9114359523162836, 2.8560619761581414
+                  ]
+                },
+                {
+                  "median": 4.937533952316285,
+                  "p10": 4.508491071525574,
+                  "p90": 7.021656952316285,
+                  "samples": [
+                    4.722325023841858, 4.508491071525574, 7.086363952316285, 5.147031976158143,
+                    4.937533952316285, 5.233822999999999, 4.515989952316284, 7.021656952316285,
+                    4.469408071525574, 4.850784071525574, 4.599572976158141, 6.8495720238418585,
+                    5.121864976158141, 4.811117047683716, 5.075323976158142
+                  ]
+                }
+              ],
+              "runntimeOverOursWall": 1.2419354723966085,
+              "runntimeOverOursGpu": 1.088417289400719,
+              "validation": [
+                {
+                  "passesReferenceCheck": true,
+                  "detections": [],
+                  "referenceDetections": 0,
+                  "matchedAtIoU08": 0,
+                  "matches": [],
+                  "unmatchedResults": 0
+                },
+                {
+                  "passesReferenceCheck": true,
+                  "detections": [],
+                  "referenceDetections": 0,
+                  "matchedAtIoU08": 0,
+                  "matches": [],
+                  "unmatchedResults": 0
+                }
+              ],
+              "modelEquivalence": "Both YOLO26-N one-to-one head; same input size and detection options. ruNNtime decodes raw distances/logits on CPU; our export decodes boxes/scores on GPU."
+            }
+          ]
+        }
+      ]
+    }
+  ]
+}
diff --git a/utils/benchmark/runntime/entry.mjs b/utils/benchmark/runntime/entry.mjs
new file mode 100644
index 0000000..e823d7b
--- /dev/null
+++ b/utils/benchmark/runntime/entry.mjs
@@ -0,0 +1,11 @@
+// Published packages, with versions and transitive dependencies pinned by package-lock.json.
+export { default as tgpu } from 'typegpu';
+export {
+  initRunntime,
+  createObjectDetector,
+  createDepthEstimator,
+  imageBuffer,
+  models,
+} from 'runntime/zoo';
+
+export * as kernelInternals from './node_modules/runntime/dist/wgpu-benchmark-internals.mjs';
diff --git a/utils/benchmark/runntime/kernels.browser.mjs b/utils/benchmark/runntime/kernels.browser.mjs
new file mode 100644
index 0000000..cbbfff2
--- /dev/null
+++ b/utils/benchmark/runntime/kernels.browser.mjs
@@ -0,0 +1,242 @@
+// Native ruNNtime operators: packing/capture outside timing, no shader ports.
+export async function compareRunntimeKernels({ repo, device, root, lib, gpuTime }) {
+  const { WgpuExecutionContext, shaders } = await import(
+    /* @vite-ignore */ '/@fs' + repo + '/src/index.ts'
+  );
+  lib.initRunntime(root);
+  const fill = (n) => Float32Array.from({ length: n }, (_, i) => (((i * 17 + 11) % 61) - 30) / 128);
+  const median = (a) => [...a].sort((x, y) => x - y)[a.length >> 1];
+  const results = [];
+  const programs = await Promise.all(
+    ['yolo26n', 'depthart'].map(async (name) => {
+      const response = await fetch(`/assets/${name}/program.json`);
+      if (!response.ok) throw new Error('Missing model descriptor for kernel membership');
+      return [name, await response.json()];
+    })
+  );
+  function membership(c) {
+    return Object.fromEntries(
+      programs.map(([name, program]) => [
+        name,
+        program.chain.filter((op) => {
+          const a = program.values[op.args[0]]?.shape,
+            b = program.values[op.args[1]]?.shape;
+          if (!a || !b) return false;
+          if (c.op === 'conv2d') {
+            const [ic, oc, h, k, stride, groups] = c.shape;
+            return (
+              ['aten.convolution.default', 'et_vk.conv_with_clamp.default'].includes(op.name) &&
+              a.length === 4 &&
+              a[1] === ic &&
+              a[2] === h &&
+              a[3] === h &&
+              b[0] === oc &&
+              b[1] === ic / groups &&
+              b[2] === k &&
+              b[3] === k &&
+              program.values[op.args[3]]?.items?.[0] === stride
+            );
+          }
+          const [m, k, n] = c.shape;
+          return (
+            ['aten.mm.default', 'aten.bmm.default'].includes(op.name) &&
+            a.at(-2) === m &&
+            a.at(-1) === k &&
+            b.at(-1) === n
+          );
+        }).length,
+      ])
+    );
+  }
+  const cases = [
+    ...[
+      [48, 64, 160, 1, 1, 1],
+      [64, 64, 80, 1, 1, 1],
+      [192, 128, 40, 1, 1, 1],
+      [256, 256, 20, 1, 1, 1],
+      [80, 80, 20, 1, 1, 1],
+      [32, 16, 80, 1, 1, 1],
+      [960, 1280, 1, 1, 1, 1],
+      [3, 16, 640, 3, 2, 1],
+      [16, 32, 320, 3, 2, 1],
+      [64, 64, 160, 3, 2, 1],
+      [128, 256, 40, 3, 2, 1],
+      [64, 16, 80, 3, 1, 1],
+      [16, 8, 160, 3, 1, 1],
+      [64, 64, 80, 3, 1, 64],
+      [576, 576, 14, 5, 1, 576],
+    ].map((shape) => ({ op: 'conv2d', dtype: 'float16', shape })),
+    ...['float16', 'float32'].flatMap((dtype) =>
+      [
+        [400, 32, 400],
+        [64, 400, 400],
+        [128, 384, 1152],
+        [32, 1536, 384],
+        [1, 288, 864],
+      ].map((shape) => ({ op: 'matmul', dtype, shape }))
+    ),
+  ];
+  for (const c of cases) {
+    const ours = new WgpuExecutionContext(device),
+      oracle = new WgpuExecutionContext(device),
+      ex = lib.gpuExecutor(root);
+    const array = c.dtype === 'float16' ? Float16Array : Float32Array,
+      dtype = c.dtype === 'float16' ? 'f16' : 'f32';
+    const nativeInputs = [];
+    let build,
+      output,
+      referenceOutput,
+      unlayout = (a) => a;
+    if (c.op === 'conv2d') {
+      const [ic, oc, h, k, s, groups] = c.shape,
+        pad = (k - 1) >> 1,
+        oh = Math.floor((h + 2 * pad - k) / s) + 1;
+      const xv = fill(ic * h * h),
+        wv = fill(oc * (ic / groups) * k * k),
+        bv = fill(oc);
+      const x = ours.tensor(c.dtype, [1, ic, h, h]).setData(new array(xv));
+      const w = ours.tensor(c.dtype, [oc, ic / groups, k, k]).setData(new array(wv));
+      const b = ours.tensor(c.dtype, [oc]).setData(new array(bv));
+      output = ours.tensor(c.dtype, [1, oc, oh, oh]);
+      ours.recordShader(shaders.convolution, [
+        x,
+        w,
+        b,
+        [s, s],
+        [pad, pad],
+        [1, 1],
+        false,
+        [0, 0],
+        groups,
+        output,
+      ]);
+      const x32 = oracle.tensor('float32', x.shape).setData(xv),
+        w32 = oracle.tensor('float32', w.shape).setData(wv),
+        b32 = oracle.tensor('float32', b.shape).setData(bv);
+      referenceOutput = oracle.tensor('float32', output.shape);
+      oracle.recordShader(shaders.convolution, [
+        x32,
+        w32,
+        b32,
+        [s, s],
+        [pad, pad],
+        [1, 1],
+        false,
+        [0, 0],
+        groups,
+        referenceOutput,
+      ]);
+      const xm = lib.hwc4Meta(ic, h, h),
+        c4 = xm.elems / (h * h),
+        packedX = new Float32Array(xm.elems);
+      for (let channel = 0; channel < ic; channel++)
+        for (let p = 0; p < h * h; p++) packedX[p * c4 + channel] = xv[channel * h * h + p];
+      const nx = lib.tensor(root, packedX, xm),
+        bits = lib.f32ArrayToF16Bits(wv).data;
+      const packedW =
+        groups === 1 ? lib.packConvHwc4F16(bits, oc, ic, k, k) : lib.packDwHwc4F16(bits, ic, k, k);
+      const nw = lib.materialized(
+        { elems: wv.length, dtype: 'f16', dims: [oc, (ic / groups) * k * k], layout: 'hwc4' },
+        lib.uploadF16(root, packedW)
+      );
+      const nb = lib.tensor(root, bv, { elems: oc, dtype: 'f16', dims: [oc] });
+      nativeInputs.push(nx, nw, nb);
+      build = () => lib.conv2d(nx, nw, nb, { kernelSize: k, stride: s, padding: pad, groups });
+      unlayout = (raw) => {
+        const result = new Float32Array(oc * oh * oh),
+          oc4 = Math.ceil(oc / 4) * 4;
+        for (let channel = 0; channel < oc; channel++)
+          for (let p = 0; p < oh * oh; p++) result[channel * oh * oh + p] = raw[p * oc4 + channel];
+        return result;
+      };
+    } else {
+      const [m, k, n] = c.shape,
+        av = fill(m * k),
+        bv = fill(k * n);
+      const a = ours.tensor(c.dtype, [m, k]).setData(new array(av)),
+        b = ours.tensor(c.dtype, [k, n]).setData(new array(bv));
+      output = ours.tensor(c.dtype, [m, n]);
+      ours.recordShader(shaders.mm, [a, b, output]);
+      const a32 = oracle.tensor('float32', [m, k]).setData(av),
+        b32 = oracle.tensor('float32', [k, n]).setData(bv);
+      referenceOutput = oracle.tensor('float32', [m, n]);
+      oracle.recordShader(shaders.mm, [a32, b32, referenceOutput]);
+      const na = lib.tensor(root, av, { elems: m * k, dtype, dims: [m, k] }),
+        nb = lib.tensor(root, bv, { elems: k * n, dtype, dims: [k, n] });
+      nativeInputs.push(na, nb);
+      build = () => lib.matmul(na, nb);
+    }
+    device.pushErrorScope('validation');
+    const captured = ex.captureFrame(() => {
+      const out = build();
+      lib.evalValues([out], ex);
+      return out;
+    });
+    const validationError = await device.popErrorScope();
+    if (validationError) throw new Error(validationError.message);
+    const runs = [() => ours.submit(), () => captured.replay()];
+    const repeats = 16;
+    for (let i = 0; i < 8; i++)
+      for (const run of runs) {
+        for (let r = 0; r < repeats; r++) run();
+        await device.queue.onSubmittedWorkDone();
+      }
+    const samples = [[], []];
+    for (let i = 0; i < 41; i++)
+      for (const engine of i & 1 ? [1, 0] : [0, 1])
+        samples[engine].push(
+          (await gpuTime(() => {
+            for (let r = 0; r < repeats; r++) runs[engine]();
+          })) / repeats
+        );
+    oracle.submit();
+    const reference = new array(new Float32Array(await referenceOutput.getData()));
+    const oursValues = new array(await output.getData());
+    const nativeValues = unlayout(
+      await ex.readback(captured.targets.buffer, { elems: captured.targets.shape.elems, dtype })
+    );
+    const validation = [oursValues, nativeValues].map((values) => {
+      if (values.length !== reference.length)
+        throw new Error('Native kernel output shape mismatch');
+      let maxAbs = 0,
+        error2 = 0,
+        signal2 = 0;
+      for (let i = 0; i < values.length; i++) {
+        if (!Number.isFinite(values[i])) throw new Error('Nonfinite native kernel output');
+        const error = values[i] - reference[i];
+        maxAbs = Math.max(maxAbs, Math.abs(error));
+        error2 += error * error;
+        signal2 += reference[i] * reference[i];
+      }
+      return {
+        maxAbsVsRoundedF32: maxAbs,
+        relativeL2VsRoundedF32: Math.sqrt(error2 / Math.max(signal2, 1e-30)),
+      };
+    });
+    // Detect indexing/packing failures; mixed-precision accumulation need not be bitwise equal.
+    if (validation.some((v) => v.relativeL2VsRoundedF32 > 0.03))
+      throw new Error(
+        `Kernel reference mismatch ${JSON.stringify(c)}: ${JSON.stringify(validation)}`
+      );
+    const medians = samples.map(median);
+    results.push({
+      ...c,
+      repeats,
+      modelReferenceCounts: membership(c),
+      engines: ['wgpu-executorch', 'runntime-native'],
+      gpuMs: medians,
+      runntimeOverOurs: medians[1] / medians[0],
+      samples,
+      validation,
+    });
+    nativeInputs.forEach((v) => v.buffer.destroy());
+    ex.dispose();
+    ours.destroy();
+    oracle.destroy();
+  }
+  return {
+    method:
+      'Published package implementation plus named exports only. Native conv uses HWC4/mat4 weight packing; ours uses NCHW. Packing, upload, graph capture and correctness readback excluded. No activation/residual fusion in these raw cases. Both libraries select their own kernels. 8 warmups, 41 alternating GPU timestamp samples, 16 replays per sample, one recorded invocation per submit, summed GPU compute duration divided by 16. Validation requires relative L2 error <=3% for these FP16 accumulation workloads and records max absolute error. F16 numerical differences compared with F32 on identical rounded dyadic inputs. These are native-layout cached-input microbenchmarks; use whole-model results for application performance.',
+    results,
+  };
+}
diff --git a/utils/benchmark/runntime/package-lock.json b/utils/benchmark/runntime/package-lock.json
new file mode 100644
index 0000000..bd9e0d6
--- /dev/null
+++ b/utils/benchmark/runntime/package-lock.json
@@ -0,0 +1,99 @@
+{
+  "name": "wgpu-executorch-runntime-comparison",
+  "lockfileVersion": 3,
+  "requires": true,
+  "packages": {
+    "": {
+      "name": "wgpu-executorch-runntime-comparison",
+      "dependencies": {
+        "runntime": "0.1.0",
+        "typegpu": "0.12.8"
+      }
+    },
+    "node_modules/base64-js": {
+      "version": "1.5.1",
+      "resolved": "https://registry.npmjs.org/base64-js/-/base64-js-1.5.1.tgz",
+      "integrity": "sha512-AKpaYlHn8t4SVbOHCy+b5+KKgvR4vrsD8vbvrbiQJps7fKDTkjkDry6ji0rUJjC0kzbNePLwzxq8iypo41qeWA==",
+      "funding": [
+        {
+          "type": "github",
+          "url": "https://github.com/sponsors/feross"
+        },
+        {
+          "type": "patreon",
+          "url": "https://www.patreon.com/feross"
+        },
+        {
+          "type": "consulting",
+          "url": "https://feross.org/support"
+        }
+      ],
+      "license": "MIT"
+    },
+    "node_modules/js-tiktoken": {
+      "version": "1.0.21",
+      "resolved": "https://registry.npmjs.org/js-tiktoken/-/js-tiktoken-1.0.21.tgz",
+      "integrity": "sha512-biOj/6M5qdgx5TKjDnFT1ymSpM5tbd3ylwDtrQvFQSu0Z7bBYko2dF+W/aUkXUPuk6IVpRxk/3Q2sHOzGlS36g==",
+      "license": "MIT",
+      "dependencies": {
+        "base64-js": "^1.5.1"
+      }
+    },
+    "node_modules/runntime": {
+      "version": "0.1.0",
+      "resolved": "https://registry.npmjs.org/runntime/-/runntime-0.1.0.tgz",
+      "integrity": "sha512-YGrtKfc9yB7V2SxxsXoytCqPTzrFv5xr3SnXxuxLkCeW0Inkg318+yRH3WFrgZvattvmESwNu3Vv+g+oQME+vQ==",
+      "license": "MIT",
+      "dependencies": {
+        "js-tiktoken": "^1.0.20"
+      },
+      "peerDependencies": {
+        "@huggingface/transformers": "^4.2.0",
+        "typegpu": "^0.12.5"
+      },
+      "peerDependenciesMeta": {
+        "@huggingface/transformers": {
+          "optional": true
+        }
+      }
+    },
+    "node_modules/tinyest": {
+      "version": "0.3.4",
+      "resolved": "https://registry.npmjs.org/tinyest/-/tinyest-0.3.4.tgz",
+      "integrity": "sha512-81EcMHTCQ2IPweOGk9SpMgjbenR9ZJRsAE84btEv0DhvVKwhe7qBy28hWgatoXa9ppWzmtpHiJ+e86SiaAtY6w==",
+      "license": "MIT",
+      "engines": {
+        "node": ">=12.20.0"
+      }
+    },
+    "node_modules/tsover-runtime": {
+      "version": "0.0.7",
+      "resolved": "https://registry.npmjs.org/tsover-runtime/-/tsover-runtime-0.0.7.tgz",
+      "integrity": "sha512-FHHwMJzZbnP23+fU1PxXljy7j0RRRosL2r1/CRUNTqfW+l7m35JsUkM615x/cAzw4GqRdXPIl3axKMj9qzpZtQ==",
+      "license": "Apache-2.0"
+    },
+    "node_modules/typed-binary": {
+      "version": "4.3.4",
+      "resolved": "https://registry.npmjs.org/typed-binary/-/typed-binary-4.3.4.tgz",
+      "integrity": "sha512-ivy9nisfsBhugH6OrygtdYI28c28mo7AFeB85COUzGG6MmuViFQPz4ylmDHNjAI3P12EAxWhqtjLsdYWfCj6xQ==",
+      "license": "MIT"
+    },
+    "node_modules/typegpu": {
+      "version": "0.12.8",
+      "resolved": "https://registry.npmjs.org/typegpu/-/typegpu-0.12.8.tgz",
+      "integrity": "sha512-OC9fDTH9YVA7IYqh8B4QF+2ADdNfy7q5YfBsI42EVk04+VLezTfrs+PVoqj8Pv+ewgOC/vjbbFmSugVrPwCsMw==",
+      "license": "MIT",
+      "dependencies": {
+        "tinyest": "~0.3.4",
+        "tsover-runtime": "^0.0.7",
+        "typed-binary": "^4.3.3"
+      },
+      "bin": {
+        "typegpu": "bin.mjs"
+      },
+      "engines": {
+        "node": ">=12.20.0"
+      }
+    }
+  }
+}
diff --git a/utils/benchmark/runntime/package.json b/utils/benchmark/runntime/package.json
new file mode 100644
index 0000000..9f7ef43
--- /dev/null
+++ b/utils/benchmark/runntime/package.json
@@ -0,0 +1,9 @@
+{
+  "name": "wgpu-executorch-runntime-comparison",
+  "private": true,
+  "type": "module",
+  "dependencies": {
+    "runntime": "0.1.0",
+    "typegpu": "0.12.8"
+  }
+}
diff --git a/utils/benchmark/runntime/setup.mjs b/utils/benchmark/runntime/setup.mjs
new file mode 100644
index 0000000..ea94e36
--- /dev/null
+++ b/utils/benchmark/runntime/setup.mjs
@@ -0,0 +1,119 @@
+// Download published weights into an external cache; no model files enter git.
+import { mkdir, readFile, writeFile } from 'node:fs/promises';
+import { dirname, join } from 'node:path';
+import { tmpdir } from 'node:os';
+import { fileURLToPath } from 'node:url';
+import { createHash } from 'node:crypto';
+
+export async function prepareRunntimeAssets() {
+  const directory = process.env.WGPU_RUNNTIME_ASSETS ?? join(tmpdir(), 'wgpu-runntime-assets');
+  await mkdir(directory, { recursive: true });
+  // Expose native core entry points without editing any operator or shader.
+  // The published zoo hides core APIs, although their compiled implementations
+  // are present in its bundle. The generated sibling only adds exports.
+  const dist = join(dirname(fileURLToPath(import.meta.url)), 'node_modules/runntime/dist');
+  const sourceName = 'classifier-ByH6OI6h.mjs';
+  const source = await readFile(join(dist, sourceName), 'utf8');
+  if (
+    createHash('sha256').update(source).digest('hex') !==
+    '28c6bfa6a8cf86b84d84f173b36fd4ff82b3766ee29412f4ce5615ffa21d859e'
+  )
+    throw new Error('Unexpected ruNNtime implementation; reinstall pinned benchmark dependencies');
+  const internalPath = join(dist, 'wgpu-benchmark-internals.mjs');
+  const exposed = [
+    'conv2d',
+    'matmul',
+    'tensor',
+    'gpuExecutor',
+    'evalValues',
+    'initRunntime',
+    'materialized',
+    'uploadF16',
+    'hwc4Meta',
+    'packConvHwc4F16',
+    'packDwHwc4F16',
+    'f32ArrayToF16Bits',
+  ];
+  await writeFile(
+    internalPath,
+    source +
+      '\n// Benchmark-only exports; original implementation above is unchanged.\nexport { ' +
+      exposed.join(', ') +
+      ' };\n'
+  );
+  const internals = {
+    sourceName,
+    sha256: createHash('sha256').update(source).digest('hex'),
+    exposed,
+    change: 'Added named exports only; implementation byte-for-byte unchanged.',
+  };
+  const provenance = [];
+  for (const [model, subpath, sha, expectedHash] of [
+    [
+      'yolo26',
+      'n/f16',
+      '7d0ca883e0690966c49efefeea19c5d349dc451b',
+      '696d40c76a64924d32931de76ff062066888ecc076fe0d91d6b106d435f04287',
+    ],
+    [
+      'depthart',
+      's/f16',
+      '436a1accadf4030923e7ef4843381b78ab6be28a',
+      '3179481f642c9937f601d3911e4fc85f78668bf7f98eb832b2b4e124b00b0d4d',
+    ],
+  ]) {
+    const repository = `software-mansion/runntime-${model}`;
+    const url = `https://huggingface.co/${repository}/resolve/${sha}/${subpath}/model.safetensors`;
+    const path = join(directory, `${model}-${sha}.safetensors`);
+    let bytes;
+    try {
+      bytes = await readFile(path);
+    } catch {
+      console.log(`Downloading ${repository} at ${sha}`);
+      const weights = await fetch(url);
+      if (!weights.ok) throw new Error(`Weights download: ${weights.status}`);
+      bytes = Buffer.from(await weights.arrayBuffer());
+      await writeFile(path, bytes);
+    }
+    if (createHash('sha256').update(bytes).digest('hex') !== expectedHash)
+      throw new Error(`Cached weights do not match pinned checksum: ${path}`);
+    provenance.push({
+      model,
+      repository,
+      revision: sha,
+      url,
+      path,
+      bytes: bytes.length,
+      sha256: createHash('sha256').update(bytes).digest('hex'),
+    });
+  }
+  // Public example photograph, downloaded once and decoded outside all timers.
+  const imageUrl =
+    'https://raw.githubusercontent.com/ultralytics/ultralytics/eb3a9dad886878ada229611763e025b7cf3b6d03/ultralytics/assets/bus.jpg';
+  const imagePath = join(directory, 'bus.jpg');
+  let image;
+  try {
+    image = await readFile(imagePath);
+  } catch {
+    const response = await fetch(imageUrl);
+    if (!response.ok) throw new Error(`Image download: ${response.status}`);
+    image = Buffer.from(await response.arrayBuffer());
+    await writeFile(imagePath, image);
+  }
+  if (
+    createHash('sha256').update(image).digest('hex') !==
+    'c02019c4979c191eb739ddd944445ef408dad5679acab6fd520ef9d434bfbc63'
+  )
+    throw new Error('Benchmark photo checksum mismatch');
+  return {
+    directory,
+    internals,
+    provenance,
+    image: {
+      url: imageUrl,
+      path: imagePath,
+      bytes: image.length,
+      sha256: createHash('sha256').update(image).digest('hex'),
+    },
+  };
+}
diff --git a/utils/benchmark/specialized-results.json b/utils/benchmark/specialized-results.json
new file mode 100644
index 0000000..534b90a
--- /dev/null
+++ b/utils/benchmark/specialized-results.json
@@ -0,0 +1,5262 @@
+{
+  "baseline": "6049402",
+  "comparison": "Our previous production kernels versus our shape-specialized kernels. Ratios are baseline/candidate, not comparisons against ruNNtime or Hugging Face.",
+  "hardware": "Apple M1 Pro, Metal 3, Chrome 155; same device for each paired comparison.",
+  "inspiration": "ruNNtime small-channel direct convolution and narrow output tiling, adapted to our NCHW layout. No external runtime dependency or conversion passes.",
+  "routing": {
+    "rgb": "Dense 3x3, IC=3, OC=8..16, stride=2, dilation=1, padding=1, per-image output spatial size >=4096. Two pixels and four output channels per thread; filters staged once.",
+    "narrow": "Dense 3x3, IC divisible by four, OC=4..8, batch*output spatial size >=4096, symmetric stride 1 or 2, symmetric dilation 1 or 2, padding=dilation.",
+    "direct": "RGB or narrow with IC<=16 and dilation=1; dispatch dimension limits checked. Two neighboring stride-one outputs reuse a four-value input row when output width is even.",
+    "tile8": "Other eligible narrow convolutions use an 8x64 output tile rather than computing unused rows in a larger tile.",
+    "fallback": "Other shapes retain previous routing. Conditions use shapes and device dispatch limits, never GPU identifiers."
+  },
+  "modelImpact": {
+    "yolo": "Two eligible convolutions: RGB input 3->16, 3x3 stride2, and 16->8, 3x3 stride1 at 160x160. FP32 model-only improvement approximately 3%; FP16 approximately 2-4% in two runs.",
+    "depthart": "No eligible convolutions in the current model graph. Small timing differences are control noise, not an optimization claim.",
+    "scope": "Unchanged complete model graphs, submit+sync wall time. Excludes preprocessing, postprocessing, readback of final model outputs and rendering. No graph fusion or Winograd."
+  },
+  "validation": {
+    "raw": "27 geometries per precision per run; both precisions, two runs, identical input/weight/output GPU buffers, poisoned outputs, zero differing output bytes. Includes boundary, neighboring fallback, batch, stride and dilation cases.",
+    "models": "Both full model outputs byte-for-byte identical to archived baseline in both precisions in both runs, using original fixture inputs.",
+    "oracle": "24 additional CPU-reference tests across both precisions, including bias/no-bias, channel/spatial tails, batches, specialization thresholds and fallback routes.",
+    "bugFix": "Independent CPU oracle exposed an existing FP32 generic GEMM batch>1 gather bug. The batch index must be multiplied by IC. Fixed the gather to use its already-computed col_b_ic; added CPU regression coverage. Archived baseline comparisons avoid that incorrect batch>1 RGB case.",
+    "checks": "233 tests passed, 2 skipped; typecheck, lint, example build and benchmark build passed."
+  },
+  "rejected": "Four pixels per thread regressed FP32 RGB and some narrow geometries; retained two pixels per thread.",
+  "reproduce": "WGPU_KERNEL_BASELINE=6049402 WGPU_KERNEL_DATA=fractional npm run benchmark:specialized -- /tmp/specialized-run.json",
+  "method": "Record commands once. Eight warmups, 51 alternating baseline/candidate samples per case. Raw kernels repeat fixed dispatches and use GPU timestamps divided by repetition count; full graphs use submit+sync wall medians. Raw inputs use deterministic fractional values whose products exercise rounding; full models use original fixture inputs. Keep within-run paired ratios because GPU clocks vary between runs.",
+  "warning": "Measurements cover one adapter/browser; shape-based routing avoids GPU identifiers but does not establish universal speedups. Model timings exclude preprocessing, postprocessing and rendering.",
+  "summary": [
+    {
+      "run": 1,
+      "precision": "float32",
+      "case": [3, 16, 640, 640, 2, 1, 1],
+      "beforeMs": 0.4768124,
+      "afterMs": 0.2312338,
+      "speedup": 2.062035913434801,
+      "differentBytes": 0
+    },
+    {
+      "run": 1,
+      "precision": "float32",
+      "case": [16, 8, 160, 160, 1, 1, 1],
+      "beforeMs": 0.16030114285714286,
+      "afterMs": 0.071731,
+      "speedup": 2.2347540513465987,
+      "differentBytes": 0
+    },
+    {
+      "run": 1,
+      "precision": "float32",
+      "case": "yolo26n",
+      "beforeMs": 13.399999976158142,
+      "afterMs": 13,
+      "speedup": 1.0307692289352417,
+      "differentBytes": 0
+    },
+    {
+      "run": 1,
+      "precision": "float32",
+      "case": "depthart",
+      "beforeMs": 15.5,
+      "afterMs": 15.299999952316284,
+      "speedup": 1.013071898582159,
+      "differentBytes": 0
+    },
+    {
+      "run": 1,
+      "precision": "float16",
+      "case": [3, 16, 640, 640, 2, 1, 1],
+      "beforeMs": 0.541217,
+      "afterMs": 0.2265612,
+      "speedup": 2.3888335690312372,
+      "differentBytes": 0
+    },
+    {
+      "run": 1,
+      "precision": "float16",
+      "case": [16, 8, 160, 160, 1, 1, 1],
+      "beforeMs": 0.3369234285714286,
+      "afterMs": 0.14692042857142856,
+      "speedup": 2.2932374472868213,
+      "differentBytes": 0
+    },
+    {
+      "run": 1,
+      "precision": "float16",
+      "case": "yolo26n",
+      "beforeMs": 10.5,
+      "afterMs": 10.300000071525574,
+      "speedup": 1.0194174686490856,
+      "differentBytes": 0
+    },
+    {
+      "run": 1,
+      "precision": "float16",
+      "case": "depthart",
+      "beforeMs": 11.299999952316284,
+      "afterMs": 11.300000071525574,
+      "speedup": 0.9999999894505054,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float32",
+      "case": [3, 16, 640, 640, 2, 1, 1],
+      "beforeMs": 0.48400299999999996,
+      "afterMs": 0.2312526,
+      "speedup": 2.0929624142604233,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float32",
+      "case": [16, 8, 160, 160, 1, 1, 1],
+      "beforeMs": 0.3051738571428571,
+      "afterMs": 0.13903942857142856,
+      "speedup": 2.1948727801774623,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float32",
+      "case": "yolo26n",
+      "beforeMs": 13.5,
+      "afterMs": 13.100000023841858,
+      "speedup": 1.0305343492694767,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float32",
+      "case": "depthart",
+      "beforeMs": 15.199999928474426,
+      "afterMs": 15.299999952316284,
+      "speedup": 0.9934640507089205,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float16",
+      "case": [3, 16, 640, 640, 2, 1, 1],
+      "beforeMs": 0.4914868,
+      "afterMs": 0.2265396,
+      "speedup": 2.1695403364356607,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float16",
+      "case": [16, 8, 160, 160, 1, 1, 1],
+      "beforeMs": 0.21386585714285714,
+      "afterMs": 0.09279028571428571,
+      "speedup": 2.3048302470086153,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float16",
+      "case": "yolo26n",
+      "beforeMs": 10.600000023841858,
+      "afterMs": 10.200000047683716,
+      "speedup": 1.0392156837537443,
+      "differentBytes": 0
+    },
+    {
+      "run": 2,
+      "precision": "float16",
+      "case": "depthart",
+      "beforeMs": 11.300000071525574,
+      "afterMs": 11.399999976158142,
+      "speedup": 0.9912280785226573,
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+    }
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+      "baseline": "6049402",
+      "method": "Shape-specialized convolution candidates vs archived production baseline; see per-case bitwise parity and timing.",
+      "warning": "Measurements cover one adapter/browser; shape-based routing avoids GPU identifiers but does not establish universal speedups. Model timings exclude preprocessing, postprocessing and rendering.",
+      "results": [
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+          "precision": "float32",
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+      "warning": "Measurements cover one adapter/browser; shape-based routing avoids GPU identifiers but does not establish universal speedups. Model timings exclude preprocessing, postprocessing and rendering.",
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diff --git a/utils/benchmark/stage-control-results.json b/utils/benchmark/stage-control-results.json
new file mode 100644
index 0000000..6c01250
--- /dev/null
+++ b/utils/benchmark/stage-control-results.json
@@ -0,0 +1,18435 @@
+{
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+  "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
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+  ]
+}
diff --git a/utils/benchmark/stage-results.json b/utils/benchmark/stage-results.json
new file mode 100644
index 0000000..6cfbde0
--- /dev/null
+++ b/utils/benchmark/stage-results.json
@@ -0,0 +1,23527 @@
+{
+  "baseline": "e0caea9cbb2a131bb7d6bc8f128efd502497bcaf",
+  "method": "Single-page controlled stage ablation; shuffled paired rounds, same device and model inputs. GPU timestamp readback outside wall timer.",
+  "warning": "Do not attribute frame-minus-model time entirely to pre/post shaders: CPU handling, GPU copies, presentation, queue/browser scheduling and callback delivery also contribute. Forced detections include a small diagnostic setup dispatch in postprocessing.",
+  "results": [
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+      "precision": "float32",
+      "timestamps": true,
+      "warmups": 8,
+      "samples": 61,
+      "gpu": {
+        "vendor": "apple",
+        "architecture": "metal-3"
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+      "browser": "Mozilla/5.0 (Macintosh; Intel Mac OS X 10_15_7) AppleWebKit/537.36 (KHTML, like Gecko) HeadlessChrome/155.0.0.0 Safari/537.36",
+      "source": "Identical 1280x720 synthetic video frames at 30fps",
+      "method": "Single page/device; two recorded model contexts sharing input/output tensors; shuffled paired rounds. All shaders recorded outside measurement. Video callback wait excluded. Timestamp readback occurs after the wall timer. Canvas case matches example commands; wall time ends at GPU completion notification, not display scanout.",
+      "interpretation": "Paired deltas are medians of within-round differences, not differences of medians. They are not additive. wallMinusModelGpuDeltaMs subtracts the paired change in model GPU duration; it is a diagnostic residual, not an independently measured stage duration. Synthetic video and headless Chrome do not reproduce every camera/compositor cost.",
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