@@ -178,6 +178,9 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
178178 [IMX8MQ_RESET_A53_SOC_DBG_RESET ] = { SRC_A53RCR0 , BIT (20 ) },
179179 [IMX8MQ_RESET_A53_L2RESET ] = { SRC_A53RCR0 , BIT (21 ) },
180180 [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST ] = { SRC_M4RCR , BIT (0 ) },
181+ [IMX8MQ_RESET_SW_M4C_RST ] = { SRC_M4RCR , BIT (1 ) },
182+ [IMX8MQ_RESET_SW_M4P_RST ] = { SRC_M4RCR , BIT (2 ) },
183+ [IMX8MQ_RESET_M4_ENABLE ] = { SRC_M4RCR , BIT (3 ) },
181184 [IMX8MQ_RESET_OTG1_PHY_RESET ] = { SRC_USBOPHY1_RCR , BIT (0 ) },
182185 [IMX8MQ_RESET_OTG2_PHY_RESET ] = { SRC_USBOPHY2_RCR , BIT (0 ) },
183186 [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N ] = { SRC_MIPIPHY_RCR , BIT (1 ) },
@@ -238,6 +241,7 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
238241 case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N : /* fallthrough */
239242 case IMX8MQ_RESET_MIPI_DSI_RESET_N : /* fallthrough */
240243 case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N : /* fallthrough */
244+ case IMX8MQ_RESET_M4_ENABLE :
241245 value = assert ? 0 : bit ;
242246 break ;
243247 }
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