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Merge tag 'x86-irq-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 irq updates from Thomas Gleixner: "Surgery of the MSI interrupt handling to prepare the support of upcoming devices which require non-PCI based MSI handling: - Cleanup historical leftovers all over the place - Rework the code to utilize more core functionality - Wrap XEN PCI/MSI interrupts into an irqdomain to make irqdomain assignment to PCI devices possible. - Assign irqdomains to PCI devices at initialization time which allows to utilize the full functionality of hierarchical irqdomains. - Remove arch_.*_msi_irq() functions from X86 and utilize the irqdomain which is assigned to the device for interrupt management. - Make the arch_.*_msi_irq() support conditional on a config switch and let the last few users select it" * tag 'x86-irq-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits) PCI: MSI: Fix Kconfig dependencies for PCI_MSI_ARCH_FALLBACKS x86/apic/msi: Unbreak DMAR and HPET MSI iommu/amd: Remove domain search for PCI/MSI iommu/vt-d: Remove domain search for PCI/MSI[X] x86/irq: Make most MSI ops XEN private x86/irq: Cleanup the arch_*_msi_irqs() leftovers PCI/MSI: Make arch_.*_msi_irq[s] fallbacks selectable x86/pci: Set default irq domain in pcibios_add_device() iommm/amd: Store irq domain in struct device iommm/vt-d: Store irq domain in struct device x86/xen: Wrap XEN MSI management into irqdomain irqdomain/msi: Allow to override msi_domain_alloc/free_irqs() x86/xen: Consolidate XEN-MSI init x86/xen: Rework MSI teardown x86/xen: Make xen_msi_init() static and rename it to xen_hvm_msi_init() PCI/MSI: Provide pci_dev_has_special_msi_domain() helper PCI_vmd_Mark_VMD_irqdomain_with_DOMAIN_BUS_VMD_MSI irqdomain/msi: Provide DOMAIN_BUS_VMD_MSI x86/irq: Initialize PCI/MSI domain at PCI init time x86/pci: Reducde #ifdeffery in PCI init code ...
2 parents c457cc8 + 981aa1d commit cc73437

44 files changed

Lines changed: 597 additions & 523 deletions

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‎arch/ia64/Kconfig‎

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@@ -56,6 +56,7 @@ config IA64
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select NEED_DMA_MAP_STATE
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select NEED_SG_DMA_LENGTH
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select NUMA if !FLATMEM
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select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
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default y
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help
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The Itanium Processor Family is Intel's 64-bit successor to

‎arch/mips/Kconfig‎

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@@ -86,6 +86,7 @@ config MIPS
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select MODULES_USE_ELF_REL if MODULES
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select MODULES_USE_ELF_RELA if MODULES && 64BIT
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select PERF_USE_VMALLOC
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select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
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select RTC_LIB
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select SYSCTL_EXCEPTION_TRACE
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select VIRT_TO_BUS

‎arch/powerpc/Kconfig‎

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@@ -245,6 +245,7 @@ config PPC
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select OLD_SIGACTION if PPC32
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select OLD_SIGSUSPEND
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select PCI_DOMAINS if PCI
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select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
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select PCI_SYSCALL if PCI
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select PPC_DAWR if PPC64
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select RTC_LIB

‎arch/s390/Kconfig‎

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@@ -185,6 +185,7 @@ config S390
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select OLD_SIGSUSPEND3
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select PCI_DOMAINS if PCI
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select PCI_MSI if PCI
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select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
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select SPARSE_IRQ
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select SYSCTL_EXCEPTION_TRACE
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select THREAD_INFO_IN_TASK

‎arch/sparc/Kconfig‎

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@@ -43,6 +43,7 @@ config SPARC
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select GENERIC_STRNLEN_USER
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select MODULES_USE_ELF_RELA
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select PCI_SYSCALL if PCI
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select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
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select ODD_RT_SIGACTION
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select OLD_SIGSUSPEND
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select CPU_NO_EFFICIENT_FFS

‎arch/x86/include/asm/apic.h‎

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@@ -519,6 +519,14 @@ static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
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static inline void apic_smt_update(void) { }
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#endif
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struct msi_msg;
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#ifdef CONFIG_PCI_MSI
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void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg);
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#else
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# define x86_vector_msi_compose_msg NULL
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#endif
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extern void ioapic_zap_locks(void);
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#endif /* _ASM_X86_APIC_H */

‎arch/x86/include/asm/hw_irq.h‎

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@@ -36,61 +36,56 @@ struct msi_desc;
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enum irq_alloc_type {
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X86_IRQ_ALLOC_TYPE_IOAPIC = 1,
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X86_IRQ_ALLOC_TYPE_HPET,
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X86_IRQ_ALLOC_TYPE_MSI,
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X86_IRQ_ALLOC_TYPE_MSIX,
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X86_IRQ_ALLOC_TYPE_PCI_MSI,
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X86_IRQ_ALLOC_TYPE_PCI_MSIX,
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X86_IRQ_ALLOC_TYPE_DMAR,
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X86_IRQ_ALLOC_TYPE_UV,
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X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT,
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X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT,
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};
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struct ioapic_alloc_info {
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int pin;
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int node;
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u32 trigger : 1;
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u32 polarity : 1;
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u32 valid : 1;
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struct IO_APIC_route_entry *entry;
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};
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struct uv_alloc_info {
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int limit;
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int blade;
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unsigned long offset;
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char *name;
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};
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/**
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* irq_alloc_info - X86 specific interrupt allocation info
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* @type: X86 specific allocation type
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* @flags: Flags for allocation tweaks
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* @devid: Device ID for allocations
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* @hwirq: Associated hw interrupt number in the domain
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* @mask: CPU mask for vector allocation
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* @desc: Pointer to msi descriptor
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* @data: Allocation specific data
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*
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* @ioapic: IOAPIC specific allocation data
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* @uv: UV specific allocation data
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*/
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struct irq_alloc_info {
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enum irq_alloc_type type;
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u32 flags;
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const struct cpumask *mask; /* CPU mask for vector allocation */
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u32 devid;
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irq_hw_number_t hwirq;
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const struct cpumask *mask;
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struct msi_desc *desc;
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void *data;
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union {
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int unused;
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#ifdef CONFIG_HPET_TIMER
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struct {
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int hpet_id;
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int hpet_index;
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void *hpet_data;
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};
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#endif
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#ifdef CONFIG_PCI_MSI
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struct {
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struct pci_dev *msi_dev;
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irq_hw_number_t msi_hwirq;
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};
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#endif
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#ifdef CONFIG_X86_IO_APIC
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struct {
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int ioapic_id;
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int ioapic_pin;
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int ioapic_node;
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u32 ioapic_trigger : 1;
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u32 ioapic_polarity : 1;
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u32 ioapic_valid : 1;
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struct IO_APIC_route_entry *ioapic_entry;
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};
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#endif
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#ifdef CONFIG_DMAR_TABLE
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struct {
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int dmar_id;
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void *dmar_data;
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};
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#endif
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#ifdef CONFIG_X86_UV
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struct {
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int uv_limit;
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int uv_blade;
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unsigned long uv_offset;
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char *uv_name;
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};
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#endif
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#if IS_ENABLED(CONFIG_VMD)
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struct {
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struct msi_desc *desc;
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};
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#endif
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struct ioapic_alloc_info ioapic;
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struct uv_alloc_info uv;
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};
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};
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‎arch/x86/include/asm/irq_remapping.h‎

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@@ -44,8 +44,6 @@ extern int irq_remapping_reenable(int);
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extern int irq_remap_enable_fault_handling(void);
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extern void panic_if_irq_remap(const char *msg);
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extern struct irq_domain *
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irq_remapping_get_ir_irq_domain(struct irq_alloc_info *info);
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extern struct irq_domain *
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irq_remapping_get_irq_domain(struct irq_alloc_info *info);
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{
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}
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static inline struct irq_domain *
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irq_remapping_get_ir_irq_domain(struct irq_alloc_info *info)
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{
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return NULL;
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}
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static inline struct irq_domain *
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irq_remapping_get_irq_domain(struct irq_alloc_info *info)
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{

‎arch/x86/include/asm/irqdomain.h‎

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@@ -51,9 +51,13 @@ extern int mp_irqdomain_ioapic_idx(struct irq_domain *domain);
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#endif /* CONFIG_X86_IO_APIC */
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#ifdef CONFIG_PCI_MSI
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extern void arch_init_msi_domain(struct irq_domain *domain);
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void x86_create_pci_msi_domain(void);
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struct irq_domain *native_create_pci_msi_domain(void);
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extern struct irq_domain *x86_pci_msi_default_domain;
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#else
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static inline void arch_init_msi_domain(struct irq_domain *domain) { }
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static inline void x86_create_pci_msi_domain(void) { }
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#define native_create_pci_msi_domain NULL
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#define x86_pci_msi_default_domain NULL
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#endif
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#endif

‎arch/x86/include/asm/mpspec.h‎

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@@ -67,21 +67,11 @@ static inline void find_smp_config(void)
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#ifdef CONFIG_X86_MPPARSE
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extern void e820__memblock_alloc_reserved_mpc_new(void);
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extern int enable_update_mptable;
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extern int default_mpc_apic_id(struct mpc_cpu *m);
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extern void default_smp_read_mpc_oem(struct mpc_table *mpc);
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# ifdef CONFIG_X86_IO_APIC
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extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str);
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# else
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# define default_mpc_oem_bus_info NULL
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# endif
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extern void default_find_smp_config(void);
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extern void default_get_smp_config(unsigned int early);
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#else
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static inline void e820__memblock_alloc_reserved_mpc_new(void) { }
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#define enable_update_mptable 0
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#define default_mpc_apic_id NULL
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#define default_smp_read_mpc_oem NULL
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#define default_mpc_oem_bus_info NULL
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#define default_find_smp_config x86_init_noop
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#define default_get_smp_config x86_init_uint_noop
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#endif

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