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PeikanTsaiMarc Zyngier
PeikanTsai
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Marc Zyngier
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irqchip/irq-mst: Add MStar interrupt controller support
Add MStar interrupt controller support using hierarchy irq domain. Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Daniel Palmer <daniel@thingy.jp> Link: https://lore.kernel.org/r/20200902063344.1852-2-mark-pk.tsai@mediatek.com
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‎MAINTAINERS‎

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@@ -11771,6 +11771,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
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T: git git://linuxtv.org/anttip/media_tree.git
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F: drivers/media/usb/msi2500/
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MSTAR INTERRUPT CONTROLLER DRIVER
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M: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
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M: Daniel Palmer <daniel@thingy.jp>
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S: Maintained
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F: Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
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F: drivers/irqchip/irq-mst-intc.c
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MSYSTEMS DISKONCHIP G3 MTD DRIVER
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M: Robert Jarzmik <robert.jarzmik@free.fr>
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L: linux-mtd@lists.infradead.org

‎drivers/irqchip/Kconfig‎

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@@ -571,4 +571,12 @@ config LOONGSON_PCH_MSI
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help
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Support for the Loongson PCH MSI Controller.
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config MST_IRQ
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bool "MStar Interrupt Controller"
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default ARCH_MEDIATEK
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Support MStar Interrupt Controller.
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endmenu

‎drivers/irqchip/Makefile‎

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@@ -111,3 +111,4 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
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obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
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obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
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obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
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obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o

‎drivers/irqchip/irq-mst-intc.c‎

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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define INTC_MASK 0x0
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#define INTC_EOI 0x20
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struct mst_intc_chip_data {
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raw_spinlock_t lock;
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unsigned int irq_start, nr_irqs;
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void __iomem *base;
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bool no_eoi;
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};
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static void mst_set_irq(struct irq_data *d, u32 offset)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
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u16 val, mask;
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unsigned long flags;
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mask = 1 << (hwirq % 16);
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offset += (hwirq / 16) * 4;
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raw_spin_lock_irqsave(&cd->lock, flags);
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val = readw_relaxed(cd->base + offset) | mask;
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writew_relaxed(val, cd->base + offset);
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raw_spin_unlock_irqrestore(&cd->lock, flags);
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}
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static void mst_clear_irq(struct irq_data *d, u32 offset)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
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u16 val, mask;
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unsigned long flags;
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mask = 1 << (hwirq % 16);
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offset += (hwirq / 16) * 4;
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raw_spin_lock_irqsave(&cd->lock, flags);
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val = readw_relaxed(cd->base + offset) & ~mask;
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writew_relaxed(val, cd->base + offset);
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raw_spin_unlock_irqrestore(&cd->lock, flags);
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}
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static void mst_intc_mask_irq(struct irq_data *d)
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{
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mst_set_irq(d, INTC_MASK);
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irq_chip_mask_parent(d);
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}
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static void mst_intc_unmask_irq(struct irq_data *d)
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{
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mst_clear_irq(d, INTC_MASK);
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irq_chip_unmask_parent(d);
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}
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static void mst_intc_eoi_irq(struct irq_data *d)
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{
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struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
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if (!cd->no_eoi)
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mst_set_irq(d, INTC_EOI);
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irq_chip_eoi_parent(d);
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}
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static struct irq_chip mst_intc_chip = {
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.name = "mst-intc",
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.irq_mask = mst_intc_mask_irq,
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.irq_unmask = mst_intc_unmask_irq,
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.irq_eoi = mst_intc_eoi_irq,
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.irq_get_irqchip_state = irq_chip_get_parent_state,
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.irq_set_irqchip_state = irq_chip_set_parent_state,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
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.irq_set_type = irq_chip_set_type_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.flags = IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE |
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IRQCHIP_MASK_ON_SUSPEND,
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};
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static int mst_intc_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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struct mst_intc_chip_data *cd = d->host_data;
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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if (fwspec->param[1] >= cd->nr_irqs)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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return -EINVAL;
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}
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static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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int i;
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irq_hw_number_t hwirq;
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struct irq_fwspec parent_fwspec, *fwspec = data;
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struct mst_intc_chip_data *cd = domain->host_data;
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/* Not GIC compliant */
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0])
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return -EINVAL;
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hwirq = fwspec->param[1];
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&mst_intc_chip,
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domain->host_data);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param[1] = cd->irq_start + hwirq;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
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}
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static const struct irq_domain_ops mst_intc_domain_ops = {
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.translate = mst_intc_domain_translate,
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.alloc = mst_intc_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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int __init
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mst_intc_of_init(struct device_node *dn, struct device_node *parent)
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{
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struct irq_domain *domain, *domain_parent;
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struct mst_intc_chip_data *cd;
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u32 irq_start, irq_end;
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domain_parent = irq_find_host(parent);
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if (!domain_parent) {
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pr_err("mst-intc: interrupt-parent not found\n");
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return -EINVAL;
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}
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if (of_property_read_u32_index(dn, "mstar,irqs-map-range", 0, &irq_start) ||
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of_property_read_u32_index(dn, "mstar,irqs-map-range", 1, &irq_end))
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return -EINVAL;
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cd = kzalloc(sizeof(*cd), GFP_KERNEL);
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if (!cd)
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return -ENOMEM;
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cd->base = of_iomap(dn, 0);
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if (!cd->base) {
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kfree(cd);
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return -ENOMEM;
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}
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cd->no_eoi = of_property_read_bool(dn, "mstar,intc-no-eoi");
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raw_spin_lock_init(&cd->lock);
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cd->irq_start = irq_start;
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cd->nr_irqs = irq_end - irq_start + 1;
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domain = irq_domain_add_hierarchy(domain_parent, 0, cd->nr_irqs, dn,
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&mst_intc_domain_ops, cd);
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if (!domain) {
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iounmap(cd->base);
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kfree(cd);
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return -ENOMEM;
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}
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return 0;
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}
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IRQCHIP_DECLARE(mst_intc, "mstar,mst-intc", mst_intc_of_init);

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