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mtd: rawnand: fsmc: Move the ECC initialization to ->attach_chip()
The probe function is only supposed to initialize the controller hardware but not the ECC engine. Indeed, we don't know anything about the NAND chip(s) at this stage. Let's move the logic initializing the ECC engine, even pretty simple, to the ->attach_chip() hook which gets called during nand_scan() routine, after the NAND chip discovery. As the previously mentioned logic is supposed to parse the DT for us, it is likely that the chip->ecc.* entries be overwritten. So let's avoid this by moving these lines to ->attach_chip(). Fixes: d7157ff ("mtd: rawnand: Use the ECC framework user input parsing bits") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
1 parent 7f4ea03 commit 98591a6

1 file changed

Lines changed: 15 additions & 15 deletions

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drivers/mtd/nand/raw/fsmc_nand.c

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -880,6 +880,20 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
880880
struct mtd_info *mtd = nand_to_mtd(nand);
881881
struct fsmc_nand_data *host = nand_to_fsmc(nand);
882882

883+
if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
884+
nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
885+
886+
if (!nand->ecc.size)
887+
nand->ecc.size = 512;
888+
889+
if (AMBA_REV_BITS(host->pid) >= 8) {
890+
nand->ecc.read_page = fsmc_read_page_hwecc;
891+
nand->ecc.calculate = fsmc_read_hwecc_ecc4;
892+
nand->ecc.correct = fsmc_bch8_correct_data;
893+
nand->ecc.bytes = 13;
894+
nand->ecc.strength = 8;
895+
}
896+
883897
if (AMBA_REV_BITS(host->pid) >= 8) {
884898
switch (mtd->oobsize) {
885899
case 16:
@@ -905,6 +919,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
905919
dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
906920
nand->ecc.calculate = fsmc_read_hwecc_ecc1;
907921
nand->ecc.correct = nand_correct_data;
922+
nand->ecc.hwctl = fsmc_enable_hwecc;
908923
nand->ecc.bytes = 3;
909924
nand->ecc.strength = 1;
910925
nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
@@ -1055,13 +1070,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
10551070

10561071
mtd->dev.parent = &pdev->dev;
10571072

1058-
/*
1059-
* Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
1060-
* can overwrite this value if the DT provides a different value.
1061-
*/
1062-
nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1063-
nand->ecc.hwctl = fsmc_enable_hwecc;
1064-
nand->ecc.size = 512;
10651073
nand->badblockbits = 7;
10661074

10671075
if (host->mode == USE_DMA_ACCESS) {
@@ -1084,14 +1092,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
10841092
nand->options |= NAND_KEEP_TIMINGS;
10851093
}
10861094

1087-
if (AMBA_REV_BITS(host->pid) >= 8) {
1088-
nand->ecc.read_page = fsmc_read_page_hwecc;
1089-
nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1090-
nand->ecc.correct = fsmc_bch8_correct_data;
1091-
nand->ecc.bytes = 13;
1092-
nand->ecc.strength = 8;
1093-
}
1094-
10951095
nand_controller_init(&host->base);
10961096
host->base.ops = &fsmc_nand_controller_ops;
10971097
nand->controller = &host->base;

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