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Merge tag 'irqchip-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier: Core changes: - Allow irq retriggering to follow a hierarchy - Allow interrupt hierarchies to be trimmed at allocation time - Allow interrupts to be hidden from /proc/interrupts (IPIs) - Introduce stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER - New per-cpu IPI handling flow Architecture changes: - Move arm/arm64 IPI handling to the core interrupt code, removing the home brewed accounting Driver updates: - New driver for the MStar (and more recently Mediatek) platforms - New driver for the Actions Owl SIRQ controller - New driver for the TI PRUSS infrastructure - Wake-up support for the Qualcomm PDC controller - Primary interrupt controller support for the Designware APB ICTL - Convert the IPI code for GIC, GICv3, hip04, armada-270-xp and bcm2836 to using standard interrupts - Improve GICv3 pseudo-NMI support to deal with both non-secure and secure priorities on arm64 - Convert the GIC/GICv3 drivers to using HW-based irq retrigger - A sprinkling of dev_err_probe() conversion - A set of NVIDIA Tegra fixes for interrupt hierarchy corruption - A reset fix for the Loongson HTVEC driver - A couple of error handling fixes in the TI SCI drivers
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Lines changed: 2761 additions & 613 deletions

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‎Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Actions Semi Owl SoCs SIRQ interrupt controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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- Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
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description: |
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This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
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and S900) and provides support for handling up to 3 external interrupt lines.
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properties:
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compatible:
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enum:
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- actions,s500-sirq
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- actions,s700-sirq
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- actions,s900-sirq
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the input IRQ number, between 0 and 2, while the second
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cell is the trigger type as defined in interrupt.txt in this directory.
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'interrupts':
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description: |
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Contains the GIC SPI IRQs mapped to the external interrupt lines.
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They shall be specified sequentially from output 0 to 2.
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minItems: 3
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maxItems: 3
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- 'interrupts'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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sirq: interrupt-controller@b01b0200 {
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compatible = "actions,s500-sirq";
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reg = <0xb01b0200 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
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};
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...

‎Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MStar Interrupt Controller
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maintainers:
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- Mark-PK Tsai <mark-pk.tsai@mediatek.com>
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description: |+
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MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
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interrupt controllers that routes interrupts to the GIC.
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The HW block exposes a number of interrupt controllers, each
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can support up to 64 interrupts.
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properties:
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compatible:
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const: mstar,mst-intc
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interrupt-controller: true
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"#interrupt-cells":
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const: 3
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description: |
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Use the same format as specified by GIC in arm,gic.yaml.
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reg:
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maxItems: 1
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mstar,irqs-map-range:
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description: |
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The range <start, end> of parent interrupt controller's interrupt
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lines that are hardwired to mstar interrupt controller.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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minItems: 2
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maxItems: 2
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mstar,intc-no-eoi:
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description:
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Mark this controller has no End Of Interrupt(EOI) implementation.
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type: boolean
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required:
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- compatible
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- reg
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- mstar,irqs-map-range
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additionalProperties: false
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examples:
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- |
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mst_intc0: interrupt-controller@1f2032d0 {
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compatible = "mstar,mst-intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x1f2032d0 0x30>;
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mstar,irqs-map-range = <0 63>;
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};
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...

‎Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt‎

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@@ -2,14 +2,17 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
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Synopsys DesignWare provides interrupt controller IP for APB known as
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dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
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APB bus, e.g. Marvell Armada 1500.
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APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
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controller in some SoCs, e.g. Hisilicon SD5203.
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Required properties:
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- compatible: shall be "snps,dw-apb-ictl"
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- reg: physical base address of the controller and length of memory mapped
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region starting with ENABLE_LOW register
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
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Additional required property when it's used as secondary interrupt controller:
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- interrupts: interrupt reference to primary interrupt controller
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The interrupt sources map to the corresponding bits in the interrupt
@@ -21,6 +24,7 @@ registers, i.e.
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- (optional) fast interrupts start at 64.
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Example:
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/* dw_apb_ictl is used as secondary interrupt controller */
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aic: interrupt-controller@3000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x3000 0xc00>;
@@ -29,3 +33,11 @@ Example:
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* dw_apb_ictl is used as primary interrupt controller */
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vic: interrupt-controller@10130000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x10130000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};

‎Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI PRU-ICSS Local Interrupt Controller
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maintainers:
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- Suman Anna <s-anna@ti.com>
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description: |
13+
Each PRU-ICSS has a single interrupt controller instance that is common
14+
to all the PRU cores. Most interrupt controllers can route 64 input events
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which are then mapped to 10 possible output interrupts through two levels
16+
of mapping. The input events can be triggered by either the PRUs and/or
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various other PRUSS internal and external peripherals. The first 2 output
18+
interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
19+
remaining 8 (2 through 9) connected to external interrupt controllers
20+
including the MPU and/or other PRUSS instances, DSPs or devices.
21+
22+
The property "ti,irqs-reserved" is used for denoting the connection
23+
differences on the output interrupts 2 through 9. If this property is not
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defined, it implies that all the PRUSS INTC output interrupts 2 through 9
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(host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
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controller.
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28+
The K3 family of SoCs can handle 160 input events that can be mapped to 20
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different possible output interrupts. The additional output interrupts (10
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through 19) are connected to new sub-modules within the ICSSG instances.
31+
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This interrupt-controller node should be defined as a child node of the
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corresponding PRUSS node. The node should be named "interrupt-controller".
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properties:
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compatible:
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enum:
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- ti,pruss-intc
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- ti,icssg-intc
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description: |
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Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
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AM335x family of SoCs,
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AM437x family of SoCs,
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AM57xx family of SoCs
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66AK2G family of SoCs
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Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs
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reg:
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maxItems: 1
50+
51+
interrupts:
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minItems: 1
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maxItems: 8
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description: |
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All the interrupts generated towards the main host processor in the SoC.
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A shared interrupt can be skipped if the desired destination and usage is
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by a different processor/device.
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interrupt-names:
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minItems: 1
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maxItems: 8
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items:
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pattern: host_intr[0-7]
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description: |
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Should use one of the above names for each valid host event interrupt
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connected to Arm interrupt controller, the name should match the
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corresponding host event interrupt number.
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interrupt-controller: true
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"#interrupt-cells":
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const: 3
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description: |
74+
Client users shall use the PRU System event number (the interrupt source
75+
that the client is interested in) [cell 1], PRU channel [cell 2] and PRU
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host_event (target) [cell 3] as the value of the interrupts property in
77+
their node. The system events can be mapped to some output host
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interrupts through 2 levels of many-to-one mapping i.e. events to channel
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mapping and channels to host interrupts so through this property entire
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mapping is provided.
81+
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ti,irqs-reserved:
83+
$ref: /schemas/types.yaml#definitions/uint8
84+
description: |
85+
Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
86+
output interrupts 2 through 9) that are not connected to the Arm interrupt
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controller or are shared and used by other devices or processors in the
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SoC. Define this property when any of 8 interrupts should not be handled
89+
by Arm interrupt controller.
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Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt
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connected to MPU
92+
- AM65x and J721E SoCs have "host_intr5", "host_intr6" and
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"host_intr7" interrupts connected to MPU, and other ICSSG
94+
instances.
95+
96+
required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- interrupt-controller
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- "#interrupt-cells"
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104+
additionalProperties: false
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examples:
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- |
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/* AM33xx PRU-ICSS */
109+
pruss: pruss@0 {
110+
compatible = "ti,am3356-pruss";
111+
reg = <0x0 0x80000>;
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#address-cells = <1>;
113+
#size-cells = <1>;
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ranges;
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116+
pruss_intc: interrupt-controller@20000 {
117+
compatible = "ti,pruss-intc";
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reg = <0x20000 0x2000>;
119+
interrupts = <20 21 22 23 24 25 26 27>;
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interrupt-names = "host_intr0", "host_intr1",
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"host_intr2", "host_intr3",
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"host_intr4", "host_intr5",
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"host_intr6", "host_intr7";
124+
interrupt-controller;
125+
#interrupt-cells = <3>;
126+
};
127+
};
128+
129+
- |
130+
131+
/* AM4376 PRU-ICSS */
132+
#include <dt-bindings/interrupt-controller/arm-gic.h>
133+
pruss@0 {
134+
compatible = "ti,am4376-pruss";
135+
reg = <0x0 0x40000>;
136+
#address-cells = <1>;
137+
#size-cells = <1>;
138+
ranges;
139+
140+
interrupt-controller@20000 {
141+
compatible = "ti,pruss-intc";
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reg = <0x20000 0x2000>;
143+
interrupt-controller;
144+
#interrupt-cells = <3>;
145+
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
148+
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
150+
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
152+
interrupt-names = "host_intr0", "host_intr1",
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"host_intr2", "host_intr3",
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"host_intr4",
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"host_intr6", "host_intr7";
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ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
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};
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};

‎MAINTAINERS‎

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@@ -1525,6 +1525,7 @@ F: Documentation/devicetree/bindings/arm/actions.yaml
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F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
15261526
F: Documentation/devicetree/bindings/dma/owl-dma.txt
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F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
1528+
F: Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
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F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
15291530
F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
15301531
F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
@@ -1536,6 +1537,7 @@ F: drivers/clk/actions/
15361537
F: drivers/clocksource/timer-owl*
15371538
F: drivers/dma/owl-dma.c
15381539
F: drivers/i2c/busses/i2c-owl.c
1540+
F: drivers/irqchip/irq-owl-sirq.c
15391541
F: drivers/mmc/host/owl-mmc.c
15401542
F: drivers/pinctrl/actions/*
15411543
F: drivers/soc/actions/
@@ -11779,6 +11781,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
1177911781
T: git git://linuxtv.org/anttip/media_tree.git
1178011782
F: drivers/media/usb/msi2500/
1178111783

11784+
MSTAR INTERRUPT CONTROLLER DRIVER
11785+
M: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
11786+
M: Daniel Palmer <daniel@thingy.jp>
11787+
S: Maintained
11788+
F: Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
11789+
F: drivers/irqchip/irq-mst-intc.c
11790+
1178211791
MSYSTEMS DISKONCHIP G3 MTD DRIVER
1178311792
M: Robert Jarzmik <robert.jarzmik@free.fr>
1178411793
L: linux-mtd@lists.infradead.org

‎arch/arm/Kconfig‎

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@@ -49,6 +49,7 @@ config ARM
4949
select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
5050
select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
5151
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52+
select GENERIC_IRQ_IPI if SMP
5253
select GENERIC_CPU_AUTOPROBE
5354
select GENERIC_EARLY_IOREMAP
5455
select GENERIC_IDLE_POLL_SETUP

‎arch/arm/include/asm/hardirq.h‎

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66
#include <linux/threads.h>
77
#include <asm/irq.h>
88

9-
/* number of IPIS _not_ including IPI_CPU_BACKTRACE */
10-
#define NR_IPI 7
11-
129
typedef struct {
1310
unsigned int __softirq_pending;
14-
#ifdef CONFIG_SMP
15-
unsigned int ipi_irqs[NR_IPI];
16-
#endif
1711
} ____cacheline_aligned irq_cpustat_t;
1812

1913
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
2014

21-
#define __inc_irq_stat(cpu, member) __IRQ_STAT(cpu, member)++
22-
#define __get_irq_stat(cpu, member) __IRQ_STAT(cpu, member)
23-
24-
#ifdef CONFIG_SMP
25-
u64 smp_irq_stat_cpu(unsigned int cpu);
26-
#else
27-
#define smp_irq_stat_cpu(cpu) 0
28-
#endif
29-
30-
#define arch_irq_stat_cpu smp_irq_stat_cpu
31-
3215
#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
3316

3417
#endif /* __ASM_HARDIRQ_H */

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