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33 | 33 | #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) |
34 | 34 | #define UARTA_7216 UARTA_7278 |
35 | 35 | #define UARTA_72164 UARTA_7278 |
| 36 | +#define UARTA_72165 UARTA_7278 |
36 | 37 | #define UARTA_7364 REG_PHYS_ADDR(0x40b000) |
37 | 38 | #define UARTA_7366 UARTA_7364 |
38 | 39 | #define UARTA_74371 REG_PHYS_ADDR(0x406b00) |
@@ -86,17 +87,18 @@ ARM_BE8( rev \rv, \rv ) |
86 | 87 | 20: checkuart(\rp, \rv, 0x33900000, 3390) |
87 | 88 | 21: checkuart(\rp, \rv, 0x72160000, 7216) |
88 | 89 | 22: checkuart(\rp, \rv, 0x07216400, 72164) |
89 | | -23: checkuart(\rp, \rv, 0x72500000, 7250) |
90 | | -24: checkuart(\rp, \rv, 0x72550000, 7255) |
91 | | -25: checkuart(\rp, \rv, 0x72600000, 7260) |
92 | | -26: checkuart(\rp, \rv, 0x72680000, 7268) |
93 | | -27: checkuart(\rp, \rv, 0x72710000, 7271) |
94 | | -28: checkuart(\rp, \rv, 0x72780000, 7278) |
95 | | -29: checkuart(\rp, \rv, 0x73640000, 7364) |
96 | | -30: checkuart(\rp, \rv, 0x73660000, 7366) |
97 | | -31: checkuart(\rp, \rv, 0x07437100, 74371) |
98 | | -32: checkuart(\rp, \rv, 0x74390000, 7439) |
99 | | -33: checkuart(\rp, \rv, 0x74450000, 7445) |
| 90 | +23: checkuart(\rp, \rv, 0x07216500, 72165) |
| 91 | +24: checkuart(\rp, \rv, 0x72500000, 7250) |
| 92 | +25: checkuart(\rp, \rv, 0x72550000, 7255) |
| 93 | +26: checkuart(\rp, \rv, 0x72600000, 7260) |
| 94 | +27: checkuart(\rp, \rv, 0x72680000, 7268) |
| 95 | +28: checkuart(\rp, \rv, 0x72710000, 7271) |
| 96 | +29: checkuart(\rp, \rv, 0x72780000, 7278) |
| 97 | +30: checkuart(\rp, \rv, 0x73640000, 7364) |
| 98 | +31: checkuart(\rp, \rv, 0x73660000, 7366) |
| 99 | +32: checkuart(\rp, \rv, 0x07437100, 74371) |
| 100 | +33: checkuart(\rp, \rv, 0x74390000, 7439) |
| 101 | +34: checkuart(\rp, \rv, 0x74450000, 7445) |
100 | 102 |
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101 | 103 | /* No valid UART found */ |
102 | 104 | 90: mov \rp, #0 |
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