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airliedairlied
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Merge tag 'amd-drm-fixes-5.10-2020-10-21' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-fixes-5.10-2020-10-21: amdgpu: - Sienna Cichlid fixes - MST manager resource leak fix - GPU reset fix amdkfd: - Luxmark fix for Navi1x Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201022040322.4183-1-alexander.deucher@amd.com
2 parents fea456d + 687e79c commit 3f31ded

13 files changed

Lines changed: 187 additions & 31 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4625,7 +4625,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
46254625
retry: /* Rest of adevs pre asic reset from XGMI hive. */
46264626
list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
46274627
r = amdgpu_device_pre_asic_reset(tmp_adev,
4628-
NULL,
4628+
(tmp_adev == adev) ? job : NULL,
46294629
&need_full_reset);
46304630
/*TODO Should we stop ?*/
46314631
if (r) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,8 @@ static int psp_sw_fini(void *handle)
208208
adev->psp.ta_fw = NULL;
209209
}
210210

211-
if (adev->asic_type == CHIP_NAVI10)
211+
if (adev->asic_type == CHIP_NAVI10 ||
212+
adev->asic_type == CHIP_SIENNA_CICHLID)
212213
psp_sysfs_fini(adev);
213214

214215
return 0;
@@ -1750,6 +1751,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
17501751
case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
17511752
*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
17521753
break;
1754+
case AMDGPU_UCODE_ID_RLC_IRAM:
1755+
*type = GFX_FW_TYPE_RLC_IRAM;
1756+
break;
1757+
case AMDGPU_UCODE_ID_RLC_DRAM:
1758+
*type = GFX_FW_TYPE_RLC_DRAM_BOOT;
1759+
break;
17531760
case AMDGPU_UCODE_ID_SMC:
17541761
*type = GFX_FW_TYPE_SMU;
17551762
break;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1986,7 +1986,8 @@ static int amdgpu_ras_check_asic_type(struct amdgpu_device *adev)
19861986
{
19871987
if (adev->asic_type != CHIP_VEGA10 &&
19881988
adev->asic_type != CHIP_VEGA20 &&
1989-
adev->asic_type != CHIP_ARCTURUS)
1989+
adev->asic_type != CHIP_ARCTURUS &&
1990+
adev->asic_type != CHIP_SIENNA_CICHLID)
19901991
return 1;
19911992
else
19921993
return 0;
@@ -2030,7 +2031,6 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
20302031

20312032
*supported = amdgpu_ras_enable == 0 ?
20322033
0 : *hw_supported & amdgpu_ras_mask;
2033-
20342034
adev->ras_features = *supported;
20352035
}
20362036

‎drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,12 +168,16 @@ struct amdgpu_rlc {
168168
u32 save_restore_list_cntl_size_bytes;
169169
u32 save_restore_list_gpm_size_bytes;
170170
u32 save_restore_list_srm_size_bytes;
171+
u32 rlc_iram_ucode_size_bytes;
172+
u32 rlc_dram_ucode_size_bytes;
171173

172174
u32 *register_list_format;
173175
u32 *register_restore;
174176
u8 *save_restore_list_cntl;
175177
u8 *save_restore_list_gpm;
176178
u8 *save_restore_list_srm;
179+
u8 *rlc_iram_ucode;
180+
u8 *rlc_dram_ucode;
177181

178182
bool is_rlc_v2_1;
179183

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -500,6 +500,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
500500
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
501501
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
502502
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
503+
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&
504+
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&
503505
ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
504506
ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
505507
ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
@@ -556,6 +558,14 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
556558
ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
557559
memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
558560
ucode->ucode_size);
561+
} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {
562+
ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
563+
memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,
564+
ucode->ucode_size);
565+
} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {
566+
ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
567+
memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,
568+
ucode->ucode_size);
559569
} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
560570
ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
561571
memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,15 @@ struct rlc_firmware_header_v2_1 {
222222
uint32_t save_restore_list_srm_offset_bytes;
223223
};
224224

225+
/* version_major=2, version_minor=1 */
226+
struct rlc_firmware_header_v2_2 {
227+
struct rlc_firmware_header_v2_1 v2_1;
228+
uint32_t rlc_iram_ucode_size_bytes;
229+
uint32_t rlc_iram_ucode_offset_bytes;
230+
uint32_t rlc_dram_ucode_size_bytes;
231+
uint32_t rlc_dram_ucode_offset_bytes;
232+
};
233+
225234
/* version_major=1, version_minor=0 */
226235
struct sdma_firmware_header_v1_0 {
227236
struct common_firmware_header header;
@@ -339,6 +348,8 @@ enum AMDGPU_UCODE_ID {
339348
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
340349
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
341350
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
351+
AMDGPU_UCODE_ID_RLC_IRAM,
352+
AMDGPU_UCODE_ID_RLC_DRAM,
342353
AMDGPU_UCODE_ID_RLC_G,
343354
AMDGPU_UCODE_ID_STORAGE,
344355
AMDGPU_UCODE_ID_SMC,

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 105 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,22 @@
112112
#define mmCP_HYP_ME_UCODE_DATA 0x5817
113113
#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
114114

115+
//CC_GC_SA_UNIT_DISABLE
116+
#define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
117+
#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
118+
#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
119+
#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
120+
//GC_USER_SA_UNIT_DISABLE
121+
#define mmGC_USER_SA_UNIT_DISABLE 0x0fea
122+
#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
123+
#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
124+
#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
125+
//PA_SC_ENHANCE_3
126+
#define mmPA_SC_ENHANCE_3 0x1085
127+
#define mmPA_SC_ENHANCE_3_BASE_IDX 0
128+
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
129+
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
130+
115131
MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
116132
MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
117133
MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -3091,6 +3107,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] =
30913107
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
30923108
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
30933109
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3110+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
30943111
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
30953112
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
30963113
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
@@ -3188,6 +3205,8 @@ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
31883205
static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
31893206
static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
31903207
static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3208+
static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3209+
static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
31913210

31923211
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
31933212
{
@@ -3586,6 +3605,17 @@ static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
35863605
le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
35873606
}
35883607

3608+
static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3609+
{
3610+
const struct rlc_firmware_header_v2_2 *rlc_hdr;
3611+
3612+
rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3613+
adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3614+
adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3615+
adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3616+
adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3617+
}
3618+
35893619
static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
35903620
{
35913621
bool ret = false;
@@ -3701,8 +3731,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
37013731
rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
37023732
version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
37033733
version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3704-
if (version_major == 2 && version_minor == 1)
3705-
adev->gfx.rlc.is_rlc_v2_1 = true;
37063734

37073735
adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
37083736
adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
@@ -3744,8 +3772,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
37443772
for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
37453773
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
37463774

3747-
if (adev->gfx.rlc.is_rlc_v2_1)
3748-
gfx_v10_0_init_rlc_ext_microcode(adev);
3775+
if (version_major == 2) {
3776+
if (version_minor >= 1)
3777+
gfx_v10_0_init_rlc_ext_microcode(adev);
3778+
if (version_minor == 2)
3779+
gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3780+
}
37493781
}
37503782

37513783
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
@@ -3806,8 +3838,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
38063838
adev->firmware.fw_size +=
38073839
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
38083840
}
3809-
if (adev->gfx.rlc.is_rlc_v2_1 &&
3810-
adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3841+
if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
38113842
adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
38123843
adev->gfx.rlc.save_restore_list_srm_size_bytes) {
38133844
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
@@ -3827,6 +3858,21 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
38273858
info->fw = adev->gfx.rlc_fw;
38283859
adev->firmware.fw_size +=
38293860
ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3861+
3862+
if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
3863+
adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
3864+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
3865+
info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
3866+
info->fw = adev->gfx.rlc_fw;
3867+
adev->firmware.fw_size +=
3868+
ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
3869+
3870+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
3871+
info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
3872+
info->fw = adev->gfx.rlc_fw;
3873+
adev->firmware.fw_size +=
3874+
ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
3875+
}
38303876
}
38313877

38323878
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
@@ -4536,12 +4582,17 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
45364582
int i, j;
45374583
u32 data;
45384584
u32 active_rbs = 0;
4585+
u32 bitmap;
45394586
u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
45404587
adev->gfx.config.max_sh_per_se;
45414588

45424589
mutex_lock(&adev->grbm_idx_mutex);
45434590
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
45444591
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4592+
bitmap = i * adev->gfx.config.max_sh_per_se + j;
4593+
if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4594+
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4595+
continue;
45454596
gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
45464597
data = gfx_v10_0_get_rb_active_bitmap(adev);
45474598
active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
@@ -6950,6 +7001,9 @@ static int gfx_v10_0_hw_init(void *handle)
69507001
if (r)
69517002
return r;
69527003

7004+
if (adev->asic_type == CHIP_SIENNA_CICHLID)
7005+
gfx_v10_3_program_pbb_mode(adev);
7006+
69537007
return r;
69547008
}
69557009

@@ -8763,6 +8817,10 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
87638817
mutex_lock(&adev->grbm_idx_mutex);
87648818
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
87658819
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8820+
bitmap = i * adev->gfx.config.max_sh_per_se + j;
8821+
if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
8822+
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
8823+
continue;
87668824
mask = 1;
87678825
ao_bitmap = 0;
87688826
counter = 0;
@@ -8797,6 +8855,47 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
87978855
return 0;
87988856
}
87998857

8858+
static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
8859+
{
8860+
uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
8861+
8862+
efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
8863+
efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8864+
efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8865+
8866+
vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
8867+
vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8868+
vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8869+
8870+
max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
8871+
adev->gfx.config.max_shader_engines);
8872+
disabled_sa = efuse_setting | vbios_setting;
8873+
disabled_sa &= max_sa_mask;
8874+
8875+
return disabled_sa;
8876+
}
8877+
8878+
static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
8879+
{
8880+
uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
8881+
uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
8882+
8883+
disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
8884+
8885+
max_sa_per_se = adev->gfx.config.max_sh_per_se;
8886+
max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
8887+
max_shader_engines = adev->gfx.config.max_shader_engines;
8888+
8889+
for (se_index = 0; max_shader_engines > se_index; se_index++) {
8890+
disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
8891+
disabled_sa_per_se &= max_sa_per_se_mask;
8892+
if (disabled_sa_per_se == max_sa_per_se_mask) {
8893+
WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
8894+
break;
8895+
}
8896+
}
8897+
}
8898+
88008899
const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
88018900
{
88028901
.type = AMD_IP_BLOCK_TYPE_GFX,

‎drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ enum psp_gfx_fw_type {
201201
GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
202202
GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
203203
GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */
204-
GFX_FW_TYPE_RLX6 = 26, /* RLX6 NV */
204+
GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */
205205
GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */
206206
GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */
207207
GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */
@@ -223,7 +223,7 @@ enum psp_gfx_fw_type {
223223
GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */
224224
GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */
225225
GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */
226-
GFX_FW_TYPE_RLX6_DRAM_BOOT = 48, /* RLX6 DRAM BOOT NV */
226+
GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */
227227
GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */
228228
GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */
229229
GFX_FW_TYPE_DMUB = 51, /* DMUB RN */

‎drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,9 @@ static int update_qpd_v10(struct device_queue_manager *dqm,
5858
/* check if sh_mem_config register already configured */
5959
if (qpd->sh_mem_config == 0) {
6060
qpd->sh_mem_config =
61-
SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
62-
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
61+
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
62+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
63+
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
6364
#if 0
6465
/* TODO:
6566
* This shouldn't be an issue with Navi10. Verify.

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5063,7 +5063,13 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
50635063
struct amdgpu_device *adev = drm_to_adev(connector->dev);
50645064
struct amdgpu_display_manager *dm = &adev->dm;
50655065

5066-
drm_atomic_private_obj_fini(&aconnector->mst_mgr.base);
5066+
/*
5067+
* Call only if mst_mgr was iniitalized before since it's not done
5068+
* for all connector types.
5069+
*/
5070+
if (aconnector->mst_mgr.dev)
5071+
drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5072+
50675073
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
50685074
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
50695075

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