Skip to content

Commit 15cb546

Browse files
torvaldstorvalds
committed
Merge tag 'platform-drivers-x86-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
Pull x86 platform driver updates from Hans de Goede: "Rather calm cycle for x86 platform drivers, all these have been in for-next for a couple of days with no bot complaints. Highlights: - PMC TigerLake fixes and new RocketLake support - various small fixes / updates in other drivers/tools" * tag 'platform-drivers-x86-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: MAINTAINERS: update X86 PLATFORM DRIVERS entry with new kernel.org git repo platform/x86: mlx-platform: Add capability field to platform FAN description platform_data/mlxreg: Extend core platform structure platform_data/mlxreg: Update module license platform/x86: mlx-platform: Remove PSU EEPROM configuration MAINTAINERS: Update maintainers for pmc_core driver platform/x86: intel_pmc_core: fix: Replace dev_dbg macro with dev_info() platform/x86: intel_pmc_core: Add Intel RocketLake (RKL) support platform/x86: intel_pmc_core: Clean up: Remove the duplicate comments and reorganize platform/x86: intel_pmc_core: Fix the slp_s0 counter displayed value platform/x86: intel_pmc_core: Fix TigerLake power gating status map platform/x86: pmc_core: Use descriptive names for LPM registers tools/power/x86/intel-speed-select: Update version for v5.10 tools/power/x86/intel-speed-select: Fix missing base-freq core IDs platform/x86: hp-wmi: add support for thermal policy
2 parents a09b1d7 + 1a3f781 commit 15cb546

9 files changed

Lines changed: 122 additions & 116 deletions

File tree

‎MAINTAINERS‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8940,8 +8940,8 @@ F: arch/x86/include/asm/intel_punit_ipc.h
89408940
F: drivers/platform/x86/intel_punit_ipc.c
89418941

89428942
INTEL PMC CORE DRIVER
8943-
M: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
8944-
M: Vishwanath Somayaji <vishwanath.somayaji@intel.com>
8943+
M: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
8944+
M: David E Box <david.e.box@intel.com>
89458945
L: platform-driver-x86@vger.kernel.org
89468946
S: Maintained
89478947
F: drivers/platform/x86/intel_pmc_core*
@@ -18921,7 +18921,7 @@ M: Hans de Goede <hdegoede@redhat.com>
1892118921
M: Mark Gross <mgross@linux.intel.com>
1892218922
L: platform-driver-x86@vger.kernel.org
1892318923
S: Maintained
18924-
T: git git://git.infradead.org/linux-platform-drivers-x86.git
18924+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git
1892518925
F: drivers/platform/olpc/
1892618926
F: drivers/platform/x86/
1892718927

‎drivers/platform/x86/hp-wmi.c‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@ enum hp_wmi_commandtype {
8181
HPWMI_FEATURE2_QUERY = 0x0d,
8282
HPWMI_WIRELESS2_QUERY = 0x1b,
8383
HPWMI_POSTCODEERROR_QUERY = 0x2a,
84+
HPWMI_THERMAL_POLICY_QUERY = 0x4c,
8485
};
8586

8687
enum hp_wmi_command {
@@ -861,6 +862,26 @@ static int __init hp_wmi_rfkill2_setup(struct platform_device *device)
861862
return err;
862863
}
863864

865+
static int thermal_policy_setup(struct platform_device *device)
866+
{
867+
int err, tp;
868+
869+
tp = hp_wmi_read_int(HPWMI_THERMAL_POLICY_QUERY);
870+
if (tp < 0)
871+
return tp;
872+
873+
/*
874+
* call thermal policy write command to ensure that the firmware correctly
875+
* sets the OEM variables for the DPTF
876+
*/
877+
err = hp_wmi_perform_query(HPWMI_THERMAL_POLICY_QUERY, HPWMI_WRITE, &tp,
878+
sizeof(tp), 0);
879+
if (err)
880+
return err;
881+
882+
return 0;
883+
}
884+
864885
static int __init hp_wmi_bios_setup(struct platform_device *device)
865886
{
866887
/* clear detected rfkill devices */
@@ -872,6 +893,8 @@ static int __init hp_wmi_bios_setup(struct platform_device *device)
872893
if (hp_wmi_rfkill_setup(device))
873894
hp_wmi_rfkill2_setup(device);
874895

896+
thermal_policy_setup(device);
897+
875898
return 0;
876899
}
877900

‎drivers/platform/x86/intel_pmc_core.c‎

Lines changed: 67 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,10 @@ static const struct pmc_bit_map spt_pfear_map[] = {
118118
};
119119

120120
static const struct pmc_bit_map *ext_spt_pfear_map[] = {
121+
/*
122+
* Check intel_pmc_core_ids[] users of spt_reg_map for
123+
* a list of core SoCs using this.
124+
*/
121125
spt_pfear_map,
122126
NULL
123127
};
@@ -154,6 +158,7 @@ static const struct pmc_reg_map spt_reg_map = {
154158
.ltr_show_sts = spt_ltr_show_map,
155159
.msr_sts = msr_map,
156160
.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
161+
.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
157162
.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
158163
.regmap_length = SPT_PMC_MMIO_REG_LEN,
159164
.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
@@ -166,7 +171,6 @@ static const struct pmc_reg_map spt_reg_map = {
166171

167172
/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
168173
static const struct pmc_bit_map cnp_pfear_map[] = {
169-
/* Reserved for Cannon Lake but valid for Comet Lake */
170174
{"PMC", BIT(0)},
171175
{"OPI-DMI", BIT(1)},
172176
{"SPI/eSPI", BIT(2)},
@@ -192,10 +196,6 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
192196
{"SDX", BIT(4)},
193197
{"SPE", BIT(5)},
194198
{"Fuse", BIT(6)},
195-
/*
196-
* Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
197-
* Tiger Lake, Elkhart Lake and Jasper Lake.
198-
*/
199199
{"SBR8", BIT(7)},
200200

201201
{"CSME_FSC", BIT(0)},
@@ -239,23 +239,22 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
239239
{"HDA_PGD4", BIT(2)},
240240
{"HDA_PGD5", BIT(3)},
241241
{"HDA_PGD6", BIT(4)},
242-
/*
243-
* Reserved for Cannon Lake but valid for Ice Lake, Comet Lake,
244-
* Tiger Lake, ELkhart Lake and Jasper Lake.
245-
*/
246242
{"PSF6", BIT(5)},
247243
{"PSF7", BIT(6)},
248244
{"PSF8", BIT(7)},
249245
{}
250246
};
251247

252248
static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
249+
/*
250+
* Check intel_pmc_core_ids[] users of cnp_reg_map for
251+
* a list of core SoCs using this.
252+
*/
253253
cnp_pfear_map,
254254
NULL
255255
};
256256

257257
static const struct pmc_bit_map icl_pfear_map[] = {
258-
/* Ice Lake and Jasper Lake generation onwards only */
259258
{"RES_65", BIT(0)},
260259
{"RES_66", BIT(1)},
261260
{"RES_67", BIT(2)},
@@ -268,13 +267,16 @@ static const struct pmc_bit_map icl_pfear_map[] = {
268267
};
269268

270269
static const struct pmc_bit_map *ext_icl_pfear_map[] = {
270+
/*
271+
* Check intel_pmc_core_ids[] users of icl_reg_map for
272+
* a list of core SoCs using this.
273+
*/
271274
cnp_pfear_map,
272275
icl_pfear_map,
273276
NULL
274277
};
275278

276279
static const struct pmc_bit_map tgl_pfear_map[] = {
277-
/* Tiger Lake and Elkhart Lake generation onwards only */
278280
{"PSF9", BIT(0)},
279281
{"RES_66", BIT(1)},
280282
{"RES_67", BIT(2)},
@@ -286,6 +288,10 @@ static const struct pmc_bit_map tgl_pfear_map[] = {
286288
};
287289

288290
static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
291+
/*
292+
* Check intel_pmc_core_ids[] users of tgl_reg_map for
293+
* a list of core SoCs using this.
294+
*/
289295
cnp_pfear_map,
290296
tgl_pfear_map,
291297
NULL
@@ -369,7 +375,10 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
369375
{"ISH", CNP_PMC_LTR_ISH},
370376
{"UFSX2", CNP_PMC_LTR_UFSX2},
371377
{"EMMC", CNP_PMC_LTR_EMMC},
372-
/* Reserved for Cannon Lake but valid for Ice Lake */
378+
/*
379+
* Check intel_pmc_core_ids[] users of cnp_reg_map for
380+
* a list of core SoCs using this.
381+
*/
373382
{"WIGIG", ICL_PMC_LTR_WIGIG},
374383
/* Below two cannot be used for LTR_IGNORE */
375384
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
@@ -380,6 +389,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
380389
static const struct pmc_reg_map cnp_reg_map = {
381390
.pfear_sts = ext_cnp_pfear_map,
382391
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
392+
.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
383393
.slps0_dbg_maps = cnp_slps0_dbg_maps,
384394
.ltr_show_sts = cnp_ltr_show_map,
385395
.msr_sts = msr_map,
@@ -396,6 +406,7 @@ static const struct pmc_reg_map cnp_reg_map = {
396406
static const struct pmc_reg_map icl_reg_map = {
397407
.pfear_sts = ext_icl_pfear_map,
398408
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
409+
.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
399410
.slps0_dbg_maps = cnp_slps0_dbg_maps,
400411
.ltr_show_sts = cnp_ltr_show_map,
401412
.msr_sts = msr_map,
@@ -409,7 +420,7 @@ static const struct pmc_reg_map icl_reg_map = {
409420
.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
410421
};
411422

412-
static const struct pmc_bit_map tgl_lpm0_map[] = {
423+
static const struct pmc_bit_map tgl_clocksource_status_map[] = {
413424
{"USB2PLL_OFF_STS", BIT(18)},
414425
{"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
415426
{"PCIe_Gen3PLL_OFF_STS", BIT(20)},
@@ -425,35 +436,35 @@ static const struct pmc_bit_map tgl_lpm0_map[] = {
425436
{}
426437
};
427438

428-
static const struct pmc_bit_map tgl_lpm1_map[] = {
429-
{"SPI_PG_STS", BIT(2)},
430-
{"xHCI_PG_STS", BIT(3)},
431-
{"PCIe_Ctrller_A_PG_STS", BIT(4)},
432-
{"PCIe_Ctrller_B_PG_STS", BIT(5)},
433-
{"PCIe_Ctrller_C_PG_STS", BIT(6)},
434-
{"GBE_PG_STS", BIT(7)},
435-
{"SATA_PG_STS", BIT(8)},
436-
{"HDA0_PG_STS", BIT(9)},
437-
{"HDA1_PG_STS", BIT(10)},
438-
{"HDA2_PG_STS", BIT(11)},
439-
{"HDA3_PG_STS", BIT(12)},
440-
{"PCIe_Ctrller_D_PG_STS", BIT(13)},
441-
{"ISIO_PG_STS", BIT(14)},
442-
{"SMB_PG_STS", BIT(16)},
443-
{"ISH_PG_STS", BIT(17)},
444-
{"ITH_PG_STS", BIT(19)},
445-
{"SDX_PG_STS", BIT(20)},
446-
{"xDCI_PG_STS", BIT(25)},
447-
{"DCI_PG_STS", BIT(26)},
448-
{"CSME0_PG_STS", BIT(27)},
449-
{"CSME_KVM_PG_STS", BIT(28)},
450-
{"CSME1_PG_STS", BIT(29)},
451-
{"CSME_CLINK_PG_STS", BIT(30)},
452-
{"CSME2_PG_STS", BIT(31)},
439+
static const struct pmc_bit_map tgl_power_gating_status_map[] = {
440+
{"CSME_PG_STS", BIT(0)},
441+
{"SATA_PG_STS", BIT(1)},
442+
{"xHCI_PG_STS", BIT(2)},
443+
{"UFSX2_PG_STS", BIT(3)},
444+
{"OTG_PG_STS", BIT(5)},
445+
{"SPA_PG_STS", BIT(6)},
446+
{"SPB_PG_STS", BIT(7)},
447+
{"SPC_PG_STS", BIT(8)},
448+
{"SPD_PG_STS", BIT(9)},
449+
{"SPE_PG_STS", BIT(10)},
450+
{"SPF_PG_STS", BIT(11)},
451+
{"LSX_PG_STS", BIT(13)},
452+
{"P2SB_PG_STS", BIT(14)},
453+
{"PSF_PG_STS", BIT(15)},
454+
{"SBR_PG_STS", BIT(16)},
455+
{"OPIDMI_PG_STS", BIT(17)},
456+
{"THC0_PG_STS", BIT(18)},
457+
{"THC1_PG_STS", BIT(19)},
458+
{"GBETSN_PG_STS", BIT(20)},
459+
{"GBE_PG_STS", BIT(21)},
460+
{"LPSS_PG_STS", BIT(22)},
461+
{"MMP_UFSX2_PG_STS", BIT(23)},
462+
{"MMP_UFSX2B_PG_STS", BIT(24)},
463+
{"FIA_PG_STS", BIT(25)},
453464
{}
454465
};
455466

456-
static const struct pmc_bit_map tgl_lpm2_map[] = {
467+
static const struct pmc_bit_map tgl_d3_status_map[] = {
457468
{"ADSP_D3_STS", BIT(0)},
458469
{"SATA_D3_STS", BIT(1)},
459470
{"xHCI0_D3_STS", BIT(2)},
@@ -468,7 +479,7 @@ static const struct pmc_bit_map tgl_lpm2_map[] = {
468479
{}
469480
};
470481

471-
static const struct pmc_bit_map tgl_lpm3_map[] = {
482+
static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
472483
{"GPIO_COM0_VNN_REQ_STS", BIT(1)},
473484
{"GPIO_COM1_VNN_REQ_STS", BIT(2)},
474485
{"GPIO_COM2_VNN_REQ_STS", BIT(3)},
@@ -493,7 +504,7 @@ static const struct pmc_bit_map tgl_lpm3_map[] = {
493504
{}
494505
};
495506

496-
static const struct pmc_bit_map tgl_lpm4_map[] = {
507+
static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
497508
{"CPU_C10_REQ_STS_0", BIT(0)},
498509
{"PCIe_LPM_En_REQ_STS_3", BIT(3)},
499510
{"ITH_REQ_STS_5", BIT(5)},
@@ -509,7 +520,7 @@ static const struct pmc_bit_map tgl_lpm4_map[] = {
509520
{}
510521
};
511522

512-
static const struct pmc_bit_map tgl_lpm5_map[] = {
523+
static const struct pmc_bit_map tgl_signal_status_map[] = {
513524
{"LSX_Wake0_En_STS", BIT(0)},
514525
{"LSX_Wake0_Pol_STS", BIT(1)},
515526
{"LSX_Wake1_En_STS", BIT(2)},
@@ -546,18 +557,19 @@ static const struct pmc_bit_map tgl_lpm5_map[] = {
546557
};
547558

548559
static const struct pmc_bit_map *tgl_lpm_maps[] = {
549-
tgl_lpm0_map,
550-
tgl_lpm1_map,
551-
tgl_lpm2_map,
552-
tgl_lpm3_map,
553-
tgl_lpm4_map,
554-
tgl_lpm5_map,
560+
tgl_clocksource_status_map,
561+
tgl_power_gating_status_map,
562+
tgl_d3_status_map,
563+
tgl_vnn_req_status_map,
564+
tgl_vnn_misc_status_map,
565+
tgl_signal_status_map,
555566
NULL
556567
};
557568

558569
static const struct pmc_reg_map tgl_reg_map = {
559570
.pfear_sts = ext_tgl_pfear_map,
560571
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
572+
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
561573
.ltr_show_sts = cnp_ltr_show_map,
562574
.msr_sts = msr_map,
563575
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
@@ -586,9 +598,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
586598
writel(val, pmcdev->regbase + reg_offset);
587599
}
588600

589-
static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
601+
static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
590602
{
591-
return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
603+
return (u64)value * pmcdev->map->slp_s0_res_counter_step;
592604
}
593605

594606
static int pmc_core_dev_state_get(void *data, u64 *val)
@@ -598,7 +610,7 @@ static int pmc_core_dev_state_get(void *data, u64 *val)
598610
u32 value;
599611

600612
value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
601-
*val = pmc_core_adjust_slp_s0_step(value);
613+
*val = pmc_core_adjust_slp_s0_step(pmcdev, value);
602614

603615
return 0;
604616
}
@@ -628,7 +640,7 @@ static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
628640
offset += 4;
629641
while (map->name) {
630642
if (dev)
631-
dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
643+
dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
632644
map->name,
633645
data & map->bit_mask ? "Yes" : "No");
634646
if (s)
@@ -671,15 +683,15 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
671683

672684
for (idx = 0; idx < arr_size; idx++) {
673685
if (dev)
674-
dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
686+
dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
675687
lpm_regs[idx]);
676688
if (s)
677689
seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
678690
lpm_regs[idx]);
679691
for (index = 0; maps[idx][index].name && index < len; index++) {
680692
bit_mask = maps[idx][index].bit_mask;
681693
if (dev)
682-
dev_dbg(dev, "%-30s %-30d\n",
694+
dev_info(dev, "%-30s %-30d\n",
683695
maps[idx][index].name,
684696
lpm_regs[idx] & bit_mask ? 1 : 0);
685697
if (s)
@@ -1147,6 +1159,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
11471159
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
11481160
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
11491161
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
1162+
X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map),
11501163
{}
11511164
};
11521165

‎drivers/platform/x86/intel_pmc_core.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@
3030
#define SPT_PMC_MPHY_CORE_STS_1 0x1142
3131
#define SPT_PMC_MPHY_COM_STS_0 0x1155
3232
#define SPT_PMC_MMIO_REG_LEN 0x1000
33-
#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64
33+
#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68
3434
#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
3535
#define MTPMC_MASK 0xffff0000
3636
#define PPFEAR_MAX_NUM_ENTRIES 12
@@ -185,8 +185,10 @@ enum ppfear_regs {
185185
#define ICL_PPFEAR_NUM_ENTRIES 9
186186
#define ICL_NUM_IP_IGN_ALLOWED 20
187187
#define ICL_PMC_LTR_WIGIG 0x1BFC
188+
#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64
188189

189190
#define TGL_NUM_IP_IGN_ALLOWED 22
191+
#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A
190192

191193
/*
192194
* Tigerlake Power Management Controller register offsets
@@ -245,6 +247,7 @@ struct pmc_reg_map {
245247
const struct pmc_bit_map *msr_sts;
246248
const struct pmc_bit_map **lpm_sts;
247249
const u32 slp_s0_offset;
250+
const int slp_s0_res_counter_step;
248251
const u32 ltr_ignore_offset;
249252
const int regmap_length;
250253
const u32 ppfear0_offset;

0 commit comments

Comments
 (0)