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airliedairlied
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Merge tag 'amd-drm-fixes-5.9-2020-09-30' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.9-2020-09-30: amdgpu: - Fix potential double free in userptr handling - Sienna Cichlid and Navy Flounder udpates - Add Sienna Cichlid PCI IDs - Drop experimental flag for navi12 - Raven fixes - Renoir fixes - HDCP fix - DCN3 fix for clang and older versions of gcc - Fix a runtime pm refcount issue Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200930161326.4243-1-alexander.deucher@amd.com
2 parents 6f4fc18 + 95433a1 commit 132d7c8

16 files changed

Lines changed: 154 additions & 41 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -80,8 +80,6 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
8080
MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
8181
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
8282
MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83-
MODULE_FIRMWARE("amdgpu/sienna_cichlid_gpu_info.bin");
84-
MODULE_FIRMWARE("amdgpu/navy_flounder_gpu_info.bin");
8583

8684
#define AMDGPU_RESUME_MS 2000
8785

@@ -1600,6 +1598,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
16001598
case CHIP_CARRIZO:
16011599
case CHIP_STONEY:
16021600
case CHIP_VEGA20:
1601+
case CHIP_SIENNA_CICHLID:
1602+
case CHIP_NAVY_FLOUNDER:
16031603
default:
16041604
return 0;
16051605
case CHIP_VEGA10:
@@ -1631,12 +1631,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
16311631
case CHIP_NAVI12:
16321632
chip_name = "navi12";
16331633
break;
1634-
case CHIP_SIENNA_CICHLID:
1635-
chip_name = "sienna_cichlid";
1636-
break;
1637-
case CHIP_NAVY_FLOUNDER:
1638-
chip_name = "navy_flounder";
1639-
break;
16401634
}
16411635

16421636
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
297297
take the current one */
298298
if (active && !adev->have_disp_power_ref) {
299299
adev->have_disp_power_ref = true;
300-
goto out;
300+
return ret;
301301
}
302302
/* if we have no active crtcs, then drop the power ref
303303
we got before */

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1044,8 +1044,16 @@ static const struct pci_device_id pciidlist[] = {
10441044
{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
10451045

10461046
/* Navi12 */
1047-
{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
1048-
{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
1047+
{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1048+
{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1049+
1050+
/* Sienna_Cichlid */
1051+
{0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1052+
{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1053+
{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1054+
{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1055+
{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1056+
{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
10491057

10501058
{0, 0, 0}
10511059
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1076,6 +1076,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
10761076

10771077
release_sg:
10781078
kfree(ttm->sg);
1079+
ttm->sg = NULL;
10791080
return r;
10801081
}
10811082

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3595,6 +3595,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
35953595
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
35963596
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
35973597
break;
3598+
case CHIP_NAVY_FLOUNDER:
3599+
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3600+
break;
35983601
default:
35993602
break;
36003603
}

‎drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -746,18 +746,18 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
746746
| UVD_SUVD_CGC_GATE__IME_HEVC_MASK
747747
| UVD_SUVD_CGC_GATE__EFC_MASK
748748
| UVD_SUVD_CGC_GATE__SAOE_MASK
749-
| 0x08000000
749+
| UVD_SUVD_CGC_GATE__SRE_AV1_MASK
750750
| UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
751751
| UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
752-
| 0x40000000
752+
| UVD_SUVD_CGC_GATE__SCM_AV1_MASK
753753
| UVD_SUVD_CGC_GATE__SMPA_MASK);
754754
WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
755755

756756
data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
757757
data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
758758
| UVD_SUVD_CGC_GATE2__MPBE1_MASK
759-
| 0x00000004
760-
| 0x00000008
759+
| UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
760+
| UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
761761
| UVD_SUVD_CGC_GATE2__MPC1_MASK);
762762
WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
763763

@@ -776,8 +776,8 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
776776
| UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
777777
| UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
778778
| UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
779-
| 0x00008000
780-
| 0x00010000
779+
| UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
780+
| UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
781781
| UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
782782
| UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
783783
| UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
@@ -892,8 +892,8 @@ static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
892892
| UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
893893
| UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
894894
| UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
895-
| 0x00008000
896-
| 0x00010000
895+
| UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
896+
| UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
897897
| UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
898898
| UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
899899
| UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -604,7 +604,7 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct
604604
int i = 0;
605605

606606
hdcp_work = kcalloc(max_caps, sizeof(*hdcp_work), GFP_KERNEL);
607-
if (hdcp_work == NULL)
607+
if (ZERO_OR_NULL_PTR(hdcp_work))
608608
return NULL;
609609

610610
hdcp_work->srm = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, sizeof(*hdcp_work->srm), GFP_KERNEL);

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -783,7 +783,6 @@ void rn_clk_mgr_construct(
783783
} else {
784784
struct clk_log_info log_info = {0};
785785

786-
clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
787786
clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
788787

789788
/* SMU Version 55.51.0 and up no longer have an issue

‎drivers/gpu/drm/amd/display/dc/dcn30/Makefile‎

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,21 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o dcn30_optc.o \
3131
dcn30_dio_link_encoder.o dcn30_resource.o
3232

3333

34-
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse -mpreferred-stack-boundary=4
35-
34+
ifdef CONFIG_X86
3635
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
36+
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
37+
endif
38+
39+
ifdef CONFIG_PPC64
40+
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -maltivec
41+
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -maltivec
42+
endif
43+
44+
ifdef CONFIG_ARM64
45+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mgeneral-regs-only
46+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mgeneral-regs-only
47+
endif
48+
3749
ifdef CONFIG_CC_IS_GCC
3850
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
3951
IS_OLD_GCC = 1
@@ -45,8 +57,10 @@ ifdef IS_OLD_GCC
4557
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
4658
# (8B stack alignment).
4759
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mpreferred-stack-boundary=4
60+
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mpreferred-stack-boundary=4
4861
else
4962
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -msse2
63+
CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -msse2
5064
endif
5165

5266
AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30))

‎drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2727,6 +2727,7 @@
27272727
#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000
27282728
#define mmDB_RESERVED_REG_1_DEFAULT 0x00000000
27292729
#define mmDB_RESERVED_REG_3_DEFAULT 0x00000000
2730+
#define mmDB_VRS_OVERRIDE_CNTL_DEFAULT 0x00000000
27302731
#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000
27312732
#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000
27322733
#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000
@@ -3062,6 +3063,7 @@
30623063
#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000
30633064
#define mmPA_STEREO_CNTL_DEFAULT 0x00000000
30643065
#define mmPA_STATE_STEREO_X_DEFAULT 0x00000000
3066+
#define mmPA_CL_VRS_CNTL_DEFAULT 0x00000000
30653067
#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000
30663068
#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000
30673069
#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000

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