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soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines
Change the RACPREFDATA(x) setting to prefetch the next 256-byte line after 4 consecutive lines have been used, instead of after 2 consecutive lines. This does improve the synthetic memcpy benchmark by an additional +0.5% on top of the previous change for Cortex-A72 CPUs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
1 parent 091353c commit 10e7dd5

1 file changed

Lines changed: 6 additions & 2 deletions

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drivers/soc/bcm/brcmstb/biuctrl.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@ static const u32 a72_b53_mach_compat[] = {
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static void __init a72_b53_rac_enable_all(struct device_node *np)
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{
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unsigned int cpu;
177-
u32 enable = 0, pref_dist;
177+
u32 enable = 0, pref_dist, shift;
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if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
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return;
@@ -184,9 +184,13 @@ static void __init a72_b53_rac_enable_all(struct device_node *np)
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pref_dist = cbc_readl(RAC_CONFIG1_REG);
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for_each_possible_cpu(cpu) {
187+
shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
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enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
188-
if (cpubiuctrl_regs == a72_cpubiuctrl_regs)
189+
if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
190+
enable &= ~(RACENPREF_MASK << shift);
191+
enable |= 3 << shift;
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pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
193+
}
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}
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cbc_writel(enable, RAC_CONFIG0_REG);

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