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1 | | -From 77f6dfcb20c2dc6a4a2f5303709c6fa0c7b65f30 Mon Sep 17 00:00:00 2001 |
| 1 | +From c3fe7071e196e25789ecf90dbc9e8491a98884d7 Mon Sep 17 00:00:00 2001 |
2 | 2 | From: Valmantas Paliksa <walmis@gmail.com> |
3 | | -Date: Thu, 12 Dec 2024 12:24:33 +0200 |
4 | | -Subject: [PATCH] Disable PHY_LANE_IDLE_OFF for each instance of rockchip_pcie_phy_power_one |
| 3 | +Date: Mon, 30 Jun 2025 19:25:14 -0300 |
| 4 | +Subject: [PATCH] phy: rockchip-pcie: Enable all four lanes if required |
5 | 5 |
|
6 | | -This patch fixes an issue in the Rockchip PCIe PHY driver where, after a warm restart of the rockchip_pcie_phy module, PCIe lanes other than lane 0 could remain stuck in the PHY_LANE_IDLE_OFF state. This resulted in the PCIe link being restricted to x1 mode, even in configurations designed to use multiple lanes. |
| 6 | +Current code enables only Lane 0 because pwr_cnt will be incremented on |
| 7 | +first call to the function. Let's reorder the enablement code to enable |
| 8 | +all 4 lanes through GRF. |
| 9 | + |
| 10 | +Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> |
| 11 | +Reviewed-by: Robin Murphy <robin.murphy@arm.com> |
7 | 12 |
|
8 | 13 | Signed-off-by: Valmantas Paliksa <walmis@gmail.com> |
| 14 | +Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com> |
| 15 | +Reviewed-by: Robin Murphy <robin.murphy@arm.com> |
| 16 | +Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> |
| 17 | +Link: https://lore.kernel.org/r/16b610aab34e069fd31d9f57260c10df2a968f80.1751322015.git.geraldogabriel@gmail.com |
| 18 | +Signed-off-by: Vinod Koul <vkoul@kernel.org> |
9 | 19 | --- |
10 | 20 | drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------ |
11 | 21 | 1 file changed, 6 insertions(+), 6 deletions(-) |
12 | 22 |
|
13 | 23 | --- a/drivers/phy/rockchip/phy-rockchip-pcie.c |
14 | 24 | +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c |
15 | | -@@ -166,6 +166,12 @@ static int rockchip_pcie_phy_power_on(st |
16 | | - unsigned long timeout; |
| 25 | +@@ -165,6 +165,12 @@ static int rockchip_pcie_phy_power_on(st |
17 | 26 |
|
18 | 27 | mutex_lock(&rk_phy->pcie_mutex); |
19 | | -+ |
| 28 | + |
20 | 29 | + regmap_write(rk_phy->reg_base, |
21 | 30 | + rk_phy->phy_data->pcie_laneoff, |
22 | 31 | + HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, |
23 | 32 | + PHY_LANE_IDLE_MASK, |
24 | 33 | + PHY_LANE_IDLE_A_SHIFT + inst->index)); |
25 | | - |
| 34 | ++ |
26 | 35 | if (rk_phy->pwr_cnt++) |
27 | 36 | goto err_out; |
28 | | -@@ -181,12 +187,6 @@ static int rockchip_pcie_phy_power_on(st |
| 37 | + |
| 38 | +@@ -179,12 +185,6 @@ static int rockchip_pcie_phy_power_on(st |
29 | 39 | PHY_CFG_ADDR_MASK, |
30 | 40 | PHY_CFG_ADDR_SHIFT)); |
31 | 41 |
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