From cc8f7281d8589916074869f282dbd59d3156ba5f Mon Sep 17 00:00:00 2001 From: functionstackx <47992694+functionstackx@users.noreply.github.com> Date: Sun, 14 Jun 2026 18:02:47 -0400 Subject: [PATCH 1/2] minimaxm3 H100/H200 non-MTP: conc-1 latency + full TEP coverage (1-256) H100: TP8 latency rows start at conc 1; TP8+EP8 (TEP8) now sweeps conc 1-256. H200: TP4 and TP8 latency rows start at conc 1; TP4+EP4 (TEP4) and TP8+EP8 (TEP8) now sweep conc 1-256, adding a TEP4 row to 8k1k. H200 TEP8 upper bound moves 512->256 (high concurrency stays covered by the dp-attn DEP rows). DEP rows unchanged. Co-Authored-By: Claude Fable 5 --- .github/configs/nvidia-master.yaml | 23 ++++++++++++----------- perf-changelog.yaml | 7 +++++++ 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/.github/configs/nvidia-master.yaml b/.github/configs/nvidia-master.yaml index 2b2848714..5f7d16d60 100644 --- a/.github/configs/nvidia-master.yaml +++ b/.github/configs/nvidia-master.yaml @@ -4635,13 +4635,13 @@ minimaxm3-fp8-h100-vllm: # ~52 GB expert shard, and KV-cache init fails at high conc (sweep # 27441767143, conc 256/512: "No available memory for the cache # blocks"). TEP8 covers the high-concurrency regime instead. - - { tp: 8, conc-start: 4, conc-end: 128 } - - { tp: 8, ep: 8, conc-start: 256, conc-end: 256 } + - { tp: 8, conc-start: 1, conc-end: 128 } + - { tp: 8, ep: 8, conc-start: 1, conc-end: 256 } - isl: 8192 osl: 1024 search-space: - - { tp: 8, conc-start: 4, conc-end: 64 } - - { tp: 8, ep: 8, conc-start: 128, conc-end: 256 } + - { tp: 8, conc-start: 1, conc-end: 64 } + - { tp: 8, ep: 8, conc-start: 1, conc-end: 256 } dsr1-fp8-h100-dynamo-sglang: image: lmsysorg/sglang:v0.5.8-cu130 @@ -4888,17 +4888,18 @@ minimaxm3-fp8-h200-vllm: - isl: 1024 osl: 1024 search-space: - - { tp: 4, conc-start: 4, conc-end: 64 } - - { tp: 4, ep: 4, conc-start: 128, conc-end: 256 } - - { tp: 8, conc-start: 4, conc-end: 128 } - - { tp: 8, ep: 8, conc-start: 256, conc-end: 512 } + - { tp: 4, conc-start: 1, conc-end: 64 } + - { tp: 4, ep: 4, conc-start: 1, conc-end: 256 } + - { tp: 8, conc-start: 1, conc-end: 128 } + - { tp: 8, ep: 8, conc-start: 1, conc-end: 256 } - { tp: 8, ep: 8, dp-attn: true, conc-start: 256, conc-end: 1024 } - isl: 8192 osl: 1024 search-space: - - { tp: 4, conc-start: 4, conc-end: 32 } - - { tp: 8, conc-start: 4, conc-end: 128 } - - { tp: 8, ep: 8, conc-start: 256, conc-end: 256 } + - { tp: 4, conc-start: 1, conc-end: 32 } + - { tp: 4, ep: 4, conc-start: 1, conc-end: 256 } + - { tp: 8, conc-start: 1, conc-end: 128 } + - { tp: 8, ep: 8, conc-start: 1, conc-end: 256 } - { tp: 8, ep: 8, dp-attn: true, conc-start: 256, conc-end: 512 } dsr1-fp4-gb200-dynamo-trt: diff --git a/perf-changelog.yaml b/perf-changelog.yaml index eda79758b..fbb8524b8 100644 --- a/perf-changelog.yaml +++ b/perf-changelog.yaml @@ -3800,3 +3800,10 @@ - "H200-style search space (TP4/TP8 latency, TP4+EP4/TP8+EP8 TEP, TP8+EP8 dp-attn DEP) trimmed at the extreme-concurrency end with TP-only latency rows started at conc 1" - "[AI generated draft test] The shipped ROCm image's AMD MiniMax-M3 model lacks SupportsEagle3, so the recipe patches it in-place at runtime (functionstackx/vllm#1, upstream vllm-project/vllm#45546; validated green on MI355X/MI300X) before serving; also adds SPEC_SUFFIX to launch_mi325x-amds.sh so spec-decoding=mtp routes to the _mtp script" pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/1759 + +- config-keys: + - minimaxm3-fp8-h100-vllm + - minimaxm3-fp8-h200-vllm + description: + - "Extend MiniMax-M3 MXFP8 H100/H200 non-MTP sweeps to concurrency 1 on the latency rows (H100: TP8; H200: TP4 and TP8) and add full TEP coverage from conc 1 to 256 (H100: TP8+EP8; H200: TP4+EP4 and TP8+EP8, incl. a new TP4+EP4 row for 8k1k). H200 TP8+EP8 upper bound moves 512->256 (high concurrency stays covered by the TP8+EP8 dp-attn DEP rows). DEP rows unchanged" + pr-link: TBD From e3e3f0716c3adf1d1efc032e3dfc92a938bccf00 Mon Sep 17 00:00:00 2001 From: functionstackx <47992694+functionstackx@users.noreply.github.com> Date: Sun, 14 Jun 2026 18:03:00 -0400 Subject: [PATCH 2/2] perf-changelog: fill in PR link for H100/H200 conc-1 + TEP Co-Authored-By: Claude Fable 5 --- perf-changelog.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/perf-changelog.yaml b/perf-changelog.yaml index fbb8524b8..fceb68948 100644 --- a/perf-changelog.yaml +++ b/perf-changelog.yaml @@ -3806,4 +3806,4 @@ - minimaxm3-fp8-h200-vllm description: - "Extend MiniMax-M3 MXFP8 H100/H200 non-MTP sweeps to concurrency 1 on the latency rows (H100: TP8; H200: TP4 and TP8) and add full TEP coverage from conc 1 to 256 (H100: TP8+EP8; H200: TP4+EP4 and TP8+EP8, incl. a new TP4+EP4 row for 8k1k). H200 TP8+EP8 upper bound moves 512->256 (high concurrency stays covered by the TP8+EP8 dp-attn DEP rows). DEP rows unchanged" - pr-link: TBD + pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/1761