diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 4634569cd..328dd8530 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -71,6 +71,10 @@ jobs:
       - name: Check refactor packaging and compatibility
         run: python ci/run.py layout -q
 
+      - name: Run H3 Sigma Schedule Tests (CPU-safe)
+        run: |
+          python -m pytest tests/reference/minimax_h3 tests/runtime/test_h3_sigma_schedule_dispatch.py -q
+
       - name: Run Mocked Hardware Discovery Tests
         run: |
           python -m pytest tests/runtime/test_dispatch.py -v
diff --git a/benchmarks/models/benchmark_h3_sigma_schedule.py b/benchmarks/models/benchmark_h3_sigma_schedule.py
new file mode 100644
index 000000000..45184db0e
--- /dev/null
+++ b/benchmarks/models/benchmark_h3_sigma_schedule.py
@@ -0,0 +1,352 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""Benchmark the h3_sigma_schedule operator across its backends (RFC #420).
+
+Operator-only microbenchmark: builds sigma grids for N in {25, 50, 1000,
+1000000} x shift in {3.0, 12.0} on three paths:
+
+* path A — CPU reference, grid built on CPU, outputs stay on CPU;
+* path B — CPU reference, grid built on CPU, sigmas and timesteps moved to
+  the target GPU via the operator's ``device`` argument (the registry default
+  path on every platform: build + host-to-device copy);
+* path C — Triton opt-in backend (semantic ``requested_backend`` or direct
+  construction), grid built on the device.
+
+B vs C is the comparison that matters when the consumer lives on the GPU; A
+is an auxiliary CPU baseline and A/C ratios must not be presented as a
+speedup under equal output conditions.
+
+Timing semantics (deliberately conservative): **per-call end-to-end host
+wall latency**. Each call is timed individually with ``time.perf_counter``
+around the whole ``op()`` call — including Python dispatch, host
+allocations, kernel launches, and the device path's single host
+synchronization (the deduplicated-length read) — and, for the GPU paths,
+one ``torch.cuda.synchronize()`` before starting each sample (so prior
+async work cannot leak into the window) and one after the call (so the
+call's device work is complete before the clock stops). Reported per case:
+raw per-call samples, mean, median, standard deviation, min, and max. The
+median is the headline number; mean and raw samples are recorded so
+outliers stay visible. No CUDA events are used, because they cannot see the
+host-side part of the call. Triton kernel compilation happens inside the
+pre-timing correctness gate (the gate's calls are this process's first
+Triton invocations): the gate's total wall time is reported once as
+``correctness_gate_wall_ms`` and no later call is labeled "first" or
+"compile". Timed samples start only after per-case warmup, so steady-state
+numbers exclude compilation by construction. The benchmark calls the op
+classes directly (registry bypassed for timing); registry-entry identity
+and correctness are pinned by tests/runtime/ and tests/backends/cuda/.
+
+Before any timing on a GPU host where the Triton backend is available, path C
+is verified bitwise against path A for every measured case (sigmas,
+timesteps, and num_model_evals); a mismatch aborts with exit code 2 and no
+performance numbers are produced.
+
+Exit codes: 0 on success; 2 on the pre-timing correctness gate; nonzero on
+invalid arguments, and on any Triton compile, launch, or runtime failure
+after the backend was confirmed available. Path B needs only torch and a
+device, so it is measured on every GPU host. Path C (and its gate) is
+skipped only for a *confirmed* absent backend — a missing Triton import on a
+GPU host — or recorded as unsupported on a HIP/ROCm build, where the
+NVIDIA-only kernels (inline PTX) refuse construction. Without any CUDA/HIP
+device (``torch.cuda.is_available()`` false) both B and C are skipped. The
+script runs from an uninstalled checkout (it bootstraps the repository root
+onto ``sys.path``).
+
+The grid is tiny (4 KB at N=1000), so GPU launch overhead may exceed the
+arithmetic — the numbers are what they are, and this benchmark does not
+assume the device path wins. N=1000000 is a dedup stress case, not a
+typical workload. No model, checkpoint, or tokenizer is loaded.
+
+Example:
+
+    python benchmarks/models/benchmark_h3_sigma_schedule.py --samples 100
+    CUDA_VISIBLE_DEVICES=0 python benchmarks/models/benchmark_h3_sigma_schedule.py \
+        --samples 100 --json /tmp/h3_sigma_bench.json
+"""
+
+from __future__ import annotations
+
+import argparse
+import json
+import statistics
+import sys
+import time
+from functools import partial
+from pathlib import Path
+
+sys.path.insert(0, str(Path(__file__).resolve().parents[2]))  # uninstalled checkout
+
+import torch  # noqa: E402
+
+_SIZES = [25, 50, 1000, 1000000]
+_SHIFTS = [3.0, 12.0]
+_SPEEDUP_NOTE = "speedup_b_over_c = latency(B) / latency(C); > 1 means C (Triton) is faster"
+
+
+def _positive_int(value: str) -> int:
+    try:
+        parsed = int(value)
+    except ValueError as exc:
+        raise argparse.ArgumentTypeError(f"expected an integer, got {value!r}") from exc
+    if parsed < 1:
+        raise argparse.ArgumentTypeError(f"expected a positive integer, got {value!r}")
+    return parsed
+
+
+def _int32_bits(tensor: torch.Tensor) -> list[int]:
+    return tensor.detach().contiguous().view(torch.int32).tolist()
+
+
+def _time_calls(call, samples: int, *, device_sync: bool) -> dict:
+    """Per-call end-to-end host wall latency; raw samples plus summary stats."""
+
+    raw_ms: list[float] = []
+    for _ in range(samples):
+        if device_sync:
+            torch.cuda.synchronize()  # no prior async work leaks into this window
+        start = time.perf_counter()
+        call()
+        if device_sync:
+            torch.cuda.synchronize()  # the call's device work is done before stop
+        raw_ms.append((time.perf_counter() - start) * 1e3)
+    return {
+        "samples_raw_ms": [round(value, 6) for value in raw_ms],
+        "mean_ms": statistics.fmean(raw_ms),
+        "median_ms": statistics.median(raw_ms),
+        "stdev_ms": statistics.stdev(raw_ms) if len(raw_ms) > 1 else 0.0,
+        "min_ms": min(raw_ms),
+        "max_ms": max(raw_ms),
+    }
+
+
+def _reference_op():
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    return NativeH3SigmaScheduleOp()
+
+
+def _time_reference(samples: int, warmup: int, *, device) -> dict[str, dict]:
+    # Path A when device is None (outputs stay on CPU); path B when device is
+    # "cuda" (same CPU build, then sigmas/timesteps moved by the operator).
+    op = _reference_op()
+    results = {}
+    for n in _SIZES:
+        for shift in _SHIFTS:
+            for _ in range(warmup):
+                op(n, shift=shift, device=device)
+            if device is not None:
+                torch.cuda.synchronize()
+            call = partial(op, n, shift=shift, device=device)
+            results[f"N={n},shift={shift:g}"] = _time_calls(
+                call, samples, device_sync=device is not None
+            )
+    return results
+
+
+def _verify_triton_matches_reference() -> float:
+    """Bitwise gate: path C must equal path A before any timing happens.
+
+    This gate's calls are the FIRST Triton invocations of the process — the
+    kernels are compiled here, not later. Returns the gate's wall time in ms
+    (compilation + all case comparisons) so the cold-start cost stays on the
+    record instead of being mislabeled somewhere else.
+    """
+
+    from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import (
+        H3SigmaScheduleCudaOp,
+    )
+
+    cpu_op = _reference_op()
+    gpu_op = H3SigmaScheduleCudaOp()
+    start = time.perf_counter()
+    for n in _SIZES:
+        for shift in _SHIFTS:
+            expected = cpu_op(n, shift=shift)
+            actual = gpu_op(n, shift=shift)
+            if (
+                _int32_bits(actual.sigmas.cpu()) != _int32_bits(expected.sigmas)
+                or _int32_bits(actual.timesteps.cpu()) != _int32_bits(expected.timesteps)
+                or actual.num_model_evals != expected.num_model_evals
+            ):
+                first_sigma = next(
+                    (
+                        idx
+                        for idx, (a, e) in enumerate(
+                            zip(_int32_bits(actual.sigmas.cpu()), _int32_bits(expected.sigmas))
+                        )
+                        if a != e
+                    ),
+                    None,
+                )
+                print(
+                    f"correctness gate FAILED at N={n}, shift={shift}: Triton result "
+                    f"differs from the CPU reference (first mismatching sigma index: "
+                    f"{first_sigma}); refusing to benchmark"
+                )
+                sys.exit(2)  # documented gate exit code; SystemExit(str) would exit 1
+    return (time.perf_counter() - start) * 1e3
+
+
+def _time_triton(samples: int, warmup: int) -> dict[str, dict]:
+    # The caller ran the correctness gate first, so every kernel has already
+    # been compiled and executed; no "first call" exists here to re-time and
+    # nothing in this function is labeled as compilation. Any failure below
+    # (launch, host read) propagates and fails the command.
+    from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import (
+        H3SigmaScheduleCudaOp,
+    )
+
+    op = H3SigmaScheduleCudaOp()
+
+    results = {}
+    for n in _SIZES:
+        for shift in _SHIFTS:
+            for _ in range(warmup):
+                op(n, shift=shift)
+            torch.cuda.synchronize()
+            call = partial(op, n, shift=shift)
+            results[f"N={n},shift={shift:g}"] = _time_calls(call, samples, device_sync=True)
+    return results
+
+
+def _summarize(report: dict) -> dict:
+    """Speedup B/C per case from medians and means; A medians for context."""
+
+    summary = {"definition": _SPEEDUP_NOTE, "cases": {}}
+    path_b = report.get("path_b_reference_cpu_build_then_copy_to_gpu")
+    path_c = report.get("path_c_triton_device_build")
+    # A path that was skipped or recorded as unsupported carries no per-case
+    # timings, so there is no ratio to compute (B alone is still reported).
+    if (
+        not path_b
+        or not path_c
+        or "skipped" in path_b
+        or "unsupported" in path_b
+        or "skipped" in path_c
+        or "unsupported" in path_c
+    ):
+        return summary
+    for key, case_b in path_b.items():
+        case_c = path_c[key]
+        summary["cases"][key] = {
+            "b_median_ms": case_b["median_ms"],
+            "c_median_ms": case_c["median_ms"],
+            "speedup_b_over_c_median": case_b["median_ms"] / case_c["median_ms"],
+            "speedup_b_over_c_mean": case_b["mean_ms"] / case_c["mean_ms"],
+            "separated_from_dispersion": abs(case_b["median_ms"] - case_c["median_ms"])
+            > (case_b["stdev_ms"] + case_c["stdev_ms"]),
+        }
+    return summary
+
+
+def main(argv: list[str] | None = None) -> int:
+    parser = argparse.ArgumentParser(description=__doc__)
+    parser.add_argument("--samples", type=_positive_int, default=100)
+    parser.add_argument("--warmup", type=_positive_int, default=5)
+    parser.add_argument("--json", default=None, help="optional output path")
+    args = parser.parse_args(argv)
+
+    has_gpu = torch.cuda.is_available()
+    report: dict = {
+        "operator": "h3_sigma_schedule",
+        "timing": (
+            "per-call end-to-end host wall latency; GPU paths sync before each "
+            "sample and after each call; Triton first-call compile excluded"
+        ),
+        "entry": "direct op construction; registry bypassed for timing (identity pinned by tests)",
+        "torch": torch.__version__,
+        "torch_cuda_runtime": torch.version.cuda,
+        "hip": torch.version.hip,
+        "triton": None,
+        "device": torch.cuda.get_device_name(0) if has_gpu else "cpu-only",
+        "n_gpu_devices": torch.cuda.device_count() if has_gpu else 0,
+        "samples": args.samples,
+        "warmup": args.warmup,
+        "sizes": _SIZES,
+        "shifts": _SHIFTS,
+        "stress_case_note": "N=1000000 is a dedup stress case, not a typical H3 workload",
+    }
+
+    print(
+        f"path A (reference, cpu build, cpu outputs): {args.samples} calls x {_SIZES} x {_SHIFTS}"
+    )
+    report["path_a_reference_cpu"] = _time_reference(args.samples, args.warmup, device=None)
+
+    if not has_gpu:
+        skip = "no CUDA/HIP device (torch.cuda.is_available() is False)"
+        report["path_b_reference_cpu_build_then_copy_to_gpu"] = {"skipped": skip}
+        report["path_c_triton_device_build"] = {"skipped": skip}
+        print("paths B and C: skipped — no CUDA/HIP device in this process")
+    else:
+        try:
+            import triton
+
+            report["triton"] = triton.__version__
+        except ImportError as exc:
+            # Path B is the registry default path and needs only torch plus a
+            # device, so a missing Triton skips path C alone.
+            skip = f"triton import failed on a GPU host: {exc}"
+            print(f"path B (reference, cpu build, outputs moved to gpu): {args.samples} calls")
+            report["path_b_reference_cpu_build_then_copy_to_gpu"] = _time_reference(
+                args.samples, args.warmup, device="cuda"
+            )
+            report["path_c_triton_device_build"] = {"skipped": skip}
+            print(f"path C: skipped — triton missing ({exc})")
+        else:
+            if torch.version.hip is not None:
+                # Triton may import on a HIP host, but the backend is NVIDIA-only
+                # (inline PTX) and refuses construction: record that instead of
+                # letting the ImportError escape from inside the correctness gate.
+                unsupported = (
+                    "HIP/ROCm build: the Triton backend is NVIDIA-only (inline PTX "
+                    "div.rn.f32) and refuses construction; the bitwise correctness "
+                    "gate was not run"
+                )
+                print(f"path B (reference, cpu build, outputs moved to gpu): {args.samples} calls")
+                report["path_b_reference_cpu_build_then_copy_to_gpu"] = _time_reference(
+                    args.samples, args.warmup, device="cuda"
+                )
+                report["path_c_triton_device_build"] = {"unsupported": unsupported}
+                print("path C: unsupported — NVIDIA-only backend on a HIP/ROCm build")
+            else:
+                print("verifying path C against path A bitwise before timing...")
+                gate_ms = _verify_triton_matches_reference()
+                report["correctness_gate_wall_ms"] = gate_ms
+                print(
+                    "correctness gate passed "
+                    f"(includes Triton kernel compilation: {gate_ms:.1f} ms wall, "
+                    "reported once, excluded from all timed samples)"
+                )
+
+                print(f"path B (reference, cpu build, outputs moved to gpu): {args.samples} calls")
+                report["path_b_reference_cpu_build_then_copy_to_gpu"] = _time_reference(
+                    args.samples, args.warmup, device="cuda"
+                )
+                print(f"path C (triton, device build): {args.samples} calls")
+                report["path_c_triton_device_build"] = _time_triton(args.samples, args.warmup)
+
+    report["summary"] = _summarize(report)
+
+    for section in (
+        "path_a_reference_cpu",
+        "path_b_reference_cpu_build_then_copy_to_gpu",
+        "path_c_triton_device_build",
+    ):
+        for key, value in report[section].items():
+            if isinstance(value, dict) and "median_ms" in value:
+                print(f"{section:>44s} {key:>20s}: {value['median_ms']:.4f} ms/call (median)")
+    for key, case in report["summary"]["cases"].items():
+        separated = case["separated_from_dispersion"]
+        note = "separated from dispersion" if separated else "within dispersion"
+        print(f"speedup B/C {key:>20s}: {case['speedup_b_over_c_median']:.2f}x ({note})")
+
+    if args.json:
+        with open(args.json, "w", encoding="utf-8") as handle:
+            json.dump(report, handle, indent=2)
+        print(f"wrote {args.json}")
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/docs/.nav.yml b/docs/.nav.yml
index 3a383da15..6e1c7357c 100644
--- a/docs/.nav.yml
+++ b/docs/.nav.yml
@@ -32,6 +32,7 @@ nav:
       - operators/det-gemm.md
       - operators/embedding.md
       - MiniMax-H3:
+        - operators/h3-sigma-schedule.md
         - operators/h3-timestep-sinusoid.md
         - operators/h3-timestep-mlp.md
         - operators/h3-adaln-projection.md
diff --git a/docs/architecture/runtime-dispatch.md b/docs/architecture/runtime-dispatch.md
index c1321a496..b3ee8b9c0 100644
--- a/docs/architecture/runtime-dispatch.md
+++ b/docs/architecture/runtime-dispatch.md
@@ -37,6 +37,15 @@ the legacy SM90 LogP backend when `RL_KERNEL_ENABLE_EXPERIMENTAL_SM90_LOGP=1` is
 set. The fused linear logp SM90 backend is gated separately and remains the
 default linear logp backend when the extension is built on Hopper.
 
+## H3 Sigma Schedule
+
+`sigma_schedule_h3` lists only the PyTorch reference on every platform, CUDA
+included; the NVIDIA Triton backend is opt-in through the semantic
+`requested_backend="rlkernel.h3_sigma_schedule.triton"` or direct construction,
+because its device-side build measured 2.5–3.2x slower than CPU construction
+plus transfer at typical H3 sizes (PR #566 evidence). See
+[H3 Sigma Schedule](../operators/h3-sigma-schedule.md).
+
 ## Relevant Files
 
 - `rl_engine/runtime/registry.py`
diff --git a/docs/operators/h3-sigma-schedule.md b/docs/operators/h3-sigma-schedule.md
new file mode 100644
index 000000000..e1ac3e9f5
--- /dev/null
+++ b/docs/operators/h3-sigma-schedule.md
@@ -0,0 +1,231 @@
+# H3 Sigma Schedule
+
+The MiniMax-H3 rectified-flow sigma grid (RFC #420, `h3_sigma_schedule`):
+`linspace(1, 0, N)` in fp32, the exponential shift
+`shift·s / (1 + (shift−1)·s)`, `unique_consecutive` deduplication, and
+`timesteps = 1 − sigmas[:-1]`. Video uses `shift=12`, audio `shift=3`; the two
+grids are independent per-request inputs, never a shared step index. The
+default backend on every platform is the PyTorch reference (CPU construction,
+outputs copied to the requested device); a device-side NVIDIA Triton backend
+is available as an explicit opt-in.
+
+## Entry Point
+
+```python
+from rl_engine.runtime.registry import kernel_registry
+
+op = kernel_registry.get_op("sigma_schedule_h3", device="cuda")   # PyTorch reference
+schedule = op(25, shift=12.0, device="cuda")   # device= selects output placement only
+schedule.sigmas          # fp32 [M], strictly decreasing, terminal exactly 0.0
+schedule.timesteps       # fp32 [M-1] = 1 - sigmas[:-1]
+schedule.num_model_evals # M - 1 (deduplicated length drives the count)
+```
+
+`get_op` returns the PyTorch reference on every platform, CUDA included: the
+grid is built on CPU and both outputs are moved to `device`. When `device` is
+omitted, the reference returns CPU tensors while the opt-in Triton backend
+builds on `cuda` by default — callers should always pass `device=` explicitly.
+Both per-backend defaults are intentional and pinned by the existing tests;
+the default-backend switch did not change them.
+
+## Opt-in: device-side Triton backend
+
+Two explicit routes select `H3SigmaScheduleCudaOp`; neither is reachable
+through a legacy `get_op` candidate list. The semantic path resolves with
+provenance (`requested_backend` `rlkernel.h3_sigma_schedule.triton`; the
+reference is `.reference`):
+
+```python
+from rl_engine.runtime.registry import kernel_registry
+from rl_engine.runtime.semantic_registry import OperatorRequirements
+
+session = kernel_registry.semantic.session()
+resolution = session.resolve(
+    semantic_op="sigma_schedule_h3",
+    requested_backend="rlkernel.h3_sigma_schedule.triton",
+    target="rollout",
+    requirements=OperatorRequirements(device="cuda", dtype="float32"),
+)
+op = session.instantiate(resolution)
+provenance = session.instance_provenance(resolution, op)
+```
+
+Or construct the class directly:
+
+```python
+from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import (
+    H3SigmaScheduleCudaOp,
+)
+
+op = H3SigmaScheduleCudaOp()   # raises ImportError without Triton or on HIP/ROCm
+schedule = op(25, shift=12.0, device="cuda")
+```
+
+Both routes produce the same bytes as the default reference path (the CUDA
+suite asserts this; the byte identity was verified on x86_64 Linux hosts).
+Whether it extends to ARM hosts for the extreme shifts (infinite,
+fp32-overflowing, underflowing) is unverified — the device fast path fills
+those grids with the x86 CPU oracle's NaN bits (see
+[Known Limitations](#known-limitations)). Opting in only moves the
+arithmetic onto the device.
+
+## Backends
+
+| Backend | Wrapper | Native symbol | Status |
+| --- | --- | --- | --- |
+| CUDA (Triton) | `rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule.H3SigmaScheduleCudaOp` | 3 Triton kernels (grid / dedup scan / timesteps) | **Opt-in** (semantic `requested_backend` or direct construction; not a legacy `get_op` candidate). Validated on RTX 4090D (torch 2.5.1+cu121, Triton 3.1.0): bitwise-identical to the pinned upstream oracle across the full device suite |
+| ROCm | — | — | **CUDA only.** The ROCm column stays open. The inline PTX `div.rn.f32` is NVIDIA-only, so the backend refuses construction on HIP; ROCm dispatches the PyTorch reference. |
+| PyTorch reference | `rl_engine.reference.minimax_h3.sigma_schedule.NativeH3SigmaScheduleOp` | `torch.linspace` + `unique_consecutive` | **Default on every platform** (byte-frozen oracle; fixture generated on Linux CPU under torch 2.14.1, reproduced on 2.4.1 and 2.5.1). Builds on CPU and copies the outputs to the requested device |
+
+## Tensor Contract
+
+| Argument | Shape | Dtype | Requirements |
+| --- | --- | --- | --- |
+| `num_inference_steps` | scalar | int | `>= 2`; terminal zero included in the count |
+| `shift` | scalar | python float | `> 0` (video 12.0 / audio 3.0) |
+| `device` | — | — | Output placement. The default reference accepts any device (builds on CPU, copies to `device`); the opt-in Triton backend requires an NVIDIA CUDA device (refuses construction on HIP/ROCm) |
+| → `sigmas` | `[M]`, `M ≤ N` | float32 | strictly decreasing; `sigmas[0] == 1.0` and `sigmas[-1] == 0.0` exactly for released shifts |
+| → `timesteps` | `[M-1]` | float32 | `1 − sigmas[:-1]`, strictly increasing from 0.0 |
+| → `num_model_evals` | scalar | int | `M − 1` |
+
+## Dispatch Behavior
+
+The legacy candidate list for `sigma_schedule_h3` is `[PyTorch reference]` on
+every platform — CUDA, ROCm, MUSA, NPU and CPU alike — so `get_op` always
+builds the grid on CPU and moves the outputs to the requested device. This is a
+deliberate default (review 2026-10-25, PR #566): the 4090D measurements below
+show the device-side build is 2.5–3.2x slower at typical H3 sizes, and no
+consumer requires on-device construction. The Triton backend is not a legacy
+candidate anywhere; it is selected only through the semantic
+`requested_backend="rlkernel.h3_sigma_schedule.triton"` or by direct
+construction (see Opt-in above). Its construction-time guards are unchanged —
+`H3SigmaScheduleCudaOp()` raises `ImportError` when Triton is not importable
+or on a HIP/ROCm build, so an opt-in that cannot be honored fails explicitly
+(semantic `instantiate` raises `OperatorInstantiationError`) instead of
+silently swapping arithmetic (see
+[Runtime Dispatch](../architecture/runtime-dispatch.md)).
+
+The two selection layers differ in fallback semantics and device scope:
+
+- Candidate-list fallback belongs to the legacy `kernel_registry.get_op` path
+  only: it moves to the next candidate when a backend cannot be constructed.
+  For `sigma_schedule_h3` every platform list holds the reference alone, so
+  there is nothing to fall back from or to.
+- The semantic path never falls back.
+  `session.resolve(requested_backend="rlkernel.h3_sigma_schedule.triton")`
+  requires that exact backend to be registered and to match the request
+  (declared `supported_devices={"cuda"}`, `fallback_policy=ERROR`). When
+  Triton is not importable, resolution still succeeds but
+  `session.instantiate` raises `OperatorInstantiationError`
+  (`"triton is required"`); the reference is not substituted.
+- The semantic reference descriptor declares
+  `supported_devices={"cpu", "cuda", "rocm"}` and `fallback_policy=ERROR` —
+  it does not cover MUSA or NPU, whereas the legacy `get_op` lists serve the
+  reference on those platforms too.
+
+## Accuracy
+
+The acceptance oracle is the pinned fixture
+`tests/reference/minimax_h3/h3_sigma_schedule_upstream_fixture.json`,
+generated by executing the original upstream
+`MiniMaxH3Scheduler.set_timesteps` (diffusers commit `f53d552`, blob
+`ca69ae6a`); six cases N∈{2,4,25} × shift∈{3,12} are compared as fp32 bit
+patterns. The device kernels reproduce the pinned CPU construction bit law:
+fp32 step, two-sided fp64 accumulation with single rounding, pre-rounded
+python-float scalars, correctly-rounded division via libdevice `div_rn` for
+the linspace step and inline PTX `div.rn.f32` for the shift transform
+(on Triton 3.0.0 / RTX 4090D the
+`tl.fdiv(..., ieee_rounding=True)` flag and the `/` operator were measured
+bit-identical and NOT correctly rounded, so they are not used),
+`enable_fp_fusion=False` on floating-point launches, and IEEE-equality dedup
+(NaN rows are kept, matching `torch.unique_consecutive`). NaN and near-zero
+parity follows the torch-CPU oracle (validated on RTX 4090D, independent
+audit 2026-10-16): a NaN `fl32(shift)` fills the grid with its own quieted
+NaN bits — sign included, so `-NaN` yields `0xffc00000` and `+NaN`
+`0x7fc00000` (host-side scalar fast path; the device kernel's `0x7fffffff`
+canonicalization would otherwise differ); an infinite `fl32(shift)` makes
+every element an invalid operation, filled with the x86 default quiet NaN
+`0xffc00000`; a subnormal `fl32(shift)` (e.g. `1e-45` → the minimum
+subnormal `2^-149`) takes the normal device path with a `+inf` first element
+and subnormal quotients (upstream keeps 10 of 25 rows at `1e-45`); a shift
+whose `fl32` underflows to `+0.0` (e.g. `1e-46`) makes element 0 the invalid
+`+0.0/+0.0`, canonicalized in-kernel to `0xffc00000`. Odd inputs follow
+upstream parity: float `N` truncates via `int()`, non-finite or
+fp32-overflowing shifts yield NaN grids, extreme finite shifts can collapse
+the grid (e.g. `1e30` → `[1.0, 0.0]`).
+
+## Performance Notes
+
+```bash
+python benchmarks/models/benchmark_h3_sigma_schedule.py --samples 100
+```
+
+Measures **per-call end-to-end host wall latency** on three paths — A:
+reference built on CPU, outputs on CPU; B: reference built on CPU, sigmas and
+timesteps moved to the GPU via `device="cuda"` (the registry default path on
+every platform); C: the opt-in Triton backend building on the device. Each call is
+timed individually (GPU paths synchronize before each sample and after each
+call); raw samples, mean/median/stdev/min/max are reported per case, and the
+median is the headline number. Before any timing on a GPU host the script
+verifies path C bitwise against path A for every measured case (exit 2 on
+mismatch); Triton compilation happens inside that gate and its wall time is
+recorded once as `correctness_gate_wall_ms`, outside all timed samples. The
+script runs from an uninstalled checkout. The grid is tiny (≤4 KB for
+N=1000): launch and host-sync overhead may well exceed the arithmetic — the
+benchmark reports what is measured, it does not assume the device path wins.
+N=1000000 is a dedup stress case, not a typical workload.
+
+Measured on RTX 4090D (torch 2.5.1+cu121, Triton 3.1.0, 100 samples/case):
+at N=25/50/1000 the device path C is 2.5–3.2x slower than B (B/C median
+0.315–0.403, every case separated from dispersion). C wins only at the N=1e6
+dedup stress case: 51.98x at shift=12 (separated), while shift=3 is 7.9x and
+within dispersion, so it is not claimed. The N=1e6 CPU medians are noisy
+(B stdev ≈ 44 ms at shift=12), so the 51.98x ratio passes the dispersion
+check only by a small margin. See Known Limitations and the raw JSON, CUDA
+test results, source hashes, and reproduction commands in the
+[4090D evidence report](https://github.com/RL-Align/RL-Kernel/tree/test-h3/reports/experiments/h3-sigma-schedule).
+
+These numbers are the basis for the default: the reference path (B) is the
+legacy `get_op` backend on CUDA because it is 2.5–3.2x faster at every typical
+H3 size and produces identical bytes. The trade reverses only at the N=1e6
+dedup stress case — at shift=12 the reference median is 48.37 ms against
+0.93 ms for Triton (51.98x), so a consumer building grids of that size should
+opt into the Triton backend explicitly; it is not a released-model workload.
+
+## Tests
+
+```bash
+python -m pytest tests/reference/minimax_h3 tests/runtime/test_h3_sigma_schedule_dispatch.py -v
+python -m pytest tests/backends/cuda/test_h3_sigma_schedule_cuda.py -v   # NVIDIA CUDA hardware
+```
+
+The device suite also carries the upstream-parity edge matrix (NaN/±inf and
+extreme shifts, float-`N` truncation) against the CPU reference, which is
+itself bit-identical to the executed upstream method on those inputs.
+
+## Known Limitations
+
+- Validated on an x86_64 host with NVIDIA RTX 4090D only (driver 580, torch 2.5.1+cu121,
+  Triton 3.1.0); other GPUs/drivers/Triton versions are not validated. On
+  Triton 3.0.0 the `tl.fdiv(..., ieee_rounding=True)` flag was measured NOT
+  correctly rounded, which is why the linspace step uses libdevice `div_rn`
+  and the shift transform uses inline PTX `div.rn.f32`.
+- Invalid-operation NaN bits are pinned to that x86 CPU oracle (`0xffc00000`).
+  A live CPU reference on ARM can produce `0x7fc00000` instead for infinite,
+  fp32-overflowing, or underflowing shifts. Bitwise parity for those edge cases
+  is not portable across host architectures; the released shifts (3 and 12)
+  do not take these paths. NVIDIA GPUs on ARM hosts have not been validated.
+- **CUDA only.** The ROCm column stays open: the Triton backend refuses
+  construction on HIP because its division is emitted as inline NVIDIA PTX;
+  ROCm dispatches the PyTorch reference.
+- Measured end-to-end latency on the 4090D: for the typical H3 sizes
+  (N = 25/50/1000) the device-side Triton build is 2.5–3.2x SLOWER than
+  building on CPU and copying to the GPU (B/C median 0.315–0.403, all separated
+  from dispersion) — which is why it is opt-in rather than the default. The
+  device path wins only at the N = 1e6 dedup stress case: 51.98x at shift=12
+  (separated) and 7.9x at shift=3 (within dispersion, not claimed); the default
+  reference path is correspondingly slower there (48.37 ms vs 0.93 ms at
+  shift=12). These numbers are single-operator microbenchmark results on one
+  card and say nothing about whole-model speed.
+- `N` beyond 2^31 is not supported (int32 indexing); the shift arithmetic is
+  internal-fp64, which is slow on consumer GPUs but irrelevant at these sizes.
diff --git a/reports/experiments/h3-sigma-schedule/README.md b/reports/experiments/h3-sigma-schedule/README.md
new file mode 100644
index 000000000..80b076557
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/README.md
@@ -0,0 +1,178 @@
+# H3 sigma schedule: RTX 4090D evidence
+
+These are historical operator measurements from October 16–17, 2026,
+rechecked against candidate commit `374488b` on October 21. No new GPU run
+was performed during the source-binding check.
+
+## Correctness and source identity
+
+The final NVIDIA closing run (`run-20261017-002253-9749`) produced
+**34 passed, 1 skipped, 0 failures/errors**. The skipped device-guard test
+requires two GPUs; this host had one. [CUDA JUnit](cuda-4090d.xml) preserves
+all outcomes; its hostname attribute was removed and the XML reserialized.
+
+[Source provenance](source-provenance.json) records SHA256 hashes for the
+tested archive, selected source files, and included results. The reference,
+CUDA backend, fixture and CPU reference test in the final closing snapshot are
+byte-identical to those files in `374488b` and to the current branch.
+
+The dispatch test, the CUDA test and the benchmark docstring were revised
+after the 4090D runs for the review-driven default backend change (the legacy
+`sigma_schedule_h3` candidate list is now reference-only on CUDA; the Triton
+backend is opt-in through the semantic `requested_backend` or direct
+construction). Those edits touch candidate order, test selection logic and
+prose only: every kernel bit assertion is unchanged, and the CUDA suite gained
+an assertion that the default reference path matches the Triton path bit for
+bit. No GPU run backed the revised tests at the time; the SM90 (H800) run
+below now does. `source-provenance.json` has been refreshed accordingly: its
+`cuda_validation` block keeps the historical `374488b` hashes of the
+4090D-tested snapshot, and the new `sm90_validation` block records the hashes
+at the SM90-tested commit (`40070d3`), the post-run changes, and the SHA256
+of every included SM90 artifact.
+
+The performance run (`run-20261016-235221-8055`) predates the final HIP
+rejection guard. Its reference and benchmark are byte-identical to the
+candidate; CUDA kernels and the scalar helper have identical ASTs. The
+forward method differs only in the error text for a rejected non-CUDA
+device. The final NVIDIA correctness run tested the updated CUDA file.
+
+Hardware/software: one NVIDIA GeForce RTX 4090D, x86_64 Linux, driver
+580.76.05, Python 3.12.3, torch 2.5.1+cu121, CUDA runtime 12.1, Triton 3.1.0.
+
+## Comparable latency
+
+[Raw benchmark JSON](benchmark-4090d.json) is copied without modification.
+It contains 100 samples per case and path (2,400 samples total), after
+five warmup calls. Path A builds on CPU and leaves outputs there; path B
+builds on CPU and copies both outputs to CUDA (the registry default path);
+path C constructs on CUDA (the Triton opt-in backend).
+Only B/C compares equal output placement. Timing is per-call host wall
+latency with synchronization before and after each GPU sample; correctness
+checking and compilation happen before timed samples.
+
+| Workload | B median (ms) | C median (ms) | B/C |
+| --- | ---: | ---: | ---: |
+| N=25, shift=3 | 0.04158 | 0.11552 | 0.360 |
+| N=25, shift=12 | 0.04188 | 0.13293 | 0.315 |
+| N=50, shift=3 | 0.04523 | 0.11281 | 0.401 |
+| N=50, shift=12 | 0.04495 | 0.11351 | 0.396 |
+| N=1000, shift=3 | 0.04609 | 0.11484 | 0.401 |
+| N=1000, shift=12 | 0.04672 | 0.11597 | 0.403 |
+| N=1000000, shift=3 | 7.91859 | 1.00316 | 7.894 |
+| N=1000000, shift=12 | 48.37110 | 0.93057 | 51.980 |
+
+C is approximately 2.5–3.2 times slower at the typical sizes. N=1000000
+is a deduplication stress case: the shift=12 gain exceeds the benchmark's
+dispersion check; shift=3 does not and is not claimed as a reliable gain.
+These are single-operator results, with no whole-model speedup claim.
+
+## SM90 (H800) evidence
+
+Collected on 2026-10-26 on a rented SM90 host (one **NVIDIA H800 PCIe**, per
+`nvidia-smi`), with the same three pytest invocations and the same benchmark
+command as above, at tested commit
+`40070d37495d193e2d8764837321d3a68dad9483` (`40070d3`). The JUnit XML for each
+run, the benchmark JSON, the environment snapshot and the full collection
+report (which embeds the raw console logs verbatim) are in
+[sm90-h800/](sm90-h800/). The standalone console `.log` files are excluded by
+the repository-wide `*.log` ignore rule — as in the 4090D directory; their
+hashes are recorded in `source-provenance.json` (`original_server_sha256`).
+GPU UUID, container hostname and `/root/…` paths
+were redacted: the JUnit `hostname` attribute was removed (as for the 4090D
+XML, which keeps the historical `/root/…` skip-message paths — the SM90 files
+additionally replace them with `REPO_ROOT` / `EVIDENCE_DIR` /
+`MINICONDA_PYTHON` tokens). `benchmark-h800.json` and `env.txt` required no
+redaction; a final newline was appended to the three XMLs and the JSON to
+satisfy the repository's end-of-file hook. `source-provenance.json` records
+both the committed (redacted) and the original server-side SHA256 of every
+file.
+
+Hardware/software: NVIDIA H800 PCIe (compute capability 9.0), driver
+580.82.07, x86_64 Linux 5.15.0-78-generic, 2× Intel Xeon Platinum 8458P,
+Python 3.12.3, torch 2.5.1+cu124, CUDA runtime 12.4, Triton 3.1.0 — the same
+Triton as the 4090D run; torch differs only in the CUDA build (cu124 vs
+cu121), the driver is 580.82.07 vs 580.76.05.
+
+| Run | Scope (`-v -rs`) | Collected | Passed | Skipped | Failed |
+| --- | --- | ---: | ---: | ---: | ---: |
+| A | reference + dispatch + CUDA suites | 69 | 67 | 2 | 0 |
+| B | CUDA + dispatch subset | 48 | 47 | 1 | 0 |
+| C | the two registry tests introduced after the 4090D runs | 2 | 2 | 0 | 0 |
+
+Skips, with the reasons printed by `-rs`: the optional Diffusers parity test
+(`diffusers` not installed on the host; the pinned fixture test passed) and
+the multi-GPU device-guard test (the host has one GPU) — the same test, for
+the same reason, as on the 4090D. Run C was the first hardware execution of
+`test_public_entry_defaults_to_reference_and_matches_triton_bits` and
+`test_public_entry_opt_in_selects_triton_and_reports_provenance`; both
+passed — on SM90 the legacy `get_op(device="cuda")` reference path and the
+directly constructed Triton backend produce identical sigma/timestep bits.
+
+Versus the 4090D record (34 passed / 1 skipped): one more CUDA test passed
+because the default-backend change split the registry-identity test into
+two; no test that passed on the 4090D failed here; the single skip is the
+same test for the same reason.
+
+Benchmark (100 samples, 5 warmups, [raw JSON](sm90-h800/benchmark-h800.json)):
+the pre-timing bitwise gate (path C vs path A) passed for all 8 cases; the
+gate took 1143.6 ms wall in total (Triton kernel compilation included),
+reported once and excluded from timed samples.
+
+| Workload | B median (ms) | C median (ms) | B/C |
+| --- | ---: | ---: | ---: |
+| N=25, shift=3 | 0.0551 | 0.0926 | 0.60x |
+| N=25, shift=12 | 0.0554 | 0.0913 | 0.61x |
+| N=50, shift=3 | 0.0556 | 0.0918 | 0.61x |
+| N=50, shift=12 | 0.0554 | 0.0887 | 0.62x |
+| N=1000, shift=3 | 0.0598 | 0.0907 | 0.66x |
+| N=1000, shift=12 | 0.0609 | 0.0892 | 0.68x |
+| N=1000000, shift=3 | 5.5054 | 1.3377 | 4.12x |
+| N=1000000, shift=12 | 5.8109 | 1.3374 | 4.34x |
+
+All eight ratios pass the benchmark's dispersion check. These latency numbers
+are supplementary only and not comparable with the 4090D table: the H800 has
+reduced FP64 throughput (the Triton kernel evaluates its intermediates in
+fp64), and paths A/B run on a different host CPU (at N=1e6 the CPU path is
+about 5.5 ms here versus about 48 ms on the 4090D host). On this host the
+device build is 1.5–1.65x slower than CPU build plus copy at N=25/50/1000
+and 4.1–4.3x faster at the N=1e6 dedup stress case — directionally the same
+default-relevant conclusion as the 4090D, at a smaller margin.
+
+Post-run changes: after the tested commit `40070d3`, commit `ace9c20`
+("fix(h3): address CodeRabbit review on sigma schedule benchmark and docs")
+modified only the benchmark's GPU-without-Triton and HIP/ROCm branches, its
+docstring, and documentation. The H800 run executed the NVIDIA + Triton
+branch, whose logic, timing order, sample counts and JSON keys that commit
+leaves unchanged; the new branches were verified by CPU-only execution,
+`_summarize` simulations and static review, and have not run on GPU or HIP
+hardware.
+
+## Reproduction
+
+From a checkout with the declared project dependencies installed, run:
+
+```bash
+python -m pytest tests/reference/minimax_h3 tests/runtime/test_h3_sigma_schedule_dispatch.py -q
+python -m pytest tests/backends/cuda/test_h3_sigma_schedule_cuda.py -v
+python benchmarks/models/benchmark_h3_sigma_schedule.py --samples 100 --warmup 5 --json /tmp/h3-sigma.json
+```
+
+The second command and benchmark paths B/C require NVIDIA CUDA hardware
+and Triton. The CPU fixture needs neither Diffusers nor network access.
+
+## Evidence limits
+
+ROCm is unsupported by this device backend, which uses inline NVIDIA PTX.
+Other GPUs, ARM-hosted NVIDIA systems, multi-GPU behavior, and full-model
+execution are unvalidated. Invalid-operation NaN payloads follow the pinned
+x86 CPU convention; an ARM live CPU oracle may differ for extreme shifts.
+
+The historical broad dispatch suite also recorded two attention failures
+(`test_registered_backend_resolves_with_provenance` and
+`test_implementation_kind_policy_filters_without_marking_fallback`). The
+recorded baseline/candidate A/B runs contained the same failures. The H3
+CUDA result above is not an all-green historical pipeline claim.
+
+The existing Actions workflow runs on `main` and `test`; a PR targeting
+`test-h3` has no automatic coverage from it. CPU checks for this submission
+are reported separately from the historical GPU evidence.
diff --git a/reports/experiments/h3-sigma-schedule/benchmark-4090d.json b/reports/experiments/h3-sigma-schedule/benchmark-4090d.json
new file mode 100644
index 000000000..4aee5d792
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/benchmark-4090d.json
@@ -0,0 +1,2708 @@
+{
+  "operator": "h3_sigma_schedule",
+  "timing": "per-call end-to-end host wall latency; GPU paths sync before each sample and after each call; Triton first-call compile excluded",
+  "entry": "direct op construction; registry bypassed for timing (identity pinned by tests)",
+  "torch": "2.5.1+cu121",
+  "torch_cuda_runtime": "12.1",
+  "hip": null,
+  "triton": "3.1.0",
+  "device": "NVIDIA GeForce RTX 4090 D",
+  "n_gpu_devices": 1,
+  "samples": 100,
+  "warmup": 5,
+  "sizes": [
+    25,
+    50,
+    1000,
+    1000000
+  ],
+  "shifts": [
+    3.0,
+    12.0
+  ],
+  "stress_case_note": "N=1000000 is a dedup stress case, not a typical H3 workload",
+  "path_a_reference_cpu": {
+    "N=25,shift=3": {
+      "samples_raw_ms": [
+        0.028618,
+        0.025094,
+        0.026226,
+        0.025433,
+        0.023674,
+        0.025608,
+        0.026569,
+        0.02386,
+        0.025179,
+        0.025492,
+        0.023644,
+        0.025481,
+        0.025216,
+        0.02351,
+        0.025377,
+        0.025131,
+        0.023674,
+        0.025317,
+        0.026468,
+        0.023615,
+        0.025317,
+        0.026006,
+        0.023726,
+        0.02503,
+        0.025183,
+        0.023499,
+        0.025332,
+        0.035562,
+        0.02487,
+        0.024267,
+        0.024058,
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+        0.023644,
+        0.023521,
+        0.02354,
+        0.023488,
+        0.023488,
+        0.023372,
+        0.023488,
+        0.0236,
+        0.023458,
+        0.02351,
+        0.023525,
+        0.023305,
+        0.023544,
+        0.023521,
+        0.023507,
+        0.023406,
+        0.023589,
+        0.023495,
+        0.023577,
+        0.023488,
+        0.023976,
+        0.025813,
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+        0.023533,
+        0.036407,
+        0.024244,
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+        0.031028,
+        0.02424,
+        0.026822,
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+        0.024289,
+        0.024002,
+        0.023872,
+        0.024028,
+        0.02367,
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+        0.024196,
+        0.02411,
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+        0.024144,
+        0.024449,
+        0.024144,
+        0.024281,
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+        0.024177,
+        0.024013,
+        0.024106,
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+        0.024132,
+        0.024006,
+        0.023987,
+        0.025552,
+        0.02617,
+        0.027087,
+        0.024132,
+        0.024322,
+        0.024095,
+        0.024408,
+        0.024185,
+        0.038289,
+        0.024766,
+        0.024401
+      ],
+      "mean_ms": 0.024801157414913177,
+      "median_ms": 0.024102628231048584,
+      "stdev_ms": 0.002426409127135147,
+      "min_ms": 0.023305416107177734,
+      "max_ms": 0.03828853368759155
+    },
+    "N=25,shift=12": {
+      "samples_raw_ms": [
+        0.025388,
+        0.024661,
+        0.024199,
+        0.024106,
+        0.024032,
+        0.024095,
+        0.023961,
+        0.024367,
+        0.02398,
+        0.024121,
+        0.025757,
+        0.024423,
+        0.024091,
+        0.024192,
+        0.023857,
+        0.024155,
+        0.023976,
+        0.024021,
+        0.023849,
+        0.024058,
+        0.024099,
+        0.023987,
+        0.023998,
+        0.037283,
+        0.024822,
+        0.02462,
+        0.024803,
+        0.024412,
+        0.024524,
+        0.024233,
+        0.024229,
+        0.024218,
+        0.024095,
+        0.024423,
+        0.024155,
+        0.024099,
+        0.024103,
+        0.024009,
+        0.023931,
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+        0.024285,
+        0.023969,
+        0.024039,
+        0.023901,
+        0.024002,
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+        0.02392,
+        0.023972,
+        0.02411,
+        0.023957,
+        0.02398,
+        0.023976,
+        0.024054,
+        0.023913,
+        0.037011,
+        0.024766,
+        0.024602,
+        0.024263,
+        0.024226,
+        0.024088,
+        0.024229,
+        0.023842,
+        0.024121,
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+        0.023838,
+        0.024121,
+        0.023969,
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+        0.023842,
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+        0.023726,
+        0.024162,
+        0.023812,
+        0.02392,
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+        0.023883,
+        0.024166,
+        0.024043,
+        0.024058,
+        0.023898,
+        0.023834,
+        0.023946,
+        0.023872,
+        0.03672,
+        0.024613,
+        0.024386,
+        0.024546,
+        0.024762,
+        0.023898,
+        0.023901,
+        0.02389,
+        0.024419,
+        0.024404,
+        0.02386,
+        0.023846,
+        0.024121,
+        0.023954,
+        0.023972,
+        0.023995
+      ],
+      "mean_ms": 0.024525783956050873,
+      "median_ms": 0.02405792474746704,
+      "stdev_ms": 0.0022290060888030773,
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+      },
+      "N=1000000,shift=3": {
+        "b_median_ms": 7.918586954474449,
+        "c_median_ms": 1.003161072731018,
+        "speedup_b_over_c_median": 7.893634601387383,
+        "speedup_b_over_c_mean": 47.80501506692969,
+        "separated_from_dispersion": false
+      },
+      "N=1000000,shift=12": {
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+        "c_median_ms": 0.9305663406848907,
+        "speedup_b_over_c_median": 51.98027598409909,
+        "speedup_b_over_c_mean": 52.640332591594216,
+        "separated_from_dispersion": true
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/reports/experiments/h3-sigma-schedule/cuda-4090d.xml b/reports/experiments/h3-sigma-schedule/cuda-4090d.xml
new file mode 100644
index 000000000..a1de68e48
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/cuda-4090d.xml
@@ -0,0 +1,2 @@
+<?xml version='1.0' encoding='utf-8'?>
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diff --git a/reports/experiments/h3-sigma-schedule/sm90-h800/benchmark-h800.json b/reports/experiments/h3-sigma-schedule/sm90-h800/benchmark-h800.json
new file mode 100644
index 000000000..ed2a0dfe1
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/sm90-h800/benchmark-h800.json
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+      "min_ms": 1.333683729171753,
+      "max_ms": 1.3510845601558685
+    }
+  },
+  "summary": {
+    "definition": "speedup_b_over_c = latency(B) / latency(C); > 1 means C (Triton) is faster",
+    "cases": {
+      "N=25,shift=3": {
+        "b_median_ms": 0.0551324337720871,
+        "c_median_ms": 0.09256601333618164,
+        "speedup_b_over_c_median": 0.5956012556342563,
+        "speedup_b_over_c_mean": 0.5994931584326411,
+        "separated_from_dispersion": true
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+      "N=25,shift=12": {
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+        "c_median_ms": 0.09125098586082458,
+        "speedup_b_over_c_median": 0.6070626658501735,
+        "speedup_b_over_c_mean": 0.6063143397870051,
+        "separated_from_dispersion": true
+      },
+      "N=50,shift=3": {
+        "b_median_ms": 0.05559995770454407,
+        "c_median_ms": 0.09175017476081848,
+        "speedup_b_over_c_median": 0.6059929351577409,
+        "speedup_b_over_c_mean": 0.6113383901177091,
+        "separated_from_dispersion": true
+      },
+      "N=50,shift=12": {
+        "b_median_ms": 0.05539506673812866,
+        "c_median_ms": 0.08871778845787048,
+        "speedup_b_over_c_median": 0.6243963888305689,
+        "speedup_b_over_c_mean": 0.6263963135326815,
+        "separated_from_dispersion": true
+      },
+      "N=1000,shift=3": {
+        "b_median_ms": 0.0597536563873291,
+        "c_median_ms": 0.09069032967090607,
+        "speedup_b_over_c_median": 0.6588757214155148,
+        "speedup_b_over_c_mean": 0.6595202658379822,
+        "separated_from_dispersion": true
+      },
+      "N=1000,shift=12": {
+        "b_median_ms": 0.06091408431529999,
+        "c_median_ms": 0.08924119174480438,
+        "speedup_b_over_c_median": 0.6825781135856066,
+        "speedup_b_over_c_mean": 0.6785058127068553,
+        "separated_from_dispersion": true
+      },
+      "N=1000000,shift=3": {
+        "b_median_ms": 5.50537183880806,
+        "c_median_ms": 1.337684690952301,
+        "speedup_b_over_c_median": 4.11559755153419,
+        "speedup_b_over_c_mean": 4.176128125963738,
+        "separated_from_dispersion": true
+      },
+      "N=1000000,shift=12": {
+        "b_median_ms": 5.810923874378204,
+        "c_median_ms": 1.3374090194702148,
+        "speedup_b_over_c_median": 4.3449115340048134,
+        "speedup_b_over_c_mean": 4.425679426642436,
+        "separated_from_dispersion": true
+      }
+    }
+  }
+}
diff --git a/reports/experiments/h3-sigma-schedule/sm90-h800/env.txt b/reports/experiments/h3-sigma-schedule/sm90-h800/env.txt
new file mode 100644
index 000000000..ee5c97f32
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/sm90-h800/env.txt
@@ -0,0 +1,6 @@
+Sun Oct 25 17:32:03 UTC 2026
+NVIDIA H800 PCIe, 9.0, 580.82.07
+Python 3.12.3
+torch 2.5.1+cu124 cuda 12.4 triton 3.1.0 cc (9, 0) dev NVIDIA H800 PCIe
+pytest 9.1.1
+HEAD 40070d37495d193e2d8764837321d3a68dad9483
diff --git a/reports/experiments/h3-sigma-schedule/sm90-h800/pr566_sm90_evidence.md b/reports/experiments/h3-sigma-schedule/sm90-h800/pr566_sm90_evidence.md
new file mode 100644
index 000000000..e8e67b96e
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/sm90-h800/pr566_sm90_evidence.md
@@ -0,0 +1,455 @@
+# PR #566 `h3_sigma_schedule` — SM90 CUDA bitwise evidence (NVIDIA H800 PCIe)
+
+Collected 2026-10-26 01:27–01:34 CST (2026-10-25 17:27–17:34 UTC) on a rented
+AutoDL container (`CONTAINER-NAME-REDACTED`). Evidence-only run:
+no source, test or documentation file was modified; nothing was pushed or
+fetched from GitHub. The GPU name below is copied from `nvidia-smi` as printed.
+
+## Environment
+
+| Item | Value |
+| --- | --- |
+| GPU | `NVIDIA H800 PCIe` (nvidia-smi; 1 device, 81559 MiB; UUID GPU-UUID-REDACTED) |
+| Compute capability | `9.0` (`nvidia-smi --query-gpu=compute_cap`); `torch.cuda.get_device_capability()` = `(9, 0)` |
+| NVIDIA driver | `580.82.07` (nvidia-smi header reports driver-side CUDA Version 13.0) |
+| CUDA runtime seen by torch | `12.4` |
+| torch | `2.5.1+cu124` (pre-installed in the image; not touched) |
+| Triton | `3.1.0` (pre-installed; not touched; identical to the RTX 4090D run) |
+| Python | `3.12.3` CPython, `MINICONDA_PYTHON` |
+| pytest | `9.1.1` (the only package installed for this run) |
+| Host | x86_64, Linux 5.15.0-78-generic; 2× Intel Xeon Platinum 8458P (176 logical CPUs); ~1 TB RAM |
+| Repository HEAD | `40070d37495d193e2d8764837321d3a68dad9483` — "Merge remote-tracking branch 'fork/h3-sigma-schedule' into h3-sigma-schedule" |
+| Working tree | clean (`git status --short` printed nothing) |
+| Repo path on host | `REPO_ROOT` |
+
+## Code transfer and version gates (step 2)
+
+The code was transferred from the developer machine, not fetched from GitHub:
+a `git clone --branch h3-sigma-schedule --single-branch` of the local
+repository was tarred (`rlk-pr566-40070d3.tgz`, 66 MB, sha256
+`3fef727cb277d412a1d2f31fbf56708c423ca5b2c0c4b632de14bbd20b8fd4c0`), copied
+with scp, and the sha256 recomputed on the host matched. Extraction printed
+harmless `LIBARCHIVE.xattr.com.apple.provenance` header warnings (macOS tar).
+Because the tarball preserved the developer's uid, git refused with
+"detected dubious ownership"; `chown -R root:root` on the extracted tree
+cleared it (ownership only — no file content changed).
+
+```
+$ git log --oneline -8
+40070d3 Merge remote-tracking branch 'fork/h3-sigma-schedule' into h3-sigma-schedule
+eae0118 Merge branch 'test-h3' into h3-sigma-schedule
+a66c999 refactor(h3): default sigma_schedule_h3 to the PyTorch reference on CUDA
+d22d4b4 Merge pull request #576 from fusheng-ji/feat/h3-flash-attention-v1
+ae8dff6 Merge branch 'test-h3' into feat/h3-flash-attention-v1
+8542cf7 docs(h3): document the missing-Triton RuntimeError for h3-flash-attention-v1
+4c2348f fix(h3): address CodeRabbit review on h3-flash-attention-v1
+6f59021 Merge branch 'test-h3' into feat/h3-flash-attention-v1
+
+$ git status --short
+(empty)
+
+$ git rev-parse HEAD
+40070d37495d193e2d8764837321d3a68dad9483
+
+$ git log --oneline | grep -c 'refactor(h3): default sigma_schedule_h3 to the PyTorch reference on CUDA'
+1
+
+$ grep -n sigma_schedule_h3 -A2 rl_engine/runtime/registry.py
+431:            semantic_op="sigma_schedule_h3",           # semantic descriptor: reference
+451:            semantic_op="sigma_schedule_h3",           # semantic descriptor: triton
+739:                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],   # cuda
+763:                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],   # rocm
+807:                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],   # musa
+847:                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],   # cpu
+```
+
+All gates satisfied: HEAD is `40070d3…`, the default-backend commit `a66c999`
+is in the history, and every legacy platform list for `sigma_schedule_h3`
+contains only `PYTORCH_H3_SIGMA_SCHEDULE`.
+
+## Test files (step 3)
+
+`git diff --stat origin/test-h3...HEAD -- tests` fails on this copy
+(`fatal: bad revision` — the single-branch clone carries no `origin/test-h3`
+ref). Fallbacks used:
+
+```
+$ git diff --stat 97a7ab9 HEAD -- tests          # 97a7ab9 = PR base before the test-h3 merge
+ tests/backends/cuda/test_h3_flash_attention.py     | 129 +++++++   <- PR #576 via test-h3, NOT this PR
+ tests/backends/cuda/test_h3_sigma_schedule_cuda.py | 392 +++++++++++++++++++++
+ tests/reference/minimax_h3/__init__.py             |   2 +
+ .../h3_sigma_schedule_upstream_fixture.json        | 201 +++++++++++
+ .../reference/minimax_h3/make_upstream_fixture.py  | 154 ++++++++
+ .../reference/minimax_h3/test_h3_sigma_schedule.py | 185 ++++++++++
+ tests/runtime/test_h3_sigma_schedule_dispatch.py   | 190 ++++++++++
+
+$ git ls-files | grep -i h3_sigma
+benchmarks/models/benchmark_h3_sigma_schedule.py
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py
+tests/reference/minimax_h3/h3_sigma_schedule_upstream_fixture.json
+tests/reference/minimax_h3/test_h3_sigma_schedule.py
+tests/runtime/test_h3_sigma_schedule_dispatch.py
+```
+
+Sigma-schedule test files run: `tests/reference/minimax_h3/test_h3_sigma_schedule.py`,
+`tests/runtime/test_h3_sigma_schedule_dispatch.py`,
+`tests/backends/cuda/test_h3_sigma_schedule_cuda.py`.
+`test_h3_flash_attention.py` belongs to PR #576 and was not run.
+
+All runs: `python -m pytest … -v -rs` from the repository root, same
+interpreter, no `-x`. Logs and JUnit XML are in `EVIDENCE_DIR/`.
+
+## Results
+
+| Run | Command | Collected | Passed | Skipped | Failed | Errors | Wall |
+| --- | --- | ---: | ---: | ---: | ---: | ---: | ---: |
+| A — all H3 sigma tests | `python -m pytest tests/reference/minimax_h3 tests/runtime/test_h3_sigma_schedule_dispatch.py tests/backends/cuda/test_h3_sigma_schedule_cuda.py -v -rs` | 69 | **67** | 2 | **0** | 0 | 4.86 s |
+| B — CUDA/Triton/bitwise + dispatch subset | `python -m pytest tests/backends/cuda/test_h3_sigma_schedule_cuda.py tests/runtime/test_h3_sigma_schedule_dispatch.py -v -rs` | 48 | **47** | 1 | **0** | 0 | 2.89 s |
+| C — the two new/renamed registry tests | `python -m pytest "tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_defaults_to_reference_and_matches_triton_bits" "tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_opt_in_selects_triton_and_reports_provenance" -v -rs` | 2 | **2** | 0 | **0** | 0 | 2.51 s |
+
+Run A by file: `test_h3_sigma_schedule.py` 20 passed / 1 skipped;
+`test_h3_sigma_schedule_dispatch.py` 12 passed; `test_h3_sigma_schedule_cuda.py`
+35 passed / 1 skipped.
+
+### Skips (both runs, same two)
+
+| Test | Reason printed by `-rs` | Explanation |
+| --- | --- | --- |
+| `tests/reference/minimax_h3/test_h3_sigma_schedule.py:171` `test_matches_installed_diffusers_scheduler_when_available` | `could not import 'diffusers': No module named 'diffusers'` | Optional dependency not installed on this host (it was not installed to avoid touching the pinned torch). The pinned fixture test covers the upstream parity and passed. |
+| `tests/backends/cuda/test_h3_sigma_schedule_cuda.py:378` `test_target_device_guard_with_mismatched_current_device` | `multi-GPU device-guard test needs 2 devices` | This host has exactly one GPU (`nvidia-smi` lists GPU 0 only; `--query-gpu=count` = 1). This is the same test skipped for the same reason on the RTX 4090D host. |
+
+### Run C — singled out (first execution on any GPU)
+
+Both tests were introduced/renamed in `a66c999` after the RTX 4090D runs, so
+this is their first execution on hardware.
+
+- `test_public_entry_defaults_to_reference_and_matches_triton_bits` — **PASSED**.
+  `kernel_registry.get_op("sigma_schedule_h3", device="cuda")` returned
+  `NativeH3SigmaScheduleOp`; its outputs built on CUDA (`N=25, shift=12.0`)
+  compared bit-for-bit equal (`_int32_bits`) to `H3SigmaScheduleCudaOp()`'s
+  `sigmas` and `timesteps`, and `num_model_evals` matched.
+- `test_public_entry_opt_in_selects_triton_and_reports_provenance` — **PASSED**.
+  Semantic `requested_backend="rlkernel.h3_sigma_schedule.triton"`
+  instantiated `H3SigmaScheduleCudaOp` and provenance reported that backend.
+
+No bitwise test failed, so step 5 (mismatch forensics) was not triggered.
+
+## Benchmark (step 3d, optional)
+
+```
+python benchmarks/models/benchmark_h3_sigma_schedule.py --samples 100 --warmup 5 --json ~/pr566_evidence/benchmark-h800.json
+```
+
+Pre-timing correctness gate: path C (Triton, device build) bitwise equal to
+path A (CPU reference) for all 8 cases — **passed**; the gate's total wall
+time was 1143.6 ms (Triton kernel compilation included), reported once and
+excluded from timed samples. Raw JSON:
+`EVIDENCE_DIR/benchmark-h800.json` (52 KB, 100 samples per case and
+path after 5 warmups).
+
+| Workload | A median (ms) | B median (ms) | C median (ms) | B/C |
+| --- | ---: | ---: | ---: | ---: |
+| N=25, shift=3 | 0.0306 | 0.0551 | 0.0926 | 0.60x (separated) |
+| N=25, shift=12 | 0.0305 | 0.0554 | 0.0913 | 0.61x (separated) |
+| N=50, shift=3 | 0.0308 | 0.0556 | 0.0918 | 0.61x (separated) |
+| N=50, shift=12 | 0.0310 | 0.0554 | 0.0887 | 0.62x (separated) |
+| N=1000, shift=3 | 0.0347 | 0.0598 | 0.0907 | 0.66x (separated) |
+| N=1000, shift=12 | 0.0346 | 0.0609 | 0.0892 | 0.68x (separated) |
+| N=1000000, shift=3 | 5.4651 | 5.5054 | 1.3377 | 4.12x (separated) |
+| N=1000000, shift=12 | 5.5773 | 5.8109 | 1.3374 | 4.34x (separated) |
+
+A = reference, CPU build, CPU outputs; B = reference, CPU build, outputs
+copied to CUDA (the registry default path); C = Triton opt-in, device build.
+"separated" = the benchmark's own dispersion check passed.
+
+Caveats (why these numbers are supplementary only): the H800 PCIe has reduced
+FP64 throughput and the Triton kernel evaluates its intermediates in fp64;
+paths A/B run on this host's Xeon 8458P, which is a different CPU from the
+4090D host (at N=1e6 the CPU path here is ~5.5 ms versus ~48 ms there);
+single-operator microbenchmark, one card. On this host the device build is
+about 1.5–1.65x slower than CPU build plus copy at N=25/50/1000 and about
+4.1–4.3x faster at the N=1e6 dedup stress case. The reviewer's question is
+answered by the bitwise results above, not by this table.
+
+## Observations (not failures)
+
+- `WARNING … Core binary extension (_C) unavailable … Falling back to native code`
+  was printed once during the benchmark. The repository was not `pip install -e .`-built
+  (its declared `transformers==5.13.1`/`accelerate` dependencies were not installed to
+  keep torch untouched); `h3_sigma_schedule` does not use `_C`. No test printed this
+  warning.
+- Only `pytest` was installed; torch 2.5.1+cu124 and Triton 3.1.0 are the image's.
+- `git diff --stat origin/test-h3...HEAD` is unavailable on this copy (no such ref);
+  `97a7ab9` and `git ls-files` fallbacks were used as instructed.
+
+## Factual conclusion
+
+On NVIDIA H800 PCIe (SM90, compute capability 9.0, driver 580.82.07, torch
+2.5.1+cu124, CUDA 12.4, Triton 3.1.0) at HEAD `40070d37495d193e2d8764837321d3a68dad9483`:
+
+- All 35 runnable tests in `tests/backends/cuda/test_h3_sigma_schedule_cuda.py`
+  passed — pinned-fixture bitwise match, live-CPU-reference bitwise match on
+  the three combos that test parametrizes (N=50/shift=3, N=50/shift=12 and
+  N=1000/shift=12; its parametrization has no N=1000/shift=3 case),
+  dense-grid dedup, grid invariants, subnormal
+  (1e-45) / underflow (1e-46) / ±NaN / inf / 1e39 / 3.5e38 / 1e30 / 1e-10
+  edge parity, float-N truncation, input rejections, repeated/interleaved
+  stability, backend identity, default-reference-vs-Triton bit equality, and
+  semantic Triton opt-in. 1 test skipped (needs 2 GPUs; host has 1). The
+  three-combo list is that test's full parametrization — all-8-case coverage
+  (N=25/50/1000/1e6 × shift 3/12) is provided separately by the benchmark's
+  pre-timing correctness gate, not by this suite.
+- All 12 dispatch tests passed. 20 reference tests passed, 1 skipped
+  (`diffusers` not installed).
+- 0 failures and 0 errors across runs A, B and C.
+- Compared with the historical RTX 4090D CUDA run (34 passed / 1 skipped,
+  torch 2.5.1+cu121, Triton 3.1.0, driver 580.76.05): one more test passed
+  here because `a66c999` split the registry-identity test into two; the one
+  skip is the same test for the same reason; no test that passed on the
+  4090D failed here. Triton version is identical; torch differs only in the
+  CUDA build (cu124 vs cu121); driver 580.82.07 vs 580.76.05.
+- Benchmark correctness gate passed on all 8 cases; latency ratios differ
+  from the 4090D (see caveats) and are reported as supplementary data only.
+
+Evidence files: `EVIDENCE_DIR/{env.txt, run_a.log, run_a.xml, run_b.log,
+run_b.xml, run_c.log, run_c.xml, bench.log, benchmark-h800.json}` on the host;
+a copy was pulled to the developer machine.
+
+## Raw outputs
+
+<details><summary><code>env.txt</code></summary>
+
+```text
+Sun Oct 25 17:32:03 UTC 2026
+NVIDIA H800 PCIe, 9.0, 580.82.07
+Python 3.12.3
+torch 2.5.1+cu124 cuda 12.4 triton 3.1.0 cc (9, 0) dev NVIDIA H800 PCIe
+pytest 9.1.1
+HEAD 40070d37495d193e2d8764837321d3a68dad9483
+```
+
+</details>
+
+<details><summary><code>run_a.log</code></summary>
+
+```text
+============================= test session starts ==============================
+platform linux -- Python 3.12.3, pytest-9.1.1, pluggy-1.7.0 -- MINICONDA_PYTHON
+cachedir: .pytest_cache
+rootdir: REPO_ROOT
+configfile: pyproject.toml
+plugins: anyio-4.6.2.post1
+collecting ... collected 69 items
+
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_matches_pinned_upstream_set_timesteps_bitwise PASSED [  1%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[2-12.0] PASSED [  2%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[2-3.0] PASSED [  4%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[8-12.0] PASSED [  5%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[8-3.0] PASSED [  7%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[25-12.0] PASSED [  8%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[25-3.0] PASSED [ 10%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[50-12.0] PASSED [ 11%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[50-3.0] PASSED [ 13%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[1000-12.0] PASSED [ 14%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_grid_invariants[1000-3.0] PASSED [ 15%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_unique_consecutive_collapses_shift_created_collisions PASSED [ 17%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_video_and_audio_shifts_give_distinct_grids PASSED [ 18%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_rejects_num_inference_steps_below_two[1] PASSED [ 20%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_rejects_num_inference_steps_below_two[0] PASSED [ 21%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_rejects_num_inference_steps_below_two[-4] PASSED [ 23%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_rejects_non_positive_shift[0.0] PASSED [ 24%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_rejects_non_positive_shift[-1.5] PASSED [ 26%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_device_argument_preserves_bytes_and_dtype PASSED [ 27%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_builds_on_cpu_under_non_cpu_default_device PASSED [ 28%]
+tests/reference/minimax_h3/test_h3_sigma_schedule.py::test_matches_installed_diffusers_scheduler_when_available SKIPPED [ 30%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_get_op_cpu_selects_reference_and_builds_pinned_grid PASSED [ 31%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_get_op_cuda_defaults_to_reference_regardless_of_triton PASSED [ 33%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_cuda_backend_construction_fails_loudly_without_triton PASSED [ 34%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_shift_scalars_pinned_to_cpu_under_meta_default PASSED [ 36%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_shift_scalars_keep_fp64_subtract_then_round_semantics PASSED [ 37%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_cuda_backend_construction_rejected_on_hip_build PASSED [ 39%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_get_op_on_hip_build_serves_reference PASSED [ 40%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_triton_backend_is_not_a_legacy_candidate_on_any_platform PASSED [ 42%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_descriptors_declared_truthfully PASSED [ 43%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_reference_path_resolves_instantiates_and_reports_provenance PASSED [ 44%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_triton_backend_fails_explicitly_when_unavailable PASSED [ 46%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_unknown_backend_is_rejected PASSED [ 47%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_pinned_cpu_fixture_bitwise PASSED [ 49%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_live_cpu_reference_bitwise[50-12.0] PASSED [ 50%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_live_cpu_reference_bitwise[50-3.0] PASSED [ 52%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_live_cpu_reference_bitwise[1000-12.0] PASSED [ 53%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_dense_grid_dedup_matches_cpu_reference PASSED [ 55%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_reference_with_cuda_device_preserves_fixture_bytes PASSED [ 56%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[2-3.0] PASSED [ 57%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[2-12.0] PASSED [ 59%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[4-3.0] PASSED [ 60%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[4-12.0] PASSED [ 62%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[25-3.0] PASSED [ 63%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[25-12.0] PASSED [ 65%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_num_inference_steps_below_two[1] PASSED [ 66%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_num_inference_steps_below_two[0] PASSED [ 68%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_num_inference_steps_below_two[-4] PASSED [ 69%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_subnormal_shift_1e_45_matches_reference_upstream_parity PASSED [ 71%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_underflow_shift_1e_46_matches_reference_upstream_parity PASSED [ 72%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_positive_nan_shift_propagates_positive_quiet_nan PASSED [ 73%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_negative_nan_shift_propagates_negative_quiet_nan PASSED [ 75%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[nan] PASSED [ 76%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[inf] PASSED [ 78%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[1e-10] PASSED [ 79%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[1e+39] PASSED [ 81%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[3.5e+38] PASSED [ 82%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[1e+30] PASSED [ 84%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_float_num_steps_truncate_like_reference[2.9-2] PASSED [ 85%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_float_num_steps_truncate_like_reference[3.1-3] PASSED [ 86%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_non_positive_shift[0.0] PASSED [ 88%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_non_positive_shift[-1.5] PASSED [ 89%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_non_positive_shift[-inf] PASSED [ 91%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_cpu_device_instead_of_silent_fallback PASSED [ 92%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_repeated_and_interleaved_calls_are_stable PASSED [ 94%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_backend_identity_is_device_path_not_cpu_fallback PASSED [ 95%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_defaults_to_reference_and_matches_triton_bits PASSED [ 97%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_opt_in_selects_triton_and_reports_provenance PASSED [ 98%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_target_device_guard_with_mismatched_current_device SKIPPED [100%]
+
+-------------- generated xml file: EVIDENCE_DIR/run_a.xml --------------
+=========================== short test summary info ============================
+SKIPPED [1] tests/reference/minimax_h3/test_h3_sigma_schedule.py:171: could not import 'diffusers': No module named 'diffusers'
+SKIPPED [1] tests/backends/cuda/test_h3_sigma_schedule_cuda.py:378: multi-GPU device-guard test needs 2 devices
+======================== 67 passed, 2 skipped in 4.86s =========================
+```
+
+</details>
+
+<details><summary><code>run_b.log</code></summary>
+
+```text
+============================= test session starts ==============================
+platform linux -- Python 3.12.3, pytest-9.1.1, pluggy-1.7.0 -- MINICONDA_PYTHON
+cachedir: .pytest_cache
+rootdir: REPO_ROOT
+configfile: pyproject.toml
+plugins: anyio-4.6.2.post1
+collecting ... collected 48 items
+
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_pinned_cpu_fixture_bitwise PASSED [  2%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_live_cpu_reference_bitwise[50-12.0] PASSED [  4%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_live_cpu_reference_bitwise[50-3.0] PASSED [  6%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_matches_live_cpu_reference_bitwise[1000-12.0] PASSED [  8%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_dense_grid_dedup_matches_cpu_reference PASSED [ 10%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_reference_with_cuda_device_preserves_fixture_bytes PASSED [ 12%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[2-3.0] PASSED [ 14%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[2-12.0] PASSED [ 16%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[4-3.0] PASSED [ 18%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[4-12.0] PASSED [ 20%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[25-3.0] PASSED [ 22%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_grid_invariants_on_device[25-12.0] PASSED [ 25%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_num_inference_steps_below_two[1] PASSED [ 27%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_num_inference_steps_below_two[0] PASSED [ 29%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_num_inference_steps_below_two[-4] PASSED [ 31%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_subnormal_shift_1e_45_matches_reference_upstream_parity PASSED [ 33%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_underflow_shift_1e_46_matches_reference_upstream_parity PASSED [ 35%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_positive_nan_shift_propagates_positive_quiet_nan PASSED [ 37%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_negative_nan_shift_propagates_negative_quiet_nan PASSED [ 39%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[nan] PASSED [ 41%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[inf] PASSED [ 43%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[1e-10] PASSED [ 45%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[1e+39] PASSED [ 47%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[3.5e+38] PASSED [ 50%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_edge_shifts_match_reference_upstream_parity[1e+30] PASSED [ 52%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_float_num_steps_truncate_like_reference[2.9-2] PASSED [ 54%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_float_num_steps_truncate_like_reference[3.1-3] PASSED [ 56%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_non_positive_shift[0.0] PASSED [ 58%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_non_positive_shift[-1.5] PASSED [ 60%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_non_positive_shift[-inf] PASSED [ 62%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_rejects_cpu_device_instead_of_silent_fallback PASSED [ 64%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_repeated_and_interleaved_calls_are_stable PASSED [ 66%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_backend_identity_is_device_path_not_cpu_fallback PASSED [ 68%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_defaults_to_reference_and_matches_triton_bits PASSED [ 70%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_opt_in_selects_triton_and_reports_provenance PASSED [ 72%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_target_device_guard_with_mismatched_current_device SKIPPED [ 75%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_get_op_cpu_selects_reference_and_builds_pinned_grid PASSED [ 77%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_get_op_cuda_defaults_to_reference_regardless_of_triton PASSED [ 79%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_cuda_backend_construction_fails_loudly_without_triton PASSED [ 81%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_shift_scalars_pinned_to_cpu_under_meta_default PASSED [ 83%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_shift_scalars_keep_fp64_subtract_then_round_semantics PASSED [ 85%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_cuda_backend_construction_rejected_on_hip_build PASSED [ 87%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_get_op_on_hip_build_serves_reference PASSED [ 89%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_triton_backend_is_not_a_legacy_candidate_on_any_platform PASSED [ 91%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_descriptors_declared_truthfully PASSED [ 93%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_reference_path_resolves_instantiates_and_reports_provenance PASSED [ 95%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_triton_backend_fails_explicitly_when_unavailable PASSED [ 97%]
+tests/runtime/test_h3_sigma_schedule_dispatch.py::test_semantic_unknown_backend_is_rejected PASSED [100%]
+
+-------------- generated xml file: EVIDENCE_DIR/run_b.xml --------------
+=========================== short test summary info ============================
+SKIPPED [1] tests/backends/cuda/test_h3_sigma_schedule_cuda.py:378: multi-GPU device-guard test needs 2 devices
+======================== 47 passed, 1 skipped in 2.89s =========================
+```
+
+</details>
+
+<details><summary><code>run_c.log</code></summary>
+
+```text
+============================= test session starts ==============================
+platform linux -- Python 3.12.3, pytest-9.1.1, pluggy-1.7.0 -- MINICONDA_PYTHON
+cachedir: .pytest_cache
+rootdir: REPO_ROOT
+configfile: pyproject.toml
+plugins: anyio-4.6.2.post1
+collecting ... collected 2 items
+
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_defaults_to_reference_and_matches_triton_bits PASSED [ 50%]
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py::test_public_entry_opt_in_selects_triton_and_reports_provenance PASSED [100%]
+
+-------------- generated xml file: EVIDENCE_DIR/run_c.xml --------------
+============================== 2 passed in 2.51s ===============================
+```
+
+</details>
+
+<details><summary><code>bench.log</code></summary>
+
+```text
+path A (reference, cpu build, cpu outputs): 100 calls x [25, 50, 1000, 1000000] x [3.0, 12.0]
+verifying path C against path A bitwise before timing...
+WARNING 10-26 01:33:03 [RL-Kernel]: Core binary extension (_C) unavailable: cannot import name '_C' from 'rl_engine' (REPO_ROOT/rl_engine/__init__.py). Falling back to native code.
+correctness gate passed (includes Triton kernel compilation: 1143.6 ms wall, reported once, excluded from all timed samples)
+path B (reference, cpu build, outputs moved to gpu): 100 calls
+path C (triton, device build): 100 calls
+                        path_a_reference_cpu         N=25,shift=3: 0.0306 ms/call (median)
+                        path_a_reference_cpu        N=25,shift=12: 0.0305 ms/call (median)
+                        path_a_reference_cpu         N=50,shift=3: 0.0308 ms/call (median)
+                        path_a_reference_cpu        N=50,shift=12: 0.0310 ms/call (median)
+                        path_a_reference_cpu       N=1000,shift=3: 0.0347 ms/call (median)
+                        path_a_reference_cpu      N=1000,shift=12: 0.0346 ms/call (median)
+                        path_a_reference_cpu    N=1000000,shift=3: 5.4651 ms/call (median)
+                        path_a_reference_cpu   N=1000000,shift=12: 5.5773 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu         N=25,shift=3: 0.0551 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu        N=25,shift=12: 0.0554 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu         N=50,shift=3: 0.0556 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu        N=50,shift=12: 0.0554 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu       N=1000,shift=3: 0.0598 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu      N=1000,shift=12: 0.0609 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu    N=1000000,shift=3: 5.5054 ms/call (median)
+ path_b_reference_cpu_build_then_copy_to_gpu   N=1000000,shift=12: 5.8109 ms/call (median)
+                  path_c_triton_device_build         N=25,shift=3: 0.0926 ms/call (median)
+                  path_c_triton_device_build        N=25,shift=12: 0.0913 ms/call (median)
+                  path_c_triton_device_build         N=50,shift=3: 0.0918 ms/call (median)
+                  path_c_triton_device_build        N=50,shift=12: 0.0887 ms/call (median)
+                  path_c_triton_device_build       N=1000,shift=3: 0.0907 ms/call (median)
+                  path_c_triton_device_build      N=1000,shift=12: 0.0892 ms/call (median)
+                  path_c_triton_device_build    N=1000000,shift=3: 1.3377 ms/call (median)
+                  path_c_triton_device_build   N=1000000,shift=12: 1.3374 ms/call (median)
+speedup B/C         N=25,shift=3: 0.60x (separated from dispersion)
+speedup B/C        N=25,shift=12: 0.61x (separated from dispersion)
+speedup B/C         N=50,shift=3: 0.61x (separated from dispersion)
+speedup B/C        N=50,shift=12: 0.62x (separated from dispersion)
+speedup B/C       N=1000,shift=3: 0.66x (separated from dispersion)
+speedup B/C      N=1000,shift=12: 0.68x (separated from dispersion)
+speedup B/C    N=1000000,shift=3: 4.12x (separated from dispersion)
+speedup B/C   N=1000000,shift=12: 4.34x (separated from dispersion)
+wrote EVIDENCE_DIR/benchmark-h800.json
+```
+
+</details>
diff --git a/reports/experiments/h3-sigma-schedule/sm90-h800/run_a.xml b/reports/experiments/h3-sigma-schedule/sm90-h800/run_a.xml
new file mode 100644
index 000000000..45e368791
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/sm90-h800/run_a.xml
@@ -0,0 +1 @@
+<?xml version="1.0" encoding="utf-8"?><testsuites name="pytest tests"><testsuite name="pytest" errors="0" failures="0" skipped="2" tests="69" time="4.859" timestamp="2026-10-26T01:32:06.595596+08:00"><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_matches_pinned_upstream_set_timesteps_bitwise" time="0.032" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[2-12.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[2-3.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[8-12.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[8-3.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[25-12.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[25-3.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[50-12.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[50-3.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[1000-12.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_grid_invariants[1000-3.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_unique_consecutive_collapses_shift_created_collisions" time="0.011" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_video_and_audio_shifts_give_distinct_grids" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_rejects_num_inference_steps_below_two[1]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_rejects_num_inference_steps_below_two[0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_rejects_num_inference_steps_below_two[-4]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_rejects_non_positive_shift[0.0]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_rejects_non_positive_shift[-1.5]" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_device_argument_preserves_bytes_and_dtype" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_builds_on_cpu_under_non_cpu_default_device" time="0.001" /><testcase classname="tests.reference.minimax_h3.test_h3_sigma_schedule" name="test_matches_installed_diffusers_scheduler_when_available" time="0.001"><skipped type="pytest.skip" message="could not import 'diffusers': No module named 'diffusers'">REPO_ROOT/tests/reference/minimax_h3/test_h3_sigma_schedule.py:171: could not import 'diffusers': No module named 'diffusers'</skipped></testcase><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_get_op_cpu_selects_reference_and_builds_pinned_grid" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_get_op_cuda_defaults_to_reference_regardless_of_triton" time="0.002" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_cuda_backend_construction_fails_loudly_without_triton" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_shift_scalars_pinned_to_cpu_under_meta_default" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_shift_scalars_keep_fp64_subtract_then_round_semantics" time="0.000" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_cuda_backend_construction_rejected_on_hip_build" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_get_op_on_hip_build_serves_reference" time="0.026" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_triton_backend_is_not_a_legacy_candidate_on_any_platform" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_descriptors_declared_truthfully" time="0.000" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_reference_path_resolves_instantiates_and_reports_provenance" time="0.005" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_triton_backend_fails_explicitly_when_unavailable" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_unknown_backend_is_rejected" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_pinned_cpu_fixture_bitwise" time="1.906" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_live_cpu_reference_bitwise[50-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_live_cpu_reference_bitwise[50-3.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_live_cpu_reference_bitwise[1000-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_dense_grid_dedup_matches_cpu_reference" time="0.637" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_reference_with_cuda_device_preserves_fixture_bytes" time="0.002" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[2-3.0]" time="0.017" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[2-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[4-3.0]" time="0.024" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[4-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[25-3.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[25-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_num_inference_steps_below_two[1]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_num_inference_steps_below_two[0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_num_inference_steps_below_two[-4]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_subnormal_shift_1e_45_matches_reference_upstream_parity" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_underflow_shift_1e_46_matches_reference_upstream_parity" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_positive_nan_shift_propagates_positive_quiet_nan" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_negative_nan_shift_propagates_negative_quiet_nan" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[nan]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[inf]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[1e-10]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[1e+39]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[3.5e+38]" time="0.003" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[1e+30]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_float_num_steps_truncate_like_reference[2.9-2]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_float_num_steps_truncate_like_reference[3.1-3]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_non_positive_shift[0.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_non_positive_shift[-1.5]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_non_positive_shift[-inf]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_cpu_device_instead_of_silent_fallback" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_repeated_and_interleaved_calls_are_stable" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_backend_identity_is_device_path_not_cpu_fallback" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_public_entry_defaults_to_reference_and_matches_triton_bits" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_public_entry_opt_in_selects_triton_and_reports_provenance" time="0.012" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_target_device_guard_with_mismatched_current_device" time="0.000"><skipped type="pytest.skip" message="multi-GPU device-guard test needs 2 devices">REPO_ROOT/tests/backends/cuda/test_h3_sigma_schedule_cuda.py:378: multi-GPU device-guard test needs 2 devices</skipped></testcase></testsuite></testsuites>
diff --git a/reports/experiments/h3-sigma-schedule/sm90-h800/run_b.xml b/reports/experiments/h3-sigma-schedule/sm90-h800/run_b.xml
new file mode 100644
index 000000000..2d76b25c0
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/sm90-h800/run_b.xml
@@ -0,0 +1 @@
+<?xml version="1.0" encoding="utf-8"?><testsuites name="pytest tests"><testsuite name="pytest" errors="0" failures="0" skipped="1" tests="48" time="2.893" timestamp="2026-10-26T01:32:12.307161+08:00"><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_pinned_cpu_fixture_bitwise" time="0.735" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_live_cpu_reference_bitwise[50-12.0]" time="0.028" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_live_cpu_reference_bitwise[50-3.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_matches_live_cpu_reference_bitwise[1000-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_dense_grid_dedup_matches_cpu_reference" time="0.258" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_reference_with_cuda_device_preserves_fixture_bytes" time="0.002" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[2-3.0]" time="0.023" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[2-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[4-3.0]" time="0.024" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[4-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[25-3.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_grid_invariants_on_device[25-12.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_num_inference_steps_below_two[1]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_num_inference_steps_below_two[0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_num_inference_steps_below_two[-4]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_subnormal_shift_1e_45_matches_reference_upstream_parity" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_underflow_shift_1e_46_matches_reference_upstream_parity" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_positive_nan_shift_propagates_positive_quiet_nan" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_negative_nan_shift_propagates_negative_quiet_nan" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[nan]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[inf]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[1e-10]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[1e+39]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[3.5e+38]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_edge_shifts_match_reference_upstream_parity[1e+30]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_float_num_steps_truncate_like_reference[2.9-2]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_float_num_steps_truncate_like_reference[3.1-3]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_non_positive_shift[0.0]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_non_positive_shift[-1.5]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_non_positive_shift[-inf]" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_rejects_cpu_device_instead_of_silent_fallback" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_repeated_and_interleaved_calls_are_stable" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_backend_identity_is_device_path_not_cpu_fallback" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_public_entry_defaults_to_reference_and_matches_triton_bits" time="0.001" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_public_entry_opt_in_selects_triton_and_reports_provenance" time="0.013" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_target_device_guard_with_mismatched_current_device" time="0.000"><skipped type="pytest.skip" message="multi-GPU device-guard test needs 2 devices">REPO_ROOT/tests/backends/cuda/test_h3_sigma_schedule_cuda.py:378: multi-GPU device-guard test needs 2 devices</skipped></testcase><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_get_op_cpu_selects_reference_and_builds_pinned_grid" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_get_op_cuda_defaults_to_reference_regardless_of_triton" time="0.003" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_cuda_backend_construction_fails_loudly_without_triton" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_shift_scalars_pinned_to_cpu_under_meta_default" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_shift_scalars_keep_fp64_subtract_then_round_semantics" time="0.000" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_cuda_backend_construction_rejected_on_hip_build" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_get_op_on_hip_build_serves_reference" time="0.009" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_triton_backend_is_not_a_legacy_candidate_on_any_platform" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_descriptors_declared_truthfully" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_reference_path_resolves_instantiates_and_reports_provenance" time="0.010" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_triton_backend_fails_explicitly_when_unavailable" time="0.001" /><testcase classname="tests.runtime.test_h3_sigma_schedule_dispatch" name="test_semantic_unknown_backend_is_rejected" time="0.001" /></testsuite></testsuites>
diff --git a/reports/experiments/h3-sigma-schedule/sm90-h800/run_c.xml b/reports/experiments/h3-sigma-schedule/sm90-h800/run_c.xml
new file mode 100644
index 000000000..069554b98
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/sm90-h800/run_c.xml
@@ -0,0 +1 @@
+<?xml version="1.0" encoding="utf-8"?><testsuites name="pytest tests"><testsuite name="pytest" errors="0" failures="0" skipped="0" tests="2" time="2.510" timestamp="2026-10-26T01:32:15.996191+08:00"><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_public_entry_defaults_to_reference_and_matches_triton_bits" time="0.881" /><testcase classname="tests.backends.cuda.test_h3_sigma_schedule_cuda" name="test_public_entry_opt_in_selects_triton_and_reports_provenance" time="0.013" /></testsuite></testsuites>
diff --git a/reports/experiments/h3-sigma-schedule/source-provenance.json b/reports/experiments/h3-sigma-schedule/source-provenance.json
new file mode 100644
index 000000000..31dc8b905
--- /dev/null
+++ b/reports/experiments/h3-sigma-schedule/source-provenance.json
@@ -0,0 +1,133 @@
+{
+  "evidence_kind": "Historical 4090D operator results (source binding rechecked 2026-10-21) plus an SM90 (H800) hardware run on 2026-10-26.",
+  "candidate_commit": "374488bb3abc856b356b79fbfbcc0e15bbb968c4",
+  "historical_snapshot_base_commit": "0e8a18aff441895082aee603959cd25cb66d7e4b",
+  "environment": {
+    "python": "3.12.3",
+    "python_impl": "CPython",
+    "platform": "Linux-5.15.0-94-generic-x86_64-with-glibc2.35",
+    "torch": "2.5.1+cu121",
+    "torch_cuda_runtime": "12.1",
+    "torch_hip": null,
+    "cuda_available": true,
+    "cuda_device_count": 1,
+    "triton": "3.1.0",
+    "cuda_device_name": "NVIDIA GeForce RTX 4090 D",
+    "cuda_capability": "8.9"
+  },
+  "nvidia_driver": "580.76.05",
+  "cuda_validation": {
+    "run": "run-20261017-002253-9749",
+    "passed": 34,
+    "skipped": 1,
+    "failures": 0,
+    "errors": 0,
+    "skip_reason": "multi-GPU device guard requires two GPUs; host had one",
+    "snapshot_sha256": "5d7ef73a86d8b1ab2086c6b09e45ce0799484fcac6a0d5964ed6372b02592fe5",
+    "source_files_sha256": {
+      "rl_engine/reference/minimax_h3/sigma_schedule.py": "18b36cdbac9e95d4b52782aa17a7228fdf35bc7e3397508a651c1fb07cb36509",
+      "rl_engine/backends/cuda/model_specific/minimax_h3/sigma_schedule.py": "784fb85f2e3dbce450fd5564c99584eb75a83c8b01374d938f036c7036494262",
+      "tests/reference/minimax_h3/test_h3_sigma_schedule.py": "1304b4738196250bd09c5532f39dd15b14e1ff46910ef4a807067c5a8b1faeee",
+      "tests/reference/minimax_h3/h3_sigma_schedule_upstream_fixture.json": "97a929a39eb781ce00bd351d8c30c85d9bfd054e7ca5405dc3a3b8ed794956c1",
+      "tests/runtime/test_h3_sigma_schedule_dispatch.py": "1750573eb6f609490e637d4088ca7f7ab6dfe01c6077d68cf1428b2a239c8e0e",
+      "tests/backends/cuda/test_h3_sigma_schedule_cuda.py": "c9ce44388a4fb31e0415026836c74c2818514ec995229d94315462c2894ae72a",
+      "benchmarks/models/benchmark_h3_sigma_schedule.py": "04975954e863050d602479d737b5218b88e03f4cc87aca7ca90cb47ebf0f3486"
+    },
+    "junit_original_sha256": "9e2d476cdaf24043e66f239e9f5d5acbb58a2949bb474b4662ca09b8a96e7240",
+    "junit_redaction": "Removed testsuite hostname attribute; XML reserialized. All test outcomes preserved."
+  },
+  "benchmark": {
+    "run": "run-20261016-235221-8055",
+    "snapshot_sha256": "0b7c25c6a9bf4e109fe0e053a90fed1a977831d859f2bf99575cfcfe08da9b34",
+    "binding": "Benchmark and reference byte-identical. CUDA kernels and scalar helper ASTs identical. Forward AST identical after normalizing only the non-CUDA device error text; final constructor adds HIP rejection. Post-run note (2026-10-26): the benchmark file later changed twice — the docstring / path-B wording (a66c999) and the GPU-without-Triton + HIP/ROCm branch fix (ace9c20). Both 4090D measurements above ran on the pre-change file; the NVIDIA + Triton execution path is unchanged by both commits.",
+    "cuda_function_asts_identical": [
+      "_shift_scalars",
+      "_shifted_grid_kernel",
+      "_unique_consecutive_kernel",
+      "_timesteps_kernel",
+      "__call__"
+    ],
+    "forward_ast_equal_after_normalizing_non_cuda_error": true
+  },
+  "included_files_sha256": {
+    "benchmark-4090d.json": "84ba715d03e6ada96c122f7cff3992d81e569acb4c56b810bb191fc84f64e6e9",
+    "cuda-4090d.xml": "c5377af475a7020c02f0c1784bd87df6412ca4f8cfc42f4687dd8f8fac1900e2"
+  },
+  "limits": [
+    "One x86_64 NVIDIA RTX 4090D (October 2026) and one x86_64 NVIDIA H800 PCIe SM90 host (2026-10-26); no ROCm device backend.",
+    "No multi-GPU test or full-model run on either host.",
+    "The benchmark's GPU-without-Triton and HIP/ROCm branches (ace9c20) have not run on GPU or HIP hardware; the H800 latency table is supplementary (reduced FP64 throughput, different host CPU) and not comparable with the 4090D numbers.",
+    "Historical broad dispatch suite had two attention failures also present in the recorded baseline A/B comparison; not an all-green pipeline claim."
+  ],
+  "sm90_validation": {
+    "run_date": "2026-10-26",
+    "tested_commit": "40070d37495d193e2d8764837321d3a68dad9483",
+    "environment": {
+      "gpu": "NVIDIA H800 PCIe",
+      "compute_capability": "9.0",
+      "driver": "580.82.07",
+      "platform": "x86_64 Linux 5.15.0-78-generic; 2x Intel Xeon Platinum 8458P",
+      "python": "3.12.3",
+      "torch": "2.5.1+cu124",
+      "torch_cuda_runtime": "12.4",
+      "torch_hip": null,
+      "triton": "3.1.0",
+      "pytest": "9.1.1 (the only package installed on the host)"
+    },
+    "run_a": {
+      "collected": 69,
+      "passed": 67,
+      "skipped": 2,
+      "failures": 0,
+      "errors": 0,
+      "skip_reasons": [
+        "could not import 'diffusers' (optional parity test; fixture test passed)",
+        "multi-GPU device-guard test needs 2 devices; host had 1"
+      ]
+    },
+    "run_b": {
+      "collected": 48,
+      "passed": 47,
+      "skipped": 1,
+      "failures": 0,
+      "errors": 0
+    },
+    "run_c": {
+      "collected": 2,
+      "passed": 2,
+      "note": "first hardware execution of the two registry tests introduced by a66c999; the default reference path and the Triton backend produced identical bits"
+    },
+    "source_files_sha256_at_tested_commit": {
+      "rl_engine/reference/minimax_h3/sigma_schedule.py": "18b36cdbac9e95d4b52782aa17a7228fdf35bc7e3397508a651c1fb07cb36509",
+      "rl_engine/backends/cuda/model_specific/minimax_h3/sigma_schedule.py": "784fb85f2e3dbce450fd5564c99584eb75a83c8b01374d938f036c7036494262",
+      "tests/reference/minimax_h3/test_h3_sigma_schedule.py": "1304b4738196250bd09c5532f39dd15b14e1ff46910ef4a807067c5a8b1faeee",
+      "tests/reference/minimax_h3/h3_sigma_schedule_upstream_fixture.json": "97a929a39eb781ce00bd351d8c30c85d9bfd054e7ca5405dc3a3b8ed794956c1",
+      "tests/runtime/test_h3_sigma_schedule_dispatch.py": "c14a503dcdc82ccfc2c3c3a8da695038bfdaaa65db1d5f4ae87fbd4bb19e686f",
+      "tests/backends/cuda/test_h3_sigma_schedule_cuda.py": "82a584cadadebdf139ed9871ba2165d492c94727d024cffbf48bc079013c176b",
+      "benchmarks/models/benchmark_h3_sigma_schedule.py": "5c1b135c5b723cfcdfc6a9dc9c542601bbc3067a62f28ae75bd8fa2772059ec2"
+    },
+    "included_files_sha256": {
+      "sm90-h800/env.txt": "13d42ff62485307c55d4af5efe7fb6e7633a8f37a869d975d70249b1acaaaebf",
+      "sm90-h800/run_a.xml": "4797238671384fbeb1ad9ddd54fa18ba48d760d18d69207f354ca291c3882604",
+      "sm90-h800/run_b.xml": "86cfec27c58060990317720777ce63b51dc208d09962445f1bca3a8121e5a658",
+      "sm90-h800/run_c.xml": "e2ea3433d80e7634976819856123659d6dafa8b3c747b964afc192e90ca802d2",
+      "sm90-h800/benchmark-h800.json": "769b89b16679bdc5db365a2cc10f1dc7cc1966d72fbcf5ce0aae5a9d61b73d4c",
+      "sm90-h800/pr566_sm90_evidence.md": "5ecf4b0672fd41bf74f9ce9f0484ed07fce252e3c6aadc490a5dd8b1080a9e81"
+    },
+    "original_server_sha256": {
+      "sm90-h800/env.txt": "13d42ff62485307c55d4af5efe7fb6e7633a8f37a869d975d70249b1acaaaebf",
+      "sm90-h800/run_a.log": "565ae81515f8d1111f7043b1e195c7ad8196cd031a90d38bb73c407e21be2240",
+      "sm90-h800/run_a.xml": "66889f04f9f162c2c36d8e21b148c5d9d33596550cd71c13ed91b5d339ceb9d0",
+      "sm90-h800/run_b.log": "ad200760d36aad6802506b43b5ec7bc043eb55ef25907bd285c50962a25fee2a",
+      "sm90-h800/run_b.xml": "1d5767d44b77c4bb489eb7a3c602791bc824c97082f9ac363bc2482f0211807e",
+      "sm90-h800/run_c.log": "6f3a91c8d97cf81e8e00a38b559fe0f3dc52bb1aa8313a1723de754a993ea7e1",
+      "sm90-h800/run_c.xml": "bda3e575dc09ec32463dfbc8fb2cdc9a6259f68ae14cdc53a529cdc5be2d73c6",
+      "sm90-h800/bench.log": "da43426479f55f16cb4d1202691b1234a91434265f18d9419af91aa26ecae845",
+      "sm90-h800/benchmark-h800.json": "50868bae541aee093465fb8e5998af0d6d80f967538763fca6b1ce8a491b97b4",
+      "sm90-h800/pr566_sm90_evidence.md": "f4edb693161ce5a212c4da47f9e2737f3b35ec1f78ddd2908700f0e76e81e0c6"
+    },
+    "benchmark_gate": "path C (Triton) bitwise equal to path A (CPU reference) for all 8 cases; gate wall incl. Triton compilation 1143.6 ms, excluded from timed samples; benchmark-h800.json is byte-identical to the server original except an appended final newline",
+    "redaction": "GPU UUID, container hostname and /root/... paths removed from the committed logs, JUnit XML and report (JUnit hostname attribute dropped, as for the 4090D XML; host paths additionally replaced by REPO_ROOT / EVIDENCE_DIR / MINICONDA_PYTHON tokens, one step beyond the 4090D precedent). A final newline was appended to the three XMLs and to benchmark-h800.json for the end-of-file-fixer hook; env.txt needed no change. The four standalone console logs (run_a/b/c.log, bench.log) are excluded by the repository-wide *.log ignore rule — as in the 4090D evidence directory — so they are not committed; their full text is embedded verbatim in sm90-h800/pr566_sm90_evidence.md and their hashes are recorded in original_server_sha256. included_files_sha256 covers the committed, redacted files.",
+    "binding": "Tested tree 40070d3 = a66c999 (default-backend change) plus the test-h3 merge (eae0118). Reference, CUDA backend, fixture and reference test are byte-identical to the 4090D snapshot; the dispatch and CUDA tests and the benchmark differ (a66c999 split one registry test into two and rewrote dispatch assertions; every kernel bit assertion is unchanged). After the run, commit ace9c20 changed only the benchmark's GPU-without-Triton and HIP/ROCm branches (not executed on the H800 host; the run took the NVIDIA + Triton branch, whose logic, order, samples and JSON keys are unchanged) plus documentation: current sha256 benchmarks/models/benchmark_h3_sigma_schedule.py 04e2403ec4093245583d48f0e8a1b8645d6810743cbb9534a762335251ed4d16, docs/operators/h3-sigma-schedule.md 8f31e87df382178a4001167a29ab53c7062d3eef1b577bf683c7817b6de11956. Those new branches were verified by CPU-only execution, _summarize simulations and static review; they have not run on GPU or HIP hardware."
+  }
+}
diff --git a/rl_engine/backends/cuda/model_specific/__init__.py b/rl_engine/backends/cuda/model_specific/__init__.py
index 3b09d3c11..9ed43ae29 100644
--- a/rl_engine/backends/cuda/model_specific/__init__.py
+++ b/rl_engine/backends/cuda/model_specific/__init__.py
@@ -1,2 +1,4 @@
 # SPDX-License-Identifier: Apache-2.0
-"""CUDA implementations with model-specific arithmetic contracts."""
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""Triton CUDA backend for model-specific operators (RFC #420 MiniMax-H3)."""
diff --git a/rl_engine/backends/cuda/model_specific/minimax_h3/__init__.py b/rl_engine/backends/cuda/model_specific/minimax_h3/__init__.py
index 86cf4c9da..572c4ac13 100644
--- a/rl_engine/backends/cuda/model_specific/minimax_h3/__init__.py
+++ b/rl_engine/backends/cuda/model_specific/minimax_h3/__init__.py
@@ -1,2 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 # Copyright (c) 2026 RL-Kernel Contributors
+
+"""MiniMax-H3 (RFC #420) model-specific CUDA backends."""
+
+from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import H3SigmaScheduleCudaOp
+
+__all__ = ["H3SigmaScheduleCudaOp"]
diff --git a/rl_engine/backends/cuda/model_specific/minimax_h3/sigma_schedule.py b/rl_engine/backends/cuda/model_specific/minimax_h3/sigma_schedule.py
new file mode 100644
index 000000000..9bf31dc02
--- /dev/null
+++ b/rl_engine/backends/cuda/model_specific/minimax_h3/sigma_schedule.py
@@ -0,0 +1,331 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""Triton CUDA backend for the MiniMax-H3 sigma grid (RFC #420).
+
+NVIDIA only: the grid-transform division is emitted as inline PTX
+``div.rn.f32`` (see below), which makes the kernels NVIDIA-specific. HIP is
+not supported by this backend; the registry does not offer it on rocm.
+
+The grid is built **on the device**: no CPU construction followed by a copy,
+and no torch factory functions whose GPU kernels differ bitwise from the CPU
+reference. The bit-level target is the pinned CPU fixture in
+``tests/reference/minimax_h3/`` (upstream diffusers ``set_timesteps`` at commit
+``f53d552``), reproduced here by:
+
+* ``linspace`` law: ``step = fl32(-1 / (n-1))``; for ``idx < n//2`` the value
+  is ``fl32(1.0 + fp64(step) * fp64(idx))``, otherwise
+  ``fl32(0.0 - fp64(step) * fp64(n-1-idx))`` (two-sided, single rounding);
+* shift arithmetic with the scalar roundings torch applies to python-float
+  operands: ``fl32(shift)`` and ``fl32(shift - 1.0)`` computed first, then
+  mul / mul+add / div — each fp32 step evaluated through an exact fp64
+  intermediate rounded once to fp32 (bit-identical to the correctly rounded,
+  non-FTZ fp32 op that torch's CPU kernels perform; fp32 x fp32 products and
+  sums are exact in fp64). Plain Triton fp32 mul/add may compile
+  flush-to-zero, which destroys the subnormal numerators of subnormal shifts
+  and broke parity (independent audit 2026-10-16);
+* correctly-rounded, non-FTZ fp32 division emitted as inline PTX
+  ``div.rn.f32``. Two measured findings forced this: (1) on Triton 3.0.0 /
+  RTX 4090D ``tl.fdiv(..., ieee_rounding=True)`` and the ``/`` operator were
+  bit-identical to each other and NOT correctly rounded (64707 mismatched
+  elements vs the CPU division across the fingerprint grids — probe
+  artifacts/.../diag/div_probe.py); (2) on Triton 3.1.0 the libdevice
+  ``div_rn`` binding flushed subnormal DIVIDENDS — ``div_rn(2^-149, +0.0)``
+  returned NaN instead of +inf and subnormal/normal returned +0, collapsing
+  the ``1e-45`` grid (probe artifacts/.../diag/subnormal_probe.py). The bare
+  PTX instruction carries no ``.ftz`` modifier, so IEEE subnormal semantics
+  hold; ``enable_fp_fusion=False`` on every floating-point launch, so no
+  multiply-add is contracted into an FMA (fused and separate roundings
+  differ on real grids, e.g. N=50, shift=12);
+* ``unique_consecutive`` semantics: keep an element when it is not IEEE-equal
+  to its predecessor (NaN never equals, so NaN rows are kept, matching torch);
+* ``timesteps = fl32(1.0 - sigma)`` for the first ``M - 1`` sigmas, with NaN
+  sigmas passed through unchanged (torch CPU returns the quiet NaN operand
+  itself from ``1.0 - NaN``, sign and payload included).
+
+NaN and near-zero parity (independent GPU audit 2026-10-16):
+
+* A NaN ``fl32(shift)`` propagates its own quieted bits through the whole
+  grid on the CPU oracle — sign included (``+NaN`` -> ``0x7fc00000``,
+  ``-NaN`` -> ``0xffc00000``; quieting = setting bit 22). ``forward``
+  detects NaN/inf scalars on the host and fills the grid directly with the
+  oracle's pattern; the device kernel canonicalizes NaNs to ``0x7fffffff``,
+  which is why the fill exists.
+* An infinite ``fl32(shift)`` (``inf``, or a finite shift above the fp32
+  range such as ``1e39`` / ``3.5e38``) makes every element an invalid
+  operation (``inf/inf``, or ``inf*0`` at the terminal zero), which x86/SSE
+  evaluates to the default quiet NaN ``0xffc00000`` regardless of sign.
+* A subnormal ``fl32(shift)`` (e.g. ``1e-45`` rounds up to the minimum
+  subnormal ``2^-149``) takes the normal kernel path: element 0 is
+  ``2^-149 / +0.0 = +inf`` and the remaining elements are subnormal
+  quotients — upstream keeps e.g. 10 of 25 rows for ``1e-45``.
+* A shift whose ``fl32`` underflows to ``+0.0`` (e.g. ``1e-46``) makes
+  element 0 the invalid ``+0.0 / +0.0``: the kernel canonicalizes NaN
+  division results to the CPU's ``0xffc00000`` (finite shifts CAN produce
+  exactly this one NaN — the denominator ``1 + fl32(shift-1)*s`` is exactly
+  ``+0.0`` at ``s = 1`` when ``fl32(shift)`` is tiny).
+
+Dedup runs as one single-program kernel (sequential block scan), so the
+compaction order is deterministic for any ``N``. The output length ``M`` is
+read back with one host synchronization of a device counter — the only sync;
+sigma values never leave the device.
+
+Availability: constructing the op raises ``ImportError`` when Triton is not
+importable, so the registry's first-available-candidate selection skips this
+backend at construction time instead of failing later in ``forward``.
+"""
+
+from __future__ import annotations
+
+import math
+
+import torch
+
+try:
+    import triton
+    import triton.language as tl
+
+    # Correctly-rounded fp32 division (PTX div.rn.f32). The import path moved
+    # across Triton versions; both known layouts are accepted.
+    try:
+        from triton.language.extra import libdevice as _libdevice
+    except ImportError:  # pragma: no cover - alternative Triton layout
+        from triton.language.extra.cuda import libdevice as _libdevice
+
+    _TRITON_AVAILABLE = True
+except ImportError:  # pragma: no cover - exercised only without a Triton wheel
+    _TRITON_AVAILABLE = False
+
+from rl_engine.reference.minimax_h3.sigma_schedule import H3SigmaSchedule
+
+_BLOCK = 1024
+
+
+def _shift_scalars(shift: float) -> tuple[float, float]:
+    """Round the two python-float scalars exactly as torch would.
+
+    ``fl32(shift)`` and ``fl32(shift - 1.0)`` with the subtraction in fp64
+    first — pinned on the CPU device so an ambient default device (meta,
+    CUDA) cannot move the factory or add a synchronization. These are the
+    only host-side roundings; the grid itself is built by the kernels.
+    """
+
+    shift_f32 = torch.tensor(shift, dtype=torch.float32, device="cpu").item()
+    shift_m1_f32 = torch.tensor(shift - 1.0, dtype=torch.float32, device="cpu").item()
+    return shift_f32, shift_m1_f32
+
+
+if _TRITON_AVAILABLE:
+
+    @triton.jit
+    def _shifted_grid_kernel(
+        out_ptr,
+        n,
+        shift_f32,
+        shift_m1_f32,
+        BLOCK: tl.constexpr,
+    ):
+        offs = tl.program_id(0) * BLOCK + tl.arange(0, BLOCK)
+        mask = offs < n
+
+        # Base grid, pinned CPU linspace law: fp32 step, two-sided fp64
+        # accumulate with a single rounding to fp32. The step division uses
+        # div_rn like the main transform (tl.fdiv's ieee_rounding flag is not
+        # correctly rounded on the validated Triton 3.0.0, see module docs).
+        step32 = _libdevice.div_rn(-1.0, (n - 1).to(tl.float32))
+        step64 = step32.to(tl.float64)
+        half = n // 2
+        start_side = 1.0 + step64 * offs.to(tl.float64)
+        end_side = 0.0 - step64 * (n - 1 - offs).to(tl.float64)
+        base = tl.where(offs < half, start_side, end_side).to(tl.float32)
+
+        # Shift transform with pre-rounded scalars. Every fp32 step is
+        # computed through an exact fp64 intermediate rounded once to fp32:
+        # an fp32 x fp32 product or sum is exactly representable in fp64, so
+        # this is bit-identical to the correctly rounded (round-to-nearest,
+        # NON-FTZ) fp32 op that torch's CPU (SSE) kernels perform. Plain
+        # Triton fp32 mul/add may compile flush-to-zero, which zeros the
+        # subnormal numerators of subnormal shifts (fl32(1e-45) = 2^-149) and
+        # broke upstream parity (independent audit 2026-10-16).
+        base64 = base.to(tl.float64)
+        numerator = (shift_f32.to(tl.float64) * base64).to(tl.float32)
+        inner = (shift_m1_f32.to(tl.float64) * base64).to(tl.float32)
+        denominator = (1.0 + inner.to(tl.float64)).to(tl.float32)
+
+        # Division via inline PTX div.rn.f32: correctly rounded AND non-FTZ
+        # (no .ftz modifier — IEEE subnormal handling, nonzero/0 -> inf).
+        # The libdevice div_rn binding was measured on Triton 3.1.0 / RTX
+        # 4090D to flush subnormal DIVIDENDS: div_rn(2^-149, +0.0) returned
+        # NaN instead of +inf and subnormal/normal returned +0, collapsing
+        # the 1e-45 grid (probe: remote/diag/subnormal_probe.py). This makes
+        # the kernel NVIDIA-PTX-specific — see the module docstring.
+        value = tl.inline_asm_elementwise(
+            "div.rn.f32 $0, $1, $2;",
+            "=r,r,r",
+            [numerator, denominator],
+            dtype=tl.float32,
+            is_pure=True,
+            pack=1,
+        )
+
+        # NaN canonicalization for finite fl32(shift): the only NaN source is
+        # the invalid 0/+0 at element 0 — a shift whose fl32 underflows to
+        # +0.0 (e.g. 1e-46) makes (shift-1)*1 round to -1.0 and the
+        # denominator exactly +0.0 there while the numerator is +0.0. torch
+        # CPU evaluates 0/+0 to the x86 default quiet NaN 0xffc00000 (sign
+        # bit SET); the device division yields 0x7fffffff. Rewrite NaN
+        # results to the CPU bit pattern. (A subnormal fl32(shift) such as
+        # 1e-45 takes numerator 2^-149 / +0.0 = +inf — a valid IEEE result —
+        # and flows through untouched.)
+        value_int = value.to(tl.int32, bitcast=True)
+        cpu_qnan = tl.full([BLOCK], -4194304, tl.int32)  # 0xffc00000 signed
+        out_int = tl.where(value != value, cpu_qnan, value_int)
+        tl.store(out_ptr + offs, out_int.to(tl.float32, bitcast=True), mask=mask)
+
+    @triton.jit
+    def _unique_consecutive_kernel(
+        src_ptr,
+        dst_ptr,
+        count_ptr,
+        n,
+        BLOCK: tl.constexpr,
+    ):
+        # Single program: sequential over blocks, so the scan order — and
+        # therefore the compaction result — is deterministic for any n.
+        running = tl.zeros((1,), dtype=tl.int32)
+        for start in range(0, n, BLOCK):
+            offs = start + tl.arange(0, BLOCK)
+            mask = offs < n
+            cur = tl.load(src_ptr + offs, mask=mask, other=0.0)
+            # offs == 0 sees NaN as "previous" and is always kept; IEEE
+            # equality keeps NaN rows (NaN != NaN), matching torch.
+            prev = tl.load(src_ptr + offs - 1, mask=mask & (offs > 0), other=float("nan"))
+            keep = mask & (cur != prev)
+            keep_i32 = keep.to(tl.int32)
+            dest = running + tl.cumsum(keep_i32, axis=0) - keep_i32
+            tl.store(dst_ptr + dest, cur, mask=keep)
+            running = running + tl.sum(keep_i32, axis=0)
+        tl.store(count_ptr + tl.arange(0, 1), running)
+
+    @triton.jit
+    def _timesteps_kernel(sig_ptr, out_ptr, m, BLOCK: tl.constexpr):
+        offs = tl.program_id(0) * BLOCK + tl.arange(0, BLOCK)
+        mask = offs < m - 1
+        sigma = tl.load(sig_ptr + offs, mask=mask, other=0.0)
+        # 1 - sigma, except NaN sigmas pass through unchanged: torch CPU
+        # (SSE) returns the quiet NaN operand itself from 1.0 - NaN — payload
+        # and sign included — while the device subtract would canonicalize to
+        # 0x7fffffff. The grid's NaNs are already in CPU bit form, so copying
+        # sigma reproduces the CPU result for both NaN signs.
+        timesteps = tl.where(sigma != sigma, sigma, 1.0 - sigma)
+        tl.store(out_ptr + offs, timesteps, mask=mask)
+
+
+class H3SigmaScheduleCudaOp:
+    """Device-side H3 sigma grid via Triton (NVIDIA CUDA only)."""
+
+    def __init__(self) -> None:
+        # Platform gate first: the kernels emit inline PTX (div.rn.f32) and
+        # cannot run on AMD. Raising ImportError — like the Triton check
+        # below — keeps the registry's candidate-skip semantics
+        # (docs/architecture/runtime-dispatch.md) intact if this class ever
+        # appears in a HIP device table; construction fails here, long
+        # before any Triton compilation is attempted.
+        if torch.version.hip is not None:
+            raise ImportError(
+                "H3SigmaScheduleCudaOp is NVIDIA-only: its kernels emit inline "
+                "PTX div.rn.f32 for exact IEEE division and cannot run on "
+                "HIP/ROCm. Use the PyTorch reference "
+                "(rl_engine.reference.minimax_h3.sigma_schedule) on AMD."
+            )
+        if not _TRITON_AVAILABLE:
+            # Construction-time failure lets the registry's candidate loop
+            # skip this backend (docs/architecture/runtime-dispatch.md);
+            # forward-time errors are never used for selection.
+            raise ImportError("triton is required for H3SigmaScheduleCudaOp")
+
+    def __call__(
+        self,
+        num_inference_steps: int,
+        *,
+        shift: float,
+        device: str | torch.device | None = None,
+    ) -> H3SigmaSchedule:
+        return self.forward(num_inference_steps, shift=shift, device=device)
+
+    def forward(
+        self,
+        num_inference_steps: int,
+        *,
+        shift: float,
+        device: str | torch.device | None = None,
+    ) -> H3SigmaSchedule:
+        """Build the grid on the target device; see the module docstring."""
+        # Same checks and messages as the CPU reference (upstream's own
+        # failures; no extra policy).
+        if num_inference_steps < 2:
+            raise ValueError(
+                "num_inference_steps must be >= 2 (terminal zero included), got "
+                f"{num_inference_steps}."
+            )
+        if shift <= 0:
+            raise ValueError(f"`shift` must be positive, got {shift}.")
+
+        target = torch.device(device) if device is not None else torch.device("cuda")
+        if target.type != "cuda":
+            raise ValueError(
+                "H3SigmaScheduleCudaOp builds the grid on an NVIDIA CUDA device "
+                "(the kernels are NVIDIA-only); pass device='cuda' or use the "
+                "PyTorch reference for CPU or AMD platforms."
+            )
+
+        n = int(num_inference_steps)
+        shift_f32, shift_m1_f32 = _shift_scalars(shift)
+
+        # NaN/inf scalar fast path (module docstring "NaN payloads"). A NaN
+        # fl32(shift) propagates its own quieted bits through the whole grid
+        # on the CPU oracle — SIGN INCLUDED, so -NaN yields 0xffc00000 while
+        # +NaN yields 0x7fc00000 (quieting = setting bit 22). An infinite
+        # fl32(shift) makes every element an invalid operation (inf/inf, or
+        # inf*0 at the terminal zero), which x86 evaluates to the default
+        # quiet NaN 0xffc00000 regardless of the shift's sign. The device
+        # kernel canonicalizes NaNs to 0x7fffffff instead, so these grids are
+        # filled directly with the oracle's bit patterns. All NaN rows
+        # survive unique_consecutive (IEEE !=), so M = n.
+        if math.isnan(shift_f32) or math.isinf(shift_f32):
+            if math.isinf(shift_f32):
+                payload = 0xFFC00000
+            else:
+                raw = int(
+                    torch.tensor(shift, dtype=torch.float32, device="cpu").view(torch.int32).item()
+                )
+                payload = raw & 0xFFFFFFFF | 0x00400000  # quiet the NaN bits
+            signed = payload if payload < 0x80000000 else payload - 0x1_0000_0000
+            with torch.cuda.device(target):
+                bits = torch.full((n,), signed, dtype=torch.int32, device=target)
+                sigmas = bits.view(torch.float32)
+                timesteps = sigmas[: n - 1].clone()
+            return H3SigmaSchedule(sigmas=sigmas, timesteps=timesteps, num_model_evals=n - 1)
+
+        # Device guard: allocations, Triton launches (which use the current
+        # device/stream) and the count read must all target `target`, also
+        # when it is not the current device (cuda:k on multi-GPU hosts).
+        with torch.cuda.device(target):
+            grid = torch.empty(n, dtype=torch.float32, device=target)
+            compacted = torch.empty(n, dtype=torch.float32, device=target)
+            count = torch.empty(1, dtype=torch.int32, device=target)
+
+            blocks = triton.cdiv(n, _BLOCK)
+            _shifted_grid_kernel[(blocks,)](
+                grid, n, shift_f32, shift_m1_f32, BLOCK=_BLOCK, enable_fp_fusion=False
+            )
+            _unique_consecutive_kernel[(1,)](grid, compacted, count, n, BLOCK=_BLOCK)
+            # The single allowed host synchronization: the deduplicated length.
+            m = int(count.item())
+            sigmas = compacted[:m]
+            timesteps = torch.empty(m - 1, dtype=torch.float32, device=target)
+            if m > 1:
+                _timesteps_kernel[(triton.cdiv(m - 1, _BLOCK),)](
+                    compacted, timesteps, m, BLOCK=_BLOCK, enable_fp_fusion=False
+                )
+        return H3SigmaSchedule(sigmas=sigmas, timesteps=timesteps, num_model_evals=m - 1)
diff --git a/rl_engine/reference/minimax_h3/__init__.py b/rl_engine/reference/minimax_h3/__init__.py
index e54c60b77..7570ffbd7 100644
--- a/rl_engine/reference/minimax_h3/__init__.py
+++ b/rl_engine/reference/minimax_h3/__init__.py
@@ -11,6 +11,21 @@
 
 from __future__ import annotations
 
+from rl_engine.reference.minimax_h3.sigma_schedule import H3SigmaSchedule, NativeH3SigmaScheduleOp
+
+__all__ = [
+    "H3SigmaSchedule",
+    "H3_ADALN_CHUNK_NAMES",
+    "H3_ADALN_CHUNKS",
+    "H3_FREQ_DIM",
+    "H3_HIDDEN_SIZE",
+    "H3_MAX_PERIOD",
+    "H3_MODALITY_NUM",
+    "H3_TIME_EMBED_DIM",
+    "H3_TIME_EMBED_HIDDEN_DIM",
+    "NativeH3SigmaScheduleOp",
+]
+
 H3_FREQ_DIM = 256
 H3_MAX_PERIOD = 10000
 H3_TIME_EMBED_HIDDEN_DIM = 5376
diff --git a/rl_engine/reference/minimax_h3/sigma_schedule.py b/rl_engine/reference/minimax_h3/sigma_schedule.py
new file mode 100644
index 000000000..f2a22ed90
--- /dev/null
+++ b/rl_engine/reference/minimax_h3/sigma_schedule.py
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""FP32 reference for the MiniMax-H3 sigma grid (RFC #420 ``h3_sigma_schedule``).
+
+Upstream: ``MiniMaxH3Scheduler.set_timesteps`` in diffusers
+``schedulers/scheduling_minimax_h3.py``, pinned to git blob sha
+``ca69ae6a2f6aae5bb68498216316a71eb07c1f7b``. The file was added once, in
+commit f53d552036a0d1bd5570782a39cd40cfabf112bc ("Add MiniMax-H3 (#14355)",
+2026-08-05), and has not changed since:
+https://github.com/huggingface/diffusers/blob/f53d552/src/diffusers/schedulers/scheduling_minimax_h3.py
+The construction order is byte-frozen against that source:
+
+    linspace(1, 0, N, float32)             # CPU
+    -> shift * s / (1 + (shift - 1) * s)   # python-float scalar operands
+    -> unique_consecutive                  # collapse fp32 collisions near s=1
+    -> timesteps = 1 - sigmas[:-1]         # t = 1 - sigma, t = 1 is clean
+
+Released checkpoints run one grid per modality — shift=12.0 for video,
+shift=3.0 for audio — so the grid is a per-call argument, not scheduler state.
+Every arithmetic step runs on CPU in float32; tensors move to ``device`` only
+after the grid is fully built. Consumers take sigma as a per-row input
+(PR #471 ``h3_ode_step``), so this operator carries no step index.
+"""
+
+from __future__ import annotations
+
+from dataclasses import dataclass
+
+import torch
+from torch import Tensor
+
+
+@dataclass(frozen=True)
+class H3SigmaSchedule:
+    """One MiniMax-H3 sigma grid.
+
+    Attributes:
+        sigmas: float32, shape ``[M]`` with ``M <= num_inference_steps``.
+            Strictly decreasing; ``sigmas[0] == 1.0`` exactly for the released
+            shifts (3.0, 12.0) and ``sigmas[-1] == 0.0`` exactly (the shift
+            maps 0 to 0).
+        timesteps: float32, shape ``[M - 1]``; ``timesteps = 1 - sigmas[:-1]``,
+            strictly increasing from ``0.0`` towards ``1.0``.
+        num_model_evals: ``M - 1``, the number of transformer evaluations the
+            grid drives (dedup included).
+    """
+
+    sigmas: Tensor
+    timesteps: Tensor
+    num_model_evals: int
+
+
+class NativeH3SigmaScheduleOp:
+    """Pure PyTorch reference for the H3 sigma grid — forward only."""
+
+    def __call__(
+        self,
+        num_inference_steps: int,
+        *,
+        shift: float,
+        device: str | torch.device | None = None,
+    ) -> H3SigmaSchedule:
+        return self.forward(num_inference_steps, shift=shift, device=device)
+
+    def forward(
+        self,
+        num_inference_steps: int,
+        *,
+        shift: float,
+        device: str | torch.device | None = None,
+    ) -> H3SigmaSchedule:
+        """Build the grid in the frozen order; see the module docstring."""
+        # Both checks mirror upstream's own failures and add no extra policy:
+        # num_inference_steps < 2 is set_timesteps' check (pinned blob,
+        # lines 149-153) and shift <= 0 the constructor's (lines 75-76).
+        if num_inference_steps < 2:
+            raise ValueError(
+                "num_inference_steps must be >= 2 (terminal zero included), got "
+                f"{num_inference_steps}."
+            )
+        if shift <= 0:
+            raise ValueError(f"`shift` must be positive, got {shift}.")
+
+        # Scalar operands must stay python floats in exactly this expression:
+        # pre-casting shift to a tensor or reassociating the division changes
+        # fp32 rounding and breaks byte equality with upstream (lines 156-159).
+        # device="cpu" is explicit because factory functions without a device
+        # follow the ambient default device (meta/CUDA context) instead.
+        base = torch.linspace(1.0, 0.0, int(num_inference_steps), dtype=torch.float32, device="cpu")
+        shift = float(shift)
+        sigmas = shift * base / (1 + (shift - 1) * base)
+        # The shift compresses spacing near sigma=1; drop the fp32 collisions
+        # it creates before deriving timesteps and the evaluation count.
+        sigmas = torch.unique_consecutive(sigmas)
+        timesteps = 1.0 - sigmas[:-1]
+
+        return H3SigmaSchedule(
+            sigmas=sigmas.to(device=device),
+            timesteps=timesteps.to(device=device),
+            num_model_evals=int(sigmas.numel()) - 1,
+        )
diff --git a/rl_engine/runtime/registry.py b/rl_engine/runtime/registry.py
index 1f1f3d0df..3b589a13d 100644
--- a/rl_engine/runtime/registry.py
+++ b/rl_engine/runtime/registry.py
@@ -208,6 +208,18 @@ class OpBackend(Enum, metaclass=_KernelEnumMeta):
     CUDA_SM90_LM_HEAD = "rl_engine.kernels.ops.cuda.linear.lm_head.SM90LMHeadOp"
     CUDA_SM90_EMBEDDING = "rl_engine.kernels.ops.cuda.linear.embedding.SM90EmbeddingOp"
 
+    # MiniMax-H3 (RFC #420) scheduler grid. The PyTorch reference is the
+    # legacy ``get_op`` default on every platform; the Triton CUDA backend is
+    # opt-in only — select it through the semantic path with
+    # requested_backend="rlkernel.h3_sigma_schedule.triton", or construct
+    # H3SigmaScheduleCudaOp directly (default backend change per review,
+    # PR #566).
+    PYTORCH_H3_SIGMA_SCHEDULE = (
+        "rl_engine.reference.minimax_h3.sigma_schedule.NativeH3SigmaScheduleOp"
+    )
+    CUDA_H3_SIGMA_SCHEDULE = (
+        "rl_engine.backends.cuda.model_specific.minimax_h3." "sigma_schedule.H3SigmaScheduleCudaOp"
+    )
     # MiniMax-H3 (RFC #420) conditioning path
     PYTORCH_H3_TIMESTEP_SINUSOID = (
         "rl_engine.reference.minimax_h3.timestep_sinusoid.NativeH3TimestepSinusoidOp"
@@ -488,6 +500,51 @@ def _default_semantic_descriptors() -> tuple[OperatorBackendDescriptor, ...]:
             fallback_policy=OperatorFallbackPolicy.RUNTIME_MANAGED,
             version_or_build_fingerprint="runtime-native-ffn-unresolved-v1",
         ),
+        # MiniMax-H3 sigma grid (RFC #420). Byte-frozen against the pinned
+        # upstream construction; see rl_engine/reference/minimax_h3/.
+        OperatorBackendDescriptor(
+            semantic_op="sigma_schedule_h3",
+            backend_id="rlkernel.h3_sigma_schedule.reference",
+            supported_targets=frozenset({"rollout", "training"}),
+            supported_devices=frozenset({"cpu", "cuda", "rocm"}),
+            supported_dtypes=frozenset({"float32"}),
+            supported_topologies={"*": "*"},
+            determinism_or_alignment_properties={
+                "algorithm": "upstream MiniMaxH3Scheduler.set_timesteps, fp32 pinned",
+                "batch_invariant": True,
+                "deterministic": True,
+                "strict_observable": True,
+            },
+            lifecycle=OperatorLifecycle.ENGINE_CONSTRUCTION,
+            implementation_class_or_factory=(
+                "rl_engine.reference.minimax_h3.sigma_schedule.NativeH3SigmaScheduleOp"
+            ),
+            fallback_policy=OperatorFallbackPolicy.ERROR,
+            version_or_build_fingerprint="NativeH3SigmaScheduleOp-v1",
+        ),
+        OperatorBackendDescriptor(
+            semantic_op="sigma_schedule_h3",
+            backend_id="rlkernel.h3_sigma_schedule.triton",
+            supported_targets=frozenset({"rollout", "training"}),
+            # NVIDIA-only backend (inline PTX div.rn.f32); HIP/ROCm stays
+            # on the reference — the kernels cannot run on AMD.
+            supported_devices=frozenset({"cuda"}),
+            supported_dtypes=frozenset({"float32"}),
+            supported_topologies={"*": "*"},
+            determinism_or_alignment_properties={
+                "algorithm": "device-side pinned law; ieee division, no FMA fusion",
+                "batch_invariant": True,
+                "deterministic": True,
+                "strict_observable": True,
+            },
+            lifecycle=OperatorLifecycle.ENGINE_CONSTRUCTION,
+            implementation_class_or_factory=(
+                "rl_engine.backends.cuda.model_specific.minimax_h3."
+                "sigma_schedule.H3SigmaScheduleCudaOp"
+            ),
+            fallback_policy=OperatorFallbackPolicy.ERROR,
+            version_or_build_fingerprint="H3SigmaScheduleTritonOp-v1",
+        ),
     )
 
 
@@ -751,6 +808,12 @@ def __init__(self):
                     OpBackend.TRITON_ROPE,
                     OpBackend.PYTORCH_NATIVE_ROPE,
                 ],
+                # Reference only, like every other platform: the device-side
+                # Triton build is slower than CPU build + copy at typical H3
+                # sizes and nothing requires on-device construction. Triton is
+                # opt-in via the semantic path or direct construction (see
+                # docs/operators/h3-sigma-schedule.md).
+                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],
                 "timestep_sinusoid_h3": [
                     OpBackend.CUDA_H3_TIMESTEP_SINUSOID,
                     OpBackend.PYTORCH_H3_TIMESTEP_SINUSOID,
@@ -791,6 +854,7 @@ def __init__(self):
                 "kv_cache_attention": [OpBackend.PYTORCH_NATIVE_KV_CACHE_ATTN],
                 "grpo_loss": [OpBackend.TRITON_GRPO_LOSS, OpBackend.PYTORCH_GRPO_LOSS],
                 "rope": [OpBackend.TRITON_ROPE, OpBackend.PYTORCH_NATIVE_ROPE],
+                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],
                 "linear_logp": [
                     OpBackend.TRITON_LINEAR_LOGP,
                     OpBackend.PYTORCH_LINEAR_LOGP,
@@ -839,6 +903,7 @@ def __init__(self):
                     OpBackend.PYTORCH_GRPO_LOSS,
                 ],
                 "rope": [OpBackend.TRITON_ROPE, OpBackend.PYTORCH_NATIVE_ROPE],
+                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],
                 "linear_logp": [
                     OpBackend.TRITON_LINEAR_LOGP,
                     OpBackend.PYTORCH_LINEAR_LOGP,
@@ -883,6 +948,7 @@ def __init__(self):
                 "kv_cache_attention": [OpBackend.PYTORCH_NATIVE_KV_CACHE_ATTN],
                 "grpo_loss": [OpBackend.PYTORCH_GRPO_LOSS],
                 "rope": [OpBackend.PYTORCH_NATIVE_ROPE],
+                "sigma_schedule_h3": [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE],
                 "linear_logp": [OpBackend.PYTORCH_LINEAR_LOGP],
                 "ratio_kl": [OpBackend.PYTORCH_RATIO_KL],
                 "pack": [OpBackend.PYTORCH_PACK],
diff --git a/tests/backends/cuda/test_h3_sigma_schedule_cuda.py b/tests/backends/cuda/test_h3_sigma_schedule_cuda.py
new file mode 100644
index 000000000..c6cecdb17
--- /dev/null
+++ b/tests/backends/cuda/test_h3_sigma_schedule_cuda.py
@@ -0,0 +1,412 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""Device tests for the Triton NVIDIA CUDA h3_sigma_schedule backend (RFC #420).
+
+The acceptance oracle is the pinned CPU fixture generated from the upstream
+diffusers scheduler (see tests/reference/minimax_h3/). GPU results are copied
+to the host only for comparison; no value is recomputed on the CPU.
+
+The backend is NVIDIA-only (its kernels emit inline PTX ``div.rn.f32``);
+the suite runs on NVIDIA CUDA hardware with a Triton wheel and skips
+without a GPU, on HIP/ROCm builds, and when the backend module cannot
+import Triton (same guard shape as the sibling Triton suite
+``tests/backends/cuda/test_h3_flash_attention.py``). It is opt-in
+everywhere: the
+legacy registry serves the PyTorch reference on CUDA too (default backend
+change per review, 2026-10-25), and the Triton class is reached through the
+semantic ``requested_backend`` or direct construction. The suite therefore
+constructs the backend directly for kernel checks and asserts that the default
+reference path matches it bit for bit.
+"""
+
+from __future__ import annotations
+
+import json
+import pathlib
+
+import pytest
+import torch
+
+from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import _TRITON_AVAILABLE
+
+pytestmark = pytest.mark.skipif(
+    not torch.cuda.is_available() or torch.version.hip is not None or not _TRITON_AVAILABLE,
+    reason="NVIDIA CUDA device and Triton wheel required: the Triton path is "
+    "NVIDIA-only (skipped without a GPU, on HIP/ROCm builds, and when Triton "
+    "is not importable)",
+)
+
+_FIXTURE_PATH = (
+    pathlib.Path(__file__).resolve().parents[2]
+    / "reference"
+    / "minimax_h3"
+    / "h3_sigma_schedule_upstream_fixture.json"
+)
+_EXPECTED_CASES = {(2, 3.0), (2, 12.0), (4, 3.0), (4, 12.0), (25, 3.0), (25, 12.0)}
+
+
+def _cuda_op():
+    from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import (
+        H3SigmaScheduleCudaOp,
+    )
+
+    return H3SigmaScheduleCudaOp()
+
+
+def _int32_bits(tensor: torch.Tensor) -> list[int]:
+    return tensor.detach().contiguous().view(torch.int32).tolist()
+
+
+def _fixture_bits(bits: list[str]) -> list[int]:
+    return [int(value, 16) for value in bits]
+
+
+def test_matches_pinned_cpu_fixture_bitwise():
+    fixture = json.loads(_FIXTURE_PATH.read_text(encoding="utf-8"))
+    assert fixture["upstream"]["blob_sha1"] == "ca69ae6a2f6aae5bb68498216316a71eb07c1f7b"
+
+    actual_cases = [(case["num_inference_steps"], case["shift"]) for case in fixture["cases"]]
+    assert set(actual_cases) == _EXPECTED_CASES
+
+    op = _cuda_op()
+    for case in fixture["cases"]:
+        schedule = op(case["num_inference_steps"], shift=case["shift"])
+
+        assert schedule.sigmas.is_cuda
+        assert schedule.sigmas.dtype is torch.float32
+        assert tuple(schedule.sigmas.shape) == (case["sigmas_count"],)
+        assert _int32_bits(schedule.sigmas.cpu()) == _fixture_bits(case["sigmas_bits"])
+
+        assert schedule.timesteps.is_cuda
+        assert schedule.timesteps.dtype is torch.float32
+        assert tuple(schedule.timesteps.shape) == (case["timesteps_count"],)
+        expected = _fixture_bits(case["timesteps_bits"])
+        assert _int32_bits(schedule.timesteps.cpu()) == expected
+
+        assert schedule.num_model_evals == case["num_model_evals"]
+
+
+@pytest.mark.parametrize(
+    ("num_inference_steps", "shift"),
+    [
+        # N=50, shift=12 covers the fusion-sensitive elements (e.g. index 16)
+        # where a contracted FMA and separate mul/add roundings differ in the
+        # CPU simulation; the launch disables fp fusion and this comparison is
+        # the hardware verdict.
+        (50, 12.0),
+        (50, 3.0),
+        (1000, 12.0),
+    ],
+)
+def test_matches_live_cpu_reference_bitwise(num_inference_steps, shift):
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(num_inference_steps, shift=shift)
+    actual = _cuda_op()(num_inference_steps, shift=shift)
+
+    assert _int32_bits(actual.sigmas.cpu()) == _int32_bits(expected.sigmas)
+    assert _int32_bits(actual.timesteps.cpu()) == _int32_bits(expected.timesteps)
+    assert actual.num_model_evals == expected.num_model_evals
+
+
+def test_dense_grid_dedup_matches_cpu_reference():
+    # shift=12 creates fp32 collisions near sigma=1 at this density: the grid
+    # collapses by ~4%, so the compaction path is genuinely exercised.
+    n = 1_000_000
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(n, shift=12.0)
+    actual = _cuda_op()(n, shift=12.0)
+
+    assert actual.sigmas.numel() < n
+    assert actual.sigmas.numel() == expected.sigmas.numel()
+    assert _int32_bits(actual.sigmas.cpu()) == _int32_bits(expected.sigmas)
+    assert _int32_bits(actual.timesteps.cpu()) == _int32_bits(expected.timesteps)
+    assert actual.num_model_evals == expected.num_model_evals
+
+
+def test_reference_with_cuda_device_preserves_fixture_bytes():
+    # Path-B oracle (the benchmark's no-GPU-backend baseline): same CPU build,
+    # then the operator moves sigmas/timesteps to the GPU. The move must
+    # preserve the pinned bytes — this also guards against a later
+    # "optimization" building the grid directly on the device inside the
+    # reference, which would silently change its arithmetic.
+    fixture = json.loads(_FIXTURE_PATH.read_text(encoding="utf-8"))
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    op = NativeH3SigmaScheduleOp()
+    for case in fixture["cases"]:
+        schedule = op(case["num_inference_steps"], shift=case["shift"], device="cuda")
+
+        assert schedule.sigmas.is_cuda and schedule.timesteps.is_cuda
+        assert _int32_bits(schedule.sigmas.cpu()) == _fixture_bits(case["sigmas_bits"])
+        assert _int32_bits(schedule.timesteps.cpu()) == _fixture_bits(case["timesteps_bits"])
+        assert schedule.num_model_evals == case["num_model_evals"]
+
+
+@pytest.mark.parametrize("shift", [3.0, 12.0])
+@pytest.mark.parametrize("num_inference_steps", [2, 4, 25])
+def test_grid_invariants_on_device(num_inference_steps, shift):
+    schedule = _cuda_op()(num_inference_steps, shift=shift)
+    sigmas = schedule.sigmas
+    timesteps = schedule.timesteps
+
+    assert sigmas.is_cuda and timesteps.is_cuda
+    assert sigmas.dtype is torch.float32 and timesteps.dtype is torch.float32
+    assert sigmas[0].item() == 1.0
+    assert sigmas[-1].item() == 0.0
+    assert bool((sigmas[1:] < sigmas[:-1]).all())
+    assert bool((timesteps[1:] > timesteps[:-1]).all())
+    assert timesteps[0].item() == 0.0
+    assert schedule.num_model_evals == sigmas.numel() - 1 == timesteps.numel()
+
+
+@pytest.mark.parametrize("num_inference_steps", [1, 0, -4])
+def test_rejects_num_inference_steps_below_two(num_inference_steps):
+    with pytest.raises(ValueError, match="num_inference_steps"):
+        _cuda_op()(num_inference_steps, shift=12.0)
+
+
+# --- Edge-consistency regression (independent GPU audit 2026-10-16) -------
+#
+# These four cases come from the independent audit's counterexamples, each
+# confirmed against the AST-executed pinned upstream set_timesteps
+# (upstream-counterexamples.json): the CPU reference matches upstream on all
+# of them, so the device path must match the reference bitwise. Landmark
+# bits/lengths from the upstream execution are asserted directly so the
+# oracle does not depend on the local reference staying correct.
+
+
+def _assert_bitwise_match(reference, actual):
+    assert tuple(actual.sigmas.shape) == tuple(reference.sigmas.shape)
+    assert tuple(actual.timesteps.shape) == tuple(reference.timesteps.shape)
+    assert actual.num_model_evals == reference.num_model_evals
+    assert _int32_bits(actual.sigmas.cpu()) == _int32_bits(reference.sigmas)
+    assert _int32_bits(actual.timesteps.cpu()) == _int32_bits(reference.timesteps)
+
+
+def test_subnormal_shift_1e_45_matches_reference_upstream_parity():
+    # fl32(1e-45) rounds UP to the minimum subnormal 2^-149 (bit pattern 1):
+    # upstream grid = [+inf, subnormal quotients..., 0.0] with N=25 collapsing
+    # to 10 rows. A flush-to-zero device multiply turns the numerator into 0
+    # and produced [NaN, 0.0] (length 2) before the fix.
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(25, shift=1e-45)
+    actual = _cuda_op()(25, shift=1e-45)
+
+    _assert_bitwise_match(expected, actual)
+    # Landmarks from the pinned upstream execution:
+    assert expected.sigmas.numel() == 10
+    assert _int32_bits(actual.sigmas.cpu())[0] == 0x7F800000  # +inf
+
+
+def test_underflow_shift_1e_46_matches_reference_upstream_parity():
+    # fl32(1e-46) underflows to +0.0: element 0 is 0/+0, an invalid operation
+    # whose torch-CPU (x86) result is the DEFAULT QUIET NaN WITH SIGN BIT SET
+    # (0xffc00000); the rest of the grid is +0.0, so upstream keeps 2 rows.
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(25, shift=1e-46)
+    actual = _cuda_op()(25, shift=1e-46)
+
+    _assert_bitwise_match(expected, actual)
+    assert expected.sigmas.numel() == 2
+    assert _int32_bits(actual.sigmas.cpu())[0] == -4194304  # 0xffc00000, signed
+
+
+def test_positive_nan_shift_propagates_positive_quiet_nan():
+    # shift=+NaN: torch CPU propagates the (quieted) input NaN bits through
+    # the whole grid -> 0x7fc00000 everywhere, sign included.
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(25, shift=float("nan"))
+    actual = _cuda_op()(25, shift=float("nan"))
+
+    _assert_bitwise_match(expected, actual)
+    assert set(_int32_bits(actual.sigmas.cpu())) == {0x7FC00000}
+
+
+def test_negative_nan_shift_propagates_negative_quiet_nan():
+    # shift=-NaN: same propagation, but the SIGN BIT travels with the payload
+    # -> 0xffc00000 everywhere (the fixed positive fill was wrong here).
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(25, shift=-float("nan"))
+    actual = _cuda_op()(25, shift=-float("nan"))
+
+    _assert_bitwise_match(expected, actual)
+    assert set(_int32_bits(actual.sigmas.cpu())) == {-4194304}  # 0xffc00000, signed
+
+
+def test_nan_path_timesteps_do_not_alias_sigmas_storage():
+    # The NaN/inf fast path slices sigmas for timesteps; the slice must own its
+    # storage like every other path here (the kernel path writes into a fresh
+    # torch.empty) and like the reference, whose ``1.0 - sigmas[:-1]`` is a new
+    # tensor. An in-place write to timesteps must not bleed into sigmas — the
+    # bitwise tests above cannot catch aliasing because the two NaN grids carry
+    # identical bit patterns.
+    schedule = _cuda_op()(25, shift=float("nan"))
+
+    bits_before = _int32_bits(schedule.sigmas.cpu())
+    schedule.timesteps.fill_(123.0)
+    assert _int32_bits(schedule.sigmas.cpu()) == bits_before
+
+
+_EDGE_SHIFTS = [
+    float("nan"),  # all-NaN grid; IEEE != keeps every row (matches upstream)
+    float("inf"),  # all-NaN grid via fp32 scalar overflow semantics
+    1e-10,  # +inf first sigma: (1e-10 - 1.0) rounds to exactly -1.0 in fp32
+    1e39,  # fp32-overflowing shift -> NaN grid
+    3.5e38,  # just above float32 max -> NaN grid
+    1e30,  # extreme finite shift collapses the grid to [1.0, 0.0]
+]
+
+
+@pytest.mark.parametrize("shift", _EDGE_SHIFTS)
+def test_edge_shifts_match_reference_upstream_parity(shift):
+    # contract-audit.md §2 proved the CPU reference bit-identical to the
+    # actually-executed upstream set_timesteps on exactly these inputs, so
+    # the device path must reproduce the reference bytes, NaN grids included.
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(8, shift=shift)
+    actual = _cuda_op()(8, shift=shift)
+
+    assert actual.num_model_evals == expected.num_model_evals
+    assert tuple(actual.sigmas.shape) == tuple(expected.sigmas.shape)
+    assert tuple(actual.timesteps.shape) == tuple(expected.timesteps.shape)
+    assert _int32_bits(actual.sigmas.cpu()) == _int32_bits(expected.sigmas)
+    assert _int32_bits(actual.timesteps.cpu()) == _int32_bits(expected.timesteps)
+
+
+@pytest.mark.parametrize(("num_inference_steps", "truncated_to"), [(2.9, 2), (3.1, 3)])
+def test_float_num_steps_truncate_like_reference(num_inference_steps, truncated_to):
+    # Upstream parity: int() truncation, device side must agree with both the
+    # reference call and the truncated integer grid.
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    expected = NativeH3SigmaScheduleOp()(num_inference_steps, shift=12.0)
+    integer_grid = NativeH3SigmaScheduleOp()(truncated_to, shift=12.0)
+    actual = _cuda_op()(num_inference_steps, shift=12.0)
+
+    assert _int32_bits(expected.sigmas) == _int32_bits(integer_grid.sigmas)
+    assert _int32_bits(actual.sigmas.cpu()) == _int32_bits(expected.sigmas)
+    assert _int32_bits(actual.timesteps.cpu()) == _int32_bits(expected.timesteps)
+    assert actual.num_model_evals == expected.num_model_evals
+
+
+@pytest.mark.parametrize("shift", [0.0, -1.5, float("-inf")])
+def test_rejects_non_positive_shift(shift):
+    with pytest.raises(ValueError, match="positive"):
+        _cuda_op()(8, shift=shift)
+
+
+def test_rejects_cpu_device_instead_of_silent_fallback():
+    with pytest.raises(ValueError, match="NVIDIA CUDA device"):
+        _cuda_op()(25, shift=12.0, device="cpu")
+
+
+def test_repeated_and_interleaved_calls_are_stable():
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    cuda_op = _cuda_op()
+    cpu_op = NativeH3SigmaScheduleOp()
+
+    first = cuda_op(25, shift=12.0)
+    cpu_op(25, shift=3.0)  # interleaved CPU call must not pollute device state
+    second = cuda_op(25, shift=3.0)
+    third = cuda_op(25, shift=12.0)
+
+    assert _int32_bits(first.sigmas.cpu()) == _int32_bits(third.sigmas.cpu())
+    assert _int32_bits(first.timesteps.cpu()) == _int32_bits(third.timesteps.cpu())
+    assert _int32_bits(second.timesteps.cpu()) != _int32_bits(first.timesteps.cpu())
+
+
+def test_backend_identity_is_device_path_not_cpu_fallback():
+    from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import (
+        H3SigmaScheduleCudaOp,
+    )
+    from rl_engine.runtime.registry import OpBackend
+
+    # Both backends stay registered as enum members; the legacy "cuda" list
+    # carries only the reference (Triton is opt-in). The outputs above came
+    # from the directly constructed Triton class, proving the device path ran.
+    assert OpBackend.CUDA_H3_SIGMA_SCHEDULE.value.endswith(
+        "model_specific.minimax_h3.sigma_schedule.H3SigmaScheduleCudaOp"
+    )
+    assert OpBackend.PYTORCH_H3_SIGMA_SCHEDULE.value.endswith(
+        "reference.minimax_h3.sigma_schedule.NativeH3SigmaScheduleOp"
+    )
+
+    schedule = H3SigmaScheduleCudaOp()(8, shift=3.0)
+    assert schedule.sigmas.device.type == "cuda"
+    assert torch.version.hip is None  # NVIDIA-only backend
+
+
+def test_public_entry_defaults_to_reference_and_matches_triton_bits():
+    # Default backend change per review (2026-10-25): legacy ``get_op`` hands
+    # out the PyTorch reference on CUDA devices (CPU build + host-to-device
+    # copy) and the Triton class is opt-in. The switch is only safe because the
+    # two paths are bit-identical — pin that equality here, on hardware, for
+    # both outputs and the evaluation count.
+    from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import (
+        H3SigmaScheduleCudaOp,
+    )
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+    from rl_engine.runtime.registry import kernel_registry
+
+    op = kernel_registry.get_op("sigma_schedule_h3", device="cuda")
+    assert isinstance(op, NativeH3SigmaScheduleOp)
+
+    default = op(25, shift=12.0, device="cuda")
+    device_side = H3SigmaScheduleCudaOp()(25, shift=12.0)
+    assert default.sigmas.is_cuda and default.timesteps.is_cuda
+    assert _int32_bits(default.sigmas.cpu()) == _int32_bits(device_side.sigmas.cpu())
+    assert _int32_bits(default.timesteps.cpu()) == _int32_bits(device_side.timesteps.cpu())
+    assert default.num_model_evals == device_side.num_model_evals
+    assert torch.version.hip is None  # NVIDIA-only backend
+
+
+def test_public_entry_opt_in_selects_triton_and_reports_provenance():
+    # The explicit opt-in is unchanged: the semantic path must hand out the
+    # Triton class itself (device identity is the instance type, not just
+    # `.is_cuda`, which the CPU-build-then-copy default also has) and report
+    # that backend in the provenance.
+    from rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule import (
+        H3SigmaScheduleCudaOp,
+    )
+    from rl_engine.runtime.registry import kernel_registry
+    from rl_engine.runtime.semantic_registry import OperatorRequirements
+
+    session = kernel_registry.semantic.session()
+    resolution = session.resolve(
+        semantic_op="sigma_schedule_h3",
+        requested_backend="rlkernel.h3_sigma_schedule.triton",
+        target="rollout",
+        requirements=OperatorRequirements(device="cuda", dtype="float32"),
+    )
+    instance = session.instantiate(resolution)
+    assert isinstance(instance, H3SigmaScheduleCudaOp)
+    provenance = session.instance_provenance(resolution, instance)
+    assert provenance.backend_id == "rlkernel.h3_sigma_schedule.triton"
+    assert provenance.concrete_implementation.endswith("H3SigmaScheduleCudaOp")
+    assert torch.version.hip is None  # NVIDIA-only backend
+
+
+@pytest.mark.skipif(
+    torch.cuda.device_count() < 2, reason="multi-GPU device-guard test needs 2 devices"
+)
+def test_target_device_guard_with_mismatched_current_device():
+    from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+    other = "cuda:1" if torch.cuda.current_device() == 0 else "cuda:0"
+    expected = NativeH3SigmaScheduleOp()(25, shift=12.0)
+    with torch.cuda.device(0 if other == "cuda:1" else 1):
+        # Current device deliberately differs from the requested target.
+        schedule = _cuda_op()(25, shift=12.0, device=other)
+
+    assert schedule.sigmas.device == torch.device(other)
+    assert _int32_bits(schedule.sigmas.cpu()) == _int32_bits(expected.sigmas)
+    assert _int32_bits(schedule.timesteps.cpu()) == _int32_bits(expected.timesteps)
diff --git a/tests/reference/minimax_h3/__init__.py b/tests/reference/minimax_h3/__init__.py
new file mode 100644
index 000000000..86cf4c9da
--- /dev/null
+++ b/tests/reference/minimax_h3/__init__.py
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
diff --git a/tests/reference/minimax_h3/h3_sigma_schedule_upstream_fixture.json b/tests/reference/minimax_h3/h3_sigma_schedule_upstream_fixture.json
new file mode 100644
index 000000000..e4a5ba76a
--- /dev/null
+++ b/tests/reference/minimax_h3/h3_sigma_schedule_upstream_fixture.json
@@ -0,0 +1,201 @@
+{
+  "upstream": {
+    "url": "https://github.com/huggingface/diffusers/blob/f53d552/src/diffusers/schedulers/scheduling_minimax_h3.py",
+    "commit": "f53d552036a0d1bd5570782a39cd40cfabf112bc",
+    "blob_sha1": "ca69ae6a2f6aae5bb68498216316a71eb07c1f7b",
+    "fetch_note": "fetched 2026-10-12 via the api.github.com contents endpoint; the blob matched at commit f53d552 and at main at fetch time",
+    "class": "MiniMaxH3Scheduler",
+    "method": "set_timesteps",
+    "execution": "the method body is AST-extracted and executed as-is against a namespace shim; no formula is transcribed",
+    "torch": "2.14.1",
+    "device": "cpu",
+    "dtype": "float32"
+  },
+  "generator": "make_upstream_fixture.py --upstream-file <src> --out <this file>",
+  "cases": [
+    {
+      "num_inference_steps": 2,
+      "shift": 3.0,
+      "sigmas_count": 2,
+      "sigmas_bits": [
+        "3f800000",
+        "00000000"
+      ],
+      "timesteps_count": 1,
+      "timesteps_bits": [
+        "00000000"
+      ],
+      "num_model_evals": 1
+    },
+    {
+      "num_inference_steps": 2,
+      "shift": 12.0,
+      "sigmas_count": 2,
+      "sigmas_bits": [
+        "3f800000",
+        "00000000"
+      ],
+      "timesteps_count": 1,
+      "timesteps_bits": [
+        "00000000"
+      ],
+      "num_model_evals": 1
+    },
+    {
+      "num_inference_steps": 4,
+      "shift": 3.0,
+      "sigmas_count": 4,
+      "sigmas_bits": [
+        "3f800000",
+        "3f5b6db6",
+        "3f199999",
+        "00000000"
+      ],
+      "timesteps_count": 3,
+      "timesteps_bits": [
+        "00000000",
+        "3e124928",
+        "3eccccce"
+      ],
+      "num_model_evals": 3
+    },
+    {
+      "num_inference_steps": 4,
+      "shift": 12.0,
+      "sigmas_count": 4,
+      "sigmas_bits": [
+        "3f800000",
+        "3f75c28f",
+        "3f5b6db6",
+        "00000000"
+      ],
+      "timesteps_count": 3,
+      "timesteps_bits": [
+        "00000000",
+        "3d23d710",
+        "3e124928"
+      ],
+      "num_model_evals": 3
+    },
+    {
+      "num_inference_steps": 25,
+      "shift": 3.0,
+      "sigmas_count": 25,
+      "sigmas_bits": [
+        "3f800000",
+        "3f7c57c6",
+        "3f787878",
+        "3f745d17",
+        "3f700001",
+        "3f6b5ad6",
+        "3f666666",
+        "3f611a7d",
+        "3f5b6db6",
+        "3f555555",
+        "3f4ec4ed",
+        "3f47ae14",
+        "3f400000",
+        "3f37a6f4",
+        "3f2e8ba3",
+        "3f249249",
+        "3f199999",
+        "3f0d7944",
+        "3f000000",
+        "3ee1e1e1",
+        "3ec00000",
+        "3e99999a",
+        "3e5b6db7",
+        "3dec4ec4",
+        "00000000"
+      ],
+      "timesteps_count": 24,
+      "timesteps_bits": [
+        "00000000",
+        "3c6a0e80",
+        "3cf0f100",
+        "3d3a2e90",
+        "3d7ffff0",
+        "3da52950",
+        "3dccccd0",
+        "3df72c18",
+        "3e124928",
+        "3e2aaaac",
+        "3e44ec4c",
+        "3e6147b0",
+        "3e800000",
+        "3e90b218",
+        "3ea2e8ba",
+        "3eb6db6e",
+        "3eccccce",
+        "3ee50d78",
+        "3f000000",
+        "3f0f0f10",
+        "3f200000",
+        "3f333333",
+        "3f492492",
+        "3f627628"
+      ],
+      "num_model_evals": 24
+    },
+    {
+      "num_inference_steps": 25,
+      "shift": 12.0,
+      "sigmas_count": 25,
+      "sigmas_bits": [
+        "3f800000",
+        "3f7f1369",
+        "3f7e133f",
+        "3f7cfcfd",
+        "3f7bcda5",
+        "3f7a81a5",
+        "3f7914c2",
+        "3f7781d3",
+        "3f75c28f",
+        "3f73cf3d",
+        "3f719e34",
+        "3f6f2341",
+        "3f6c4ec5",
+        "3f690c5b",
+        "3f6540f4",
+        "3f60c7ce",
+        "3f5b6db6",
+        "3f54e931",
+        "3f4ccccd",
+        "3f426e2d",
+        "3f34b4b4",
+        "3f21af28",
+        "3f0590b2",
+        "3eaf8af8",
+        "00000000"
+      ],
+      "timesteps_count": 24,
+      "timesteps_bits": [
+        "00000000",
+        "3b6c9700",
+        "3bf66080",
+        "3c40c0c0",
+        "3c864b60",
+        "3cafcb60",
+        "3cdd67c0",
+        "3d07e2d0",
+        "3d23d710",
+        "3d430c30",
+        "3d661cc0",
+        "3d86e5f8",
+        "3d9d89d8",
+        "3db79d28",
+        "3dd5f860",
+        "3df9c190",
+        "3e124928",
+        "3e2c5b3c",
+        "3e4ccccc",
+        "3e76474c",
+        "3e969698",
+        "3ebca1b0",
+        "3ef4de9c",
+        "3f283a84"
+      ],
+      "num_model_evals": 24
+    }
+  ]
+}
diff --git a/tests/reference/minimax_h3/make_upstream_fixture.py b/tests/reference/minimax_h3/make_upstream_fixture.py
new file mode 100644
index 000000000..0dcb5d2a7
--- /dev/null
+++ b/tests/reference/minimax_h3/make_upstream_fixture.py
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""Regenerate the pinned-upstream fixture for ``test_h3_sigma_schedule``.
+
+Executes the ORIGINAL ``MiniMaxH3Scheduler.set_timesteps`` extracted from the
+upstream diffusers source file — no formula is transcribed by hand. The
+method's AST node is compiled and run against a namespace shim that supplies
+the scheduler attributes it touches, so the construction arithmetic (linspace,
+exponential shift, ``unique_consecutive``, timestep conversion) is upstream's
+own code.
+
+The upstream file's git blob sha must equal ``UPSTREAM_BLOB_SHA`` below, so
+this script cannot silently regenerate the fixture from a different revision.
+
+Usage::
+
+    python make_upstream_fixture.py \
+        --upstream-file <scheduling_minimax_h3.py> \
+        --out h3_sigma_schedule_upstream_fixture.json
+"""
+
+from __future__ import annotations
+
+import argparse
+import ast
+import copy
+import hashlib
+import json
+import types
+
+import torch
+
+UPSTREAM_URL = (
+    "https://github.com/huggingface/diffusers/blob/f53d552/src/diffusers/schedulers/"
+    "scheduling_minimax_h3.py"
+)
+UPSTREAM_COMMIT = "f53d552036a0d1bd5570782a39cd40cfabf112bc"
+UPSTREAM_BLOB_SHA = "ca69ae6a2f6aae5bb68498216316a71eb07c1f7b"
+UPSTREAM_FETCH_NOTE = (
+    "fetched 2026-10-12 via the api.github.com contents endpoint; the blob "
+    "matched at commit f53d552 and at main at fetch time"
+)
+
+# RFC #420 fingerprint matrix: video shift 12.0, audio shift 3.0.
+CASES = [
+    (2, 3.0),
+    (2, 12.0),
+    (4, 3.0),
+    (4, 12.0),
+    (25, 3.0),
+    (25, 12.0),
+]
+
+
+def _git_blob_sha(data: bytes) -> str:
+    header = b"blob %d\x00" % len(data)
+    return hashlib.sha1(header + data).hexdigest()
+
+
+def _extract_set_timesteps(source: str) -> ast.FunctionDef:
+    """Return the ``set_timesteps`` FunctionDef of ``MiniMaxH3Scheduler``."""
+    for node in ast.parse(source).body:
+        if isinstance(node, ast.ClassDef) and node.name == "MiniMaxH3Scheduler":
+            for item in node.body:
+                if isinstance(item, ast.FunctionDef) and item.name == "set_timesteps":
+                    return item
+    raise SystemExit("MiniMaxH3Scheduler.set_timesteps not found in upstream source")
+
+
+def _run_upstream_set_timesteps(
+    func: ast.FunctionDef, num_inference_steps: int, shift: float
+) -> tuple[torch.Tensor, torch.Tensor]:
+    """Execute the extracted upstream method once against a shim instance."""
+    module = ast.Module(body=[copy.deepcopy(func)], type_ignores=[])
+    code = compile(module, "<upstream set_timesteps>", "exec")
+    namespace: dict = {"torch": torch}
+    exec(code, namespace)  # the point is to run upstream's own code
+
+    scheduler = types.SimpleNamespace(
+        num_inference_steps=None,
+        sigmas=None,
+        timesteps=None,
+        _shift=float(shift),
+        _step_index=None,
+        _begin_index=None,
+    )
+    namespace["set_timesteps"](scheduler, num_inference_steps=num_inference_steps, device=None)
+    return scheduler.sigmas, scheduler.timesteps
+
+
+def _bits(tensor: torch.Tensor) -> list[str]:
+    values = tensor.detach().cpu().contiguous().view(torch.int32).tolist()
+    return [f"{value & 0xFFFFFFFF:08x}" for value in values]
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser(description=__doc__)
+    parser.add_argument("--upstream-file", required=True)
+    parser.add_argument("--out", required=True)
+    args = parser.parse_args()
+
+    with open(args.upstream_file, "rb") as handle:
+        data = handle.read()
+    blob_sha = _git_blob_sha(data)
+    if blob_sha != UPSTREAM_BLOB_SHA:
+        raise SystemExit(
+            f"upstream file blob sha {blob_sha} != pinned {UPSTREAM_BLOB_SHA}; "
+            "refusing to regenerate the fixture from an unknown revision"
+        )
+
+    func = _extract_set_timesteps(data.decode("utf-8"))
+    cases = []
+    for num_inference_steps, shift in CASES:
+        sigmas, timesteps = _run_upstream_set_timesteps(func, num_inference_steps, shift)
+        cases.append(
+            {
+                "num_inference_steps": num_inference_steps,
+                "shift": shift,
+                "sigmas_count": int(sigmas.numel()),
+                "sigmas_bits": _bits(sigmas),
+                "timesteps_count": int(timesteps.numel()),
+                "timesteps_bits": _bits(timesteps),
+                "num_model_evals": int(timesteps.numel()),
+            }
+        )
+
+    fixture = {
+        "upstream": {
+            "url": UPSTREAM_URL,
+            "commit": UPSTREAM_COMMIT,
+            "blob_sha1": UPSTREAM_BLOB_SHA,
+            "fetch_note": UPSTREAM_FETCH_NOTE,
+            "class": "MiniMaxH3Scheduler",
+            "method": "set_timesteps",
+            "execution": (
+                "the method body is AST-extracted and executed as-is against a "
+                "namespace shim; no formula is transcribed"
+            ),
+            "torch": torch.__version__,
+            "device": "cpu",
+            "dtype": "float32",
+        },
+        "generator": "make_upstream_fixture.py --upstream-file <src> --out <this file>",
+        "cases": cases,
+    }
+    with open(args.out, "w", encoding="utf-8") as handle:
+        json.dump(fixture, handle, indent=2)
+        handle.write("\n")
+    print(f"wrote {args.out} with {len(cases)} cases")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/tests/reference/minimax_h3/test_h3_sigma_schedule.py b/tests/reference/minimax_h3/test_h3_sigma_schedule.py
new file mode 100644
index 000000000..4ac2af4a2
--- /dev/null
+++ b/tests/reference/minimax_h3/test_h3_sigma_schedule.py
@@ -0,0 +1,185 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""Focused tests for the MiniMax-H3 sigma grid reference (RFC #420).
+
+Covers only the four-step construction pinned by
+``MiniMaxH3Scheduler.set_timesteps`` (diffusers ``scheduling_minimax_h3.py``,
+lines 148-168): ``linspace(1, 0, N)`` in fp32 -> exponential shift ->
+``unique_consecutive`` -> ``timesteps = 1 - sigmas[:-1]``.
+
+The primary oracle is ``h3_sigma_schedule_upstream_fixture.json``: fp32 bit
+patterns produced by actually executing the upstream method (AST-extracted
+and run as-is, see ``make_upstream_fixture.py``) from the source file with
+git blob sha ``ca69ae6a2f6aae5bb68498216316a71eb07c1f7b`` (diffusers commit
+``f53d552``, the only revision that touched the file). That check needs
+no network, no installed diffusers, and never skips.
+"""
+
+from __future__ import annotations
+
+import json
+import pathlib
+
+import pytest
+import torch
+
+from rl_engine.reference.minimax_h3.sigma_schedule import NativeH3SigmaScheduleOp
+
+_OP = NativeH3SigmaScheduleOp()
+
+# RFC #420 fingerprint shifts: video 12.0, audio 3.0 (H12 — one grid per
+# modality; grids must never be shared implicitly).
+_CASES = [
+    (2, 12.0),
+    (2, 3.0),
+    (8, 12.0),
+    (8, 3.0),
+    (25, 12.0),
+    (25, 3.0),
+    (50, 12.0),
+    (50, 3.0),
+    (1000, 12.0),
+    (1000, 3.0),
+]
+
+
+_FIXTURE_PATH = pathlib.Path(__file__).parent / "h3_sigma_schedule_upstream_fixture.json"
+_UPSTREAM_BLOB_SHA = "ca69ae6a2f6aae5bb68498216316a71eb07c1f7b"
+_EXPECTED_CASES = {(2, 3.0), (2, 12.0), (4, 3.0), (4, 12.0), (25, 3.0), (25, 12.0)}
+
+
+def _int32_bits(tensor: torch.Tensor) -> list[int]:
+    return tensor.detach().contiguous().view(torch.int32).tolist()
+
+
+def _bits_to_int32(bits: list[str]) -> torch.Tensor:
+    return torch.tensor([int(value, 16) for value in bits], dtype=torch.int32)
+
+
+def test_matches_pinned_upstream_set_timesteps_bitwise():
+    # Non-skippable: the expected fp32 bit patterns were generated by actually
+    # executing the upstream set_timesteps method from the pinned source (see
+    # make_upstream_fixture.py) — no network, no diffusers install, and no
+    # hand-copied formula are involved.
+    fixture = json.loads(_FIXTURE_PATH.read_text(encoding="utf-8"))
+    assert fixture["upstream"]["blob_sha1"] == _UPSTREAM_BLOB_SHA
+
+    actual_cases = [(case["num_inference_steps"], case["shift"]) for case in fixture["cases"]]
+    assert len(actual_cases) == len(set(actual_cases)), "duplicate fixture cases"
+    assert set(actual_cases) == _EXPECTED_CASES
+
+    for case in fixture["cases"]:
+        schedule = _OP(case["num_inference_steps"], shift=case["shift"])
+
+        assert schedule.sigmas.dtype is torch.float32
+        assert tuple(schedule.sigmas.shape) == (case["sigmas_count"],)
+        assert _int32_bits(schedule.sigmas) == _bits_to_int32(case["sigmas_bits"]).tolist()
+
+        assert schedule.timesteps.dtype is torch.float32
+        assert tuple(schedule.timesteps.shape) == (case["timesteps_count"],)
+        expected_timesteps = _bits_to_int32(case["timesteps_bits"]).tolist()
+        assert _int32_bits(schedule.timesteps) == expected_timesteps
+
+        assert schedule.num_model_evals == case["num_model_evals"]
+
+
+@pytest.mark.parametrize(("num_inference_steps", "shift"), _CASES)
+def test_grid_invariants(num_inference_steps, shift):
+    schedule = _OP(num_inference_steps, shift=shift)
+    sigmas, timesteps = schedule.sigmas, schedule.timesteps
+
+    assert sigmas.dtype is torch.float32
+    assert timesteps.dtype is torch.float32
+    assert sigmas.numel() <= num_inference_steps
+    # First sigma is exactly 1.0 for the released shifts (3.0, 12.0); the
+    # shift maps the terminal 0.0 to exactly 0.0.
+    assert sigmas[0].item() == 1.0
+    assert sigmas[-1].item() == 0.0
+    assert bool((sigmas[1:] < sigmas[:-1]).all())
+    assert bool((timesteps[1:] > timesteps[:-1]).all())
+    assert timesteps[0].item() == 0.0
+    # Call count follows the deduplicated grid, not the requested N.
+    assert schedule.num_model_evals == sigmas.numel() - 1 == timesteps.numel()
+
+
+def test_unique_consecutive_collapses_shift_created_collisions():
+    # shift=12 compresses spacing near sigma=1 enough that a dense grid holds
+    # fp32 collisions: N=1e6 collapses ~4% of rows in a few ms. The base
+    # linspace itself stays duplicate-free at this density, so the collapse is
+    # attributable to the shift step, as the upstream docstring claims.
+    n = 1_000_000
+    base = torch.linspace(1.0, 0.0, n, dtype=torch.float32)
+    assert torch.unique_consecutive(base).numel() == n  # precondition
+
+    schedule = _OP(n, shift=12.0)
+
+    assert schedule.sigmas.numel() < n
+    assert schedule.num_model_evals == schedule.sigmas.numel() - 1
+    assert schedule.timesteps.numel() == schedule.num_model_evals
+    assert bool((schedule.sigmas[1:] < schedule.sigmas[:-1]).all())
+    assert schedule.sigmas[-1].item() == 0.0
+
+
+def test_video_and_audio_shifts_give_distinct_grids():
+    video = _OP(25, shift=12.0)
+    audio = _OP(25, shift=3.0)
+
+    assert not torch.equal(video.sigmas, audio.sigmas)
+    assert not torch.equal(video.timesteps, audio.timesteps)
+
+
+@pytest.mark.parametrize("num_inference_steps", [1, 0, -4])
+def test_rejects_num_inference_steps_below_two(num_inference_steps):
+    with pytest.raises(ValueError, match="num_inference_steps"):
+        _OP(num_inference_steps, shift=12.0)
+
+
+@pytest.mark.parametrize("shift", [0.0, -1.5])
+def test_rejects_non_positive_shift(shift):
+    with pytest.raises(ValueError, match="positive"):
+        _OP(8, shift=shift)
+
+
+def test_device_argument_preserves_bytes_and_dtype():
+    local = _OP(25, shift=12.0)
+    moved = _OP(25, shift=12.0, device="cpu")
+
+    assert _int32_bits(moved.sigmas) == _int32_bits(local.sigmas)
+    assert _int32_bits(moved.timesteps) == _int32_bits(local.timesteps)
+    assert moved.sigmas.dtype is torch.float32
+    assert moved.sigmas.device.type == "cpu"
+
+
+def test_builds_on_cpu_under_non_cpu_default_device():
+    # torch.linspace without an explicit device follows the ambient default
+    # device, so the reference must pin "cpu" itself. Under a meta default the
+    # unfixed implementation raised NotImplementedError inside
+    # unique_consecutive (no meta kernel); on real accelerators it would
+    # silently build the grid off-CPU.
+    with torch.device("meta"):
+        schedule = _OP(25, shift=12.0)
+
+    assert schedule.sigmas.device.type == "cpu"
+    assert schedule.timesteps.device.type == "cpu"
+    reference = _OP(25, shift=12.0)
+    assert _int32_bits(schedule.sigmas) == _int32_bits(reference.sigmas)
+    assert _int32_bits(schedule.timesteps) == _int32_bits(reference.timesteps)
+
+
+def test_matches_installed_diffusers_scheduler_when_available():
+    diffusers = pytest.importorskip("diffusers")
+    scheduler_cls = getattr(diffusers, "MiniMaxH3Scheduler", None)
+    if scheduler_cls is None:
+        pytest.skip("installed diffusers has no MiniMaxH3Scheduler")
+
+    for num_inference_steps, shift in ((25, 12.0), (50, 3.0)):
+        scheduler = scheduler_cls(shift=shift)
+        scheduler.set_timesteps(num_inference_steps, device="cpu")
+        schedule = _OP(num_inference_steps, shift=shift)
+
+        assert torch.equal(scheduler.sigmas, schedule.sigmas)
+        assert torch.equal(scheduler.timesteps, schedule.timesteps)
+        # Upstream stores len(timesteps) as num_inference_steps, i.e. the
+        # model-evaluation count.
+        assert scheduler.num_inference_steps == schedule.num_model_evals
diff --git a/tests/runtime/test_h3_sigma_schedule_dispatch.py b/tests/runtime/test_h3_sigma_schedule_dispatch.py
new file mode 100644
index 000000000..fd05062d1
--- /dev/null
+++ b/tests/runtime/test_h3_sigma_schedule_dispatch.py
@@ -0,0 +1,190 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2026 RL-Kernel Contributors
+
+"""Registry and semantic-entry tests for ``h3_sigma_schedule`` (RFC #420).
+
+Covers the public selection paths on any machine: legacy ``get_op`` serving
+the PyTorch reference on every platform (the Triton backend is opt-in only and
+never a legacy candidate), semantic descriptor registration, session resolve /
+instantiate / provenance for both backends, and the CPU-pinned scalar-rounding
+helper. The device-path parity (the default reference path producing the same
+bytes as the directly constructed Triton class) is asserted on hardware in
+tests/backends/cuda/test_h3_sigma_schedule_cuda.py.
+"""
+
+from __future__ import annotations
+
+import importlib
+
+import pytest
+import torch
+
+from rl_engine.runtime.registry import KernelRegistry, OpBackend, kernel_registry
+from rl_engine.runtime.semantic_registry import (
+    OperatorInstantiationError,
+    OperatorRequirements,
+    OperatorResolutionError,
+)
+
+_BACKEND_MODULE = importlib.import_module(
+    "rl_engine.backends.cuda.model_specific.minimax_h3.sigma_schedule"
+)
+_REFERENCE_PATH = "rl_engine.reference.minimax_h3.sigma_schedule.NativeH3SigmaScheduleOp"
+
+
+def test_get_op_cpu_selects_reference_and_builds_pinned_grid():
+    op = kernel_registry.get_op("sigma_schedule_h3", device="cpu")
+    assert f"{type(op).__module__}.{type(op).__name__}" == _REFERENCE_PATH
+
+    schedule = op(4, shift=3.0, device="cpu")
+    assert [f"{v:08x}" for v in schedule.sigmas.view(torch.int32).tolist()] == [
+        "3f800000",
+        "3f5b6db6",
+        "3f199999",
+        "00000000",
+    ]
+    assert schedule.num_model_evals == 3
+
+
+def test_get_op_cuda_defaults_to_reference_regardless_of_triton(monkeypatch):
+    # Default backend change per review (2026-10-25): the CUDA candidate list
+    # carries only the PyTorch reference (CPU build + host-to-device copy) —
+    # the device-side Triton build measured 2.5-3.2x slower at typical H3
+    # sizes and nothing requires on-device construction. Triton is opt-in via
+    # the semantic path or direct construction, so whether it is importable
+    # must not influence the legacy selection in either direction.
+    for triton_importable in (False, True):
+        monkeypatch.setattr(_BACKEND_MODULE, "_TRITON_AVAILABLE", triton_importable)
+        registry = KernelRegistry()
+
+        assert registry._priority_map["cuda"]["sigma_schedule_h3"] == [
+            OpBackend.PYTORCH_H3_SIGMA_SCHEDULE
+        ]
+        op = registry.get_op("sigma_schedule_h3", device="cuda")
+        assert f"{type(op).__module__}.{type(op).__name__}" == _REFERENCE_PATH
+
+
+def test_cuda_backend_construction_fails_loudly_without_triton(monkeypatch):
+    monkeypatch.setattr(_BACKEND_MODULE, "_TRITON_AVAILABLE", False)
+
+    with pytest.raises(ImportError, match="triton is required"):
+        _BACKEND_MODULE.H3SigmaScheduleCudaOp()
+
+
+def test_shift_scalars_pinned_to_cpu_under_meta_default():
+    # Old behavior: the factory calls followed the ambient default device and
+    # failed under a meta default (RuntimeError on .item()).
+    with torch.device("meta"):
+        shift_f32, shift_m1_f32 = _BACKEND_MODULE._shift_scalars(3.0)
+    assert shift_f32 == 3.0
+    assert shift_m1_f32 == 2.0
+
+
+def test_shift_scalars_keep_fp64_subtract_then_round_semantics():
+    # Pinned artifact of the upstream scalar handling: (1e-10 - 1.0) is
+    # subtracted in fp64 first and only then rounded to fp32, landing on
+    # exactly -1.0 (this feeds the division-by-zero +inf first sigma).
+    _, shift_m1_f32 = _BACKEND_MODULE._shift_scalars(1e-10)
+    assert shift_m1_f32 == -1.0
+
+
+def test_cuda_backend_construction_rejected_on_hip_build(monkeypatch):
+    # The kernels emit inline PTX div.rn.f32 and cannot run on AMD: a HIP
+    # build must be rejected AT CONSTRUCTION (long before any Triton
+    # compilation), with the same ImportError contract the registry's
+    # candidate loop already handles for missing Triton. Simulated without
+    # any AMD hardware by monkeypatching torch.version.hip.
+    monkeypatch.setattr(torch.version, "hip", "6.2")
+
+    with pytest.raises(ImportError, match="NVIDIA-only.*inline.*PTX"):
+        _BACKEND_MODULE.H3SigmaScheduleCudaOp()
+
+
+def test_get_op_on_hip_build_serves_reference(monkeypatch):
+    # Same simulation, end to end: ``device="cuda"`` resolves to the rocm
+    # platform, whose list has always been reference-only, and the NVIDIA-only
+    # Triton class is not a legacy candidate anywhere — the caller gets the
+    # reference with no error and nothing silently misattributed, exactly as
+    # on an NVIDIA build.
+    monkeypatch.setattr(torch.version, "hip", "6.2")
+    registry = KernelRegistry()
+
+    op = registry.get_op("sigma_schedule_h3", device="cuda")
+
+    assert f"{type(op).__module__}.{type(op).__name__}" == _REFERENCE_PATH
+
+
+def test_triton_backend_is_not_a_legacy_candidate_on_any_platform():
+    # Opt-in only: the Triton class is reachable through the semantic path
+    # (requested_backend="rlkernel.h3_sigma_schedule.triton") or direct
+    # construction, never through a legacy ``get_op`` candidate list.
+    registry = KernelRegistry()
+
+    for platform in ("cuda", "rocm", "musa", "cpu", "npu"):
+        candidates = registry._priority_map[platform]["sigma_schedule_h3"]
+        assert candidates == [OpBackend.PYTORCH_H3_SIGMA_SCHEDULE], platform
+
+
+def test_semantic_descriptors_declared_truthfully():
+    reference = kernel_registry.semantic.backend_descriptor(
+        "sigma_schedule_h3", "rlkernel.h3_sigma_schedule.reference"
+    )
+    triton = kernel_registry.semantic.backend_descriptor(
+        "sigma_schedule_h3", "rlkernel.h3_sigma_schedule.triton"
+    )
+    assert reference is not None and triton is not None
+    assert reference.supported_devices == frozenset({"cpu", "cuda", "rocm"})
+    # NVIDIA-only backend (inline PTX); HIP/ROCm stays on the reference.
+    assert triton.supported_devices == frozenset({"cuda"})
+    assert reference.supported_dtypes == triton.supported_dtypes == frozenset({"float32"})
+    assert reference.implementation_reference == _REFERENCE_PATH
+
+
+def test_semantic_reference_path_resolves_instantiates_and_reports_provenance():
+    session = kernel_registry.semantic.session()
+    resolution = session.resolve(
+        semantic_op="sigma_schedule_h3",
+        requested_backend="rlkernel.h3_sigma_schedule.reference",
+        target="rollout",
+        requirements=OperatorRequirements(device="cpu", dtype="float32"),
+    )
+    assert resolution.trace.status == "resolved"
+    assert resolution.trace.concrete_backend == "rlkernel.h3_sigma_schedule.reference"
+    assert resolution.trace.implementation_reference == _REFERENCE_PATH
+
+    instance = session.instantiate(resolution)
+    assert type(instance).__name__ == "NativeH3SigmaScheduleOp"
+    assert instance(4, shift=3.0, device="cpu").num_model_evals == 3
+
+    provenance = session.instance_provenance(resolution, instance)
+    assert provenance.semantic_op == "sigma_schedule_h3"
+    assert provenance.backend_id == "rlkernel.h3_sigma_schedule.reference"
+    assert provenance.concrete_implementation == _REFERENCE_PATH
+    assert provenance.factory_reference == _REFERENCE_PATH
+
+
+def test_semantic_triton_backend_fails_explicitly_when_unavailable(monkeypatch):
+    # Resolution matches the declared capability (device "cuda"); the missing
+    # runtime dependency then surfaces as an explicit instantiation error —
+    # never as a silent swap to another backend's arithmetic.
+    monkeypatch.setattr(_BACKEND_MODULE, "_TRITON_AVAILABLE", False)
+    session = kernel_registry.semantic.session()
+    resolution = session.resolve(
+        semantic_op="sigma_schedule_h3",
+        requested_backend="rlkernel.h3_sigma_schedule.triton",
+        target="rollout",
+        requirements=OperatorRequirements(device="cuda", dtype="float32"),
+    )
+    with pytest.raises(OperatorInstantiationError, match="triton is required"):
+        session.instantiate(resolution)
+
+
+def test_semantic_unknown_backend_is_rejected():
+    session = kernel_registry.semantic.session()
+    with pytest.raises(OperatorResolutionError):
+        session.resolve(
+            semantic_op="sigma_schedule_h3",
+            requested_backend="rlkernel.h3_sigma_schedule.does-not-exist",
+            target="rollout",
+            requirements=OperatorRequirements(device="cpu", dtype="float32"),
+        )