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Commit f187a34

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skrllskrll
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Fix merge botches
1 parent 20e7b27 commit f187a34

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5 files changed

+272
-42
lines changed

5 files changed

+272
-42
lines changed

‎sys/external/gpl2/dts/dist/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,83 @@
2626
clock-frequency = <25000000>;
2727
};
2828

29+
&emmc {
30+
bus-width = <4>;
31+
no-sdio;
32+
no-sd;
33+
non-removable;
34+
wp-inverted;
35+
status = "okay";
36+
};
37+
38+
&i2c1 {
39+
status = "okay";
40+
41+
mcu: syscon@17 {
42+
compatible = "sophgo,sg2042-hwmon-mcu";
43+
reg = <0x17>;
44+
#thermal-sensor-cells = <1>;
45+
};
46+
};
47+
48+
&sd {
49+
bus-width = <4>;
50+
no-sdio;
51+
no-mmc;
52+
wp-inverted;
53+
status = "okay";
54+
};
55+
2956
&uart0 {
3057
status = "okay";
3158
};
59+
60+
/ {
61+
thermal-zones {
62+
soc-thermal {
63+
polling-delay-passive = <1000>;
64+
polling-delay = <1000>;
65+
thermal-sensors = <&mcu 0>;
66+
67+
trips {
68+
soc_active1: soc-active1 {
69+
temperature = <30000>;
70+
hysteresis = <8000>;
71+
type = "active";
72+
};
73+
74+
soc_active2: soc-active2 {
75+
temperature = <58000>;
76+
hysteresis = <12000>;
77+
type = "active";
78+
};
79+
80+
soc_active3: soc-active3 {
81+
temperature = <70000>;
82+
hysteresis = <10000>;
83+
type = "active";
84+
};
85+
86+
soc_hot: soc-hot {
87+
temperature = <80000>;
88+
hysteresis = <5000>;
89+
type = "hot";
90+
};
91+
};
92+
};
93+
94+
board-thermal {
95+
polling-delay-passive = <1000>;
96+
polling-delay = <1000>;
97+
thermal-sensors = <&mcu 1>;
98+
99+
trips {
100+
board_active: board-active {
101+
temperature = <75000>;
102+
hysteresis = <8000>;
103+
type = "active";
104+
};
105+
};
106+
};
107+
};
108+
};

‎sys/external/gpl2/dts/dist/arch/riscv/boot/dts/sophgo/sg2042.dtsi‎

Lines changed: 147 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,127 @@
4444
compatible = "simple-bus";
4545
#address-cells = <2>;
4646
#size-cells = <2>;
47+
interrupt-parent = <&intc>;
4748
ranges;
4849

50+
i2c0: i2c@7030005000 {
51+
compatible = "snps,designware-i2c";
52+
reg = <0x70 0x30005000 0x0 0x1000>;
53+
#address-cells = <1>;
54+
#size-cells = <0>;
55+
clocks = <&clkgen GATE_CLK_APB_I2C>;
56+
clock-names = "ref";
57+
clock-frequency = <100000>;
58+
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
59+
resets = <&rstgen RST_I2C0>;
60+
status = "disabled";
61+
};
62+
63+
i2c1: i2c@7030006000 {
64+
compatible = "snps,designware-i2c";
65+
reg = <0x70 0x30006000 0x0 0x1000>;
66+
#address-cells = <1>;
67+
#size-cells = <0>;
68+
clocks = <&clkgen GATE_CLK_APB_I2C>;
69+
clock-names = "ref";
70+
clock-frequency = <100000>;
71+
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
72+
resets = <&rstgen RST_I2C1>;
73+
status = "disabled";
74+
};
75+
76+
i2c2: i2c@7030007000 {
77+
compatible = "snps,designware-i2c";
78+
reg = <0x70 0x30007000 0x0 0x1000>;
79+
#address-cells = <1>;
80+
#size-cells = <0>;
81+
clocks = <&clkgen GATE_CLK_APB_I2C>;
82+
clock-names = "ref";
83+
clock-frequency = <100000>;
84+
interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
85+
resets = <&rstgen RST_I2C2>;
86+
status = "disabled";
87+
};
88+
89+
i2c3: i2c@7030008000 {
90+
compatible = "snps,designware-i2c";
91+
reg = <0x70 0x30008000 0x0 0x1000>;
92+
#address-cells = <1>;
93+
#size-cells = <0>;
94+
clocks = <&clkgen GATE_CLK_APB_I2C>;
95+
clock-names = "ref";
96+
clock-frequency = <100000>;
97+
interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
98+
resets = <&rstgen RST_I2C3>;
99+
status = "disabled";
100+
};
101+
102+
gpio0: gpio@7030009000 {
103+
compatible = "snps,dw-apb-gpio";
104+
reg = <0x70 0x30009000 0x0 0x400>;
105+
#address-cells = <1>;
106+
#size-cells = <0>;
107+
clocks = <&clkgen GATE_CLK_APB_GPIO>,
108+
<&clkgen GATE_CLK_GPIO_DB>;
109+
clock-names = "bus", "db";
110+
111+
port0a: gpio-controller@0 {
112+
compatible = "snps,dw-apb-gpio-port";
113+
gpio-controller;
114+
#gpio-cells = <2>;
115+
ngpios = <32>;
116+
reg = <0>;
117+
interrupt-controller;
118+
#interrupt-cells = <2>;
119+
interrupt-parent = <&intc>;
120+
interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
121+
};
122+
};
123+
124+
gpio1: gpio@703000a000 {
125+
compatible = "snps,dw-apb-gpio";
126+
reg = <0x70 0x3000a000 0x0 0x400>;
127+
#address-cells = <1>;
128+
#size-cells = <0>;
129+
clocks = <&clkgen GATE_CLK_APB_GPIO>,
130+
<&clkgen GATE_CLK_GPIO_DB>;
131+
clock-names = "bus", "db";
132+
133+
port1a: gpio-controller@0 {
134+
compatible = "snps,dw-apb-gpio-port";
135+
gpio-controller;
136+
#gpio-cells = <2>;
137+
ngpios = <32>;
138+
reg = <0>;
139+
interrupt-controller;
140+
#interrupt-cells = <2>;
141+
interrupt-parent = <&intc>;
142+
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
143+
};
144+
};
145+
146+
gpio2: gpio@703000b000 {
147+
compatible = "snps,dw-apb-gpio";
148+
reg = <0x70 0x3000b000 0x0 0x400>;
149+
#address-cells = <1>;
150+
#size-cells = <0>;
151+
clocks = <&clkgen GATE_CLK_APB_GPIO>,
152+
<&clkgen GATE_CLK_GPIO_DB>;
153+
clock-names = "bus", "db";
154+
155+
port2a: gpio-controller@0 {
156+
compatible = "snps,dw-apb-gpio-port";
157+
gpio-controller;
158+
#gpio-cells = <2>;
159+
ngpios = <32>;
160+
reg = <0>;
161+
interrupt-controller;
162+
#interrupt-cells = <2>;
163+
interrupt-parent = <&intc>;
164+
interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
165+
};
166+
};
167+
49168
pllclk: clock-controller@70300100c0 {
50169
compatible = "sophgo,sg2042-pll";
51170
reg = <0x70 0x300100c0 0x0 0x40>;
@@ -388,7 +507,6 @@
388507
uart0: serial@7040000000 {
389508
compatible = "snps,dw-apb-uart";
390509
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
391-
interrupt-parent = <&intc>;
392510
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
393511
clock-frequency = <500000000>;
394512
clocks = <&clkgen GATE_CLK_UART_500M>,
@@ -399,5 +517,33 @@
399517
resets = <&rstgen RST_UART0>;
400518
status = "disabled";
401519
};
520+
521+
emmc: mmc@704002a000 {
522+
compatible = "sophgo,sg2042-dwcmshc";
523+
reg = <0x70 0x4002a000 0x0 0x1000>;
524+
interrupt-parent = <&intc>;
525+
interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
526+
clocks = <&clkgen GATE_CLK_EMMC_100M>,
527+
<&clkgen GATE_CLK_AXI_EMMC>,
528+
<&clkgen GATE_CLK_100K_EMMC>;
529+
clock-names = "core",
530+
"bus",
531+
"timer";
532+
status = "disabled";
533+
};
534+
535+
sd: mmc@704002b000 {
536+
compatible = "sophgo,sg2042-dwcmshc";
537+
reg = <0x70 0x4002b000 0x0 0x1000>;
538+
interrupt-parent = <&intc>;
539+
interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
540+
clocks = <&clkgen GATE_CLK_SD_100M>,
541+
<&clkgen GATE_CLK_AXI_SD>,
542+
<&clkgen GATE_CLK_100K_SD>;
543+
clock-names = "core",
544+
"bus",
545+
"timer";
546+
status = "disabled";
547+
};
402548
};
403549
};

‎sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-common.dtsi‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,6 @@
128128
assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
129129
<&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
130130
assigned-clock-rates = <49500000>, <198000000>;
131-
status = "okay";
132131

133132
ports {
134133
#address-cells = <1>;
@@ -151,7 +150,6 @@
151150
&csi2rx {
152151
assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
153152
assigned-clock-rates = <297000000>;
154-
status = "okay";
155153

156154
ports {
157155
#address-cells = <1>;

‎sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
/* $NetBSD: jh7110-pinfunc.h,v 1.2 2024/08/12 10:55:55 skrll Exp $ */
1+
/* $NetBSD: jh7110-pinfunc.h,v 1.3 2026/01/18 18:51:31 skrll Exp $ */
22

33
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
44
/*
@@ -91,7 +91,7 @@
9191
#define GPOUT_SYS_SDIO1_DATA1 59
9292
#define GPOUT_SYS_SDIO1_DATA2 60
9393
#define GPOUT_SYS_SDIO1_DATA3 61
94-
#define GPOUT_SYS_SDIO1_DATA4 63
94+
#define GPOUT_SYS_SDIO1_DATA4 62
9595
#define GPOUT_SYS_SDIO1_DATA5 63
9696
#define GPOUT_SYS_SDIO1_DATA6 64
9797
#define GPOUT_SYS_SDIO1_DATA7 65

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