1- /* $NetBSD: sunxi_mmc.c,v 1.49 2025/12/10 22:14:13 mlelstv Exp $ */
1+ /* $NetBSD: sunxi_mmc.c,v 1.50 2026/03/18 06:42:35 skrll Exp $ */
22
33/*-
44 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca>
2929#include "opt_sunximmc.h"
3030
3131#include <sys/cdefs.h>
32- __KERNEL_RCSID (0 , "$NetBSD: sunxi_mmc.c,v 1.49 2025/12/10 22:14:13 mlelstv Exp $" );
32+ __KERNEL_RCSID (0 , "$NetBSD: sunxi_mmc.c,v 1.50 2026/03/18 06:42:35 skrll Exp $" );
3333
3434#include <sys/param.h>
3535#include <sys/bus.h>
@@ -135,6 +135,7 @@ static struct sdmmc_chip_functions sunxi_mmc_chip_functions = {
135135
136136struct sunxi_mmc_config {
137137 u_int idma_xferlen ;
138+ u_int idma_shift ;
138139 u_int flags ;
139140#define SUNXI_MMC_FLAG_CALIB_REG 0x01
140141#define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02
@@ -245,6 +246,16 @@ static const struct sunxi_mmc_config sun9i_a80_mmc_config = {
245246 .flags = 0 ,
246247};
247248
249+ static const struct sunxi_mmc_config sun20i_d1_mmc_config = {
250+ .idma_xferlen = 0x2000 ,
251+ .idma_shift = 2 ,
252+ .dma_ftrglevel = 0x20070008 ,
253+ .delays = NULL ,
254+ .flags = SUNXI_MMC_FLAG_CALIB_REG |
255+ SUNXI_MMC_FLAG_NEW_TIMINGS |
256+ SUNXI_MMC_FLAG_MASK_DATA0 ,
257+ };
258+
248259static const struct sunxi_mmc_config sun50i_a64_mmc_config = {
249260 .idma_xferlen = 0x10000 ,
250261 .dma_ftrglevel = 0x20070008 ,
@@ -290,6 +301,8 @@ static const struct device_compatible_entry compat_data[] = {
290301 .data = & sun8i_a83t_emmc_config },
291302 { .compat = "allwinner,sun9i-a80-mmc" ,
292303 .data = & sun9i_a80_mmc_config },
304+ { .compat = "allwinner,sun20i-d1-mmc" ,
305+ .data = & sun20i_d1_mmc_config },
293306 { .compat = "allwinner,sun50i-a64-mmc" ,
294307 .data = & sun50i_a64_mmc_config },
295308 { .compat = "allwinner,sun50i-a64-emmc" ,
@@ -1036,7 +1049,7 @@ sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd)
10361049 break ;
10371050 len = uimin (sc -> sc_config -> idma_xferlen , resid );
10381051 dma [desc ].dma_buf_size = htole32 (len );
1039- dma [desc ].dma_buf_addr = htole32 (paddr + off );
1052+ dma [desc ].dma_buf_addr = htole32 (( paddr + off ) >> sc -> sc_config -> idma_shift );
10401053 dma [desc ].dma_config = htole32 (SUNXI_MMC_IDMA_CONFIG_CH |
10411054 SUNXI_MMC_IDMA_CONFIG_OWN );
10421055 cmd -> c_resid -= len ;
@@ -1052,9 +1065,9 @@ sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd)
10521065 } else {
10531066 dma [desc ].dma_config |=
10541067 htole32 (SUNXI_MMC_IDMA_CONFIG_DIC );
1055- dma [desc ].dma_next = htole32 (
1068+ dma [desc ].dma_next = htole32 ((
10561069 desc_paddr + ((desc + 1 ) *
1057- sizeof (struct sunxi_mmc_idma_descriptor )));
1070+ sizeof (struct sunxi_mmc_idma_descriptor ))) >> sc -> sc_config -> idma_shift ) ;
10581071 }
10591072 ++ desc ;
10601073 }
@@ -1070,7 +1083,7 @@ sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd)
10701083 bus_dmamap_sync (sc -> sc_dmat , sc -> sc_idma_map , 0 ,
10711084 sc -> sc_idma_size , BUS_DMASYNC_PREWRITE );
10721085
1073- MMC_WRITE (sc , SUNXI_MMC_DLBA , desc_paddr );
1086+ MMC_WRITE (sc , SUNXI_MMC_DLBA , desc_paddr >> sc -> sc_config -> idma_shift );
10741087 MMC_WRITE (sc , SUNXI_MMC_FTRGLEVEL , sc -> sc_config -> dma_ftrglevel );
10751088
10761089 val = MMC_READ (sc , SUNXI_MMC_GCTRL );
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