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1 | | -/* $NetBSD: dwc_eqos.c,v 1.42 2025/10/04 04:44:20 thorpej Exp $ */ |
| 1 | +/* $NetBSD: dwc_eqos.c,v 1.43 2025/10/15 02:26:48 thorpej Exp $ */ |
2 | 2 |
|
3 | 3 | /*- |
4 | 4 | * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca> |
|
36 | 36 | */ |
37 | 37 |
|
38 | 38 | #include <sys/cdefs.h> |
39 | | -__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.42 2025/10/04 04:44:20 thorpej Exp $"); |
| 39 | +__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.43 2025/10/15 02:26:48 thorpej Exp $"); |
40 | 40 |
|
41 | 41 | #include <sys/param.h> |
42 | 42 | #include <sys/bus.h> |
@@ -1322,31 +1322,36 @@ eqos_get_dma_pbl(struct eqos_softc *sc) |
1322 | 1322 | static void |
1323 | 1323 | eqos_axi_configure(struct eqos_softc *sc) |
1324 | 1324 | { |
1325 | | - prop_dictionary_t prop = device_properties(sc->sc_dev); |
1326 | 1325 | uint32_t val; |
1327 | 1326 | u_int uival; |
1328 | | - bool bval; |
1329 | 1327 |
|
1330 | 1328 | val = RD4(sc, GMAC_DMA_SYSBUS_MODE); |
1331 | | - if (prop_dictionary_get_bool(prop, "snps,mixed-burst", &bval) && bval) { |
| 1329 | + |
| 1330 | + /* XXX are MB and FB mutually-exclusive? XXX */ |
| 1331 | + if (device_getprop_bool(sc->sc_dev, "snps,mixed-burst")) { |
1332 | 1332 | val |= GMAC_DMA_SYSBUS_MODE_MB; |
1333 | 1333 | } |
1334 | | - if (prop_dictionary_get_bool(prop, "snps,fixed-burst", &bval) && bval) { |
| 1334 | + if (device_getprop_bool(sc->sc_dev, "snps,fixed-burst")) { |
1335 | 1335 | val |= GMAC_DMA_SYSBUS_MODE_FB; |
1336 | 1336 | } |
1337 | | - if (prop_dictionary_get_uint(prop, "snps,wr_osr_lmt", &uival)) { |
| 1337 | + if (device_getprop_uint(sc->sc_dev, "snps,wr_osr_lmt", &uival)) { |
1338 | 1338 | val &= ~GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; |
1339 | | - val |= uival << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT; |
| 1339 | + val |= (uival << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) & |
| 1340 | + GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; |
1340 | 1341 | } |
1341 | | - if (prop_dictionary_get_uint(prop, "snps,rd_osr_lmt", &uival)) { |
| 1342 | + if (device_getprop_uint(sc->sc_dev, "snps,rd_osr_lmt", &uival)) { |
1342 | 1343 | val &= ~GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; |
1343 | | - val |= uival << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT; |
| 1344 | + val |= (uival << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) & |
| 1345 | + GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; |
1344 | 1346 | } |
1345 | 1347 |
|
1346 | 1348 | if (!EQOS_HW_FEATURE_ADDR64_32BIT(sc)) { |
1347 | 1349 | val |= GMAC_DMA_SYSBUS_MODE_EAME; |
1348 | 1350 | } |
1349 | 1351 |
|
| 1352 | + /* XXX snps,kbbe XXX */ |
| 1353 | + /* XXX snps,blen XXX */ |
| 1354 | + |
1350 | 1355 | /* XXX */ |
1351 | 1356 | val |= GMAC_DMA_SYSBUS_MODE_BLEN16; |
1352 | 1357 | val |= GMAC_DMA_SYSBUS_MODE_BLEN8; |
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