Pull up following revision(s) (requested by skrll in ticket #38):

	sys/arch/riscv/riscv/bus_dma.c: revision 1.11

risc-v: Adjust barriers issued in bus_dmamap_sync for the coherent case.
PR/59653

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.
These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

Net change:
op                      old                     new
---------------------   ----------------------  --------------
PREREAD                 none                    fence rw,ow
PREWRITE                fence iorw,iorw         fence rw,ow
PREREAD|PREWRITE        fence iorw,iorw         fence w,ow
POSTREAD                fence iorw,iorw         fence ir,r
POSTWRITE               none                    none
POSTREAD|POSTWRITE      fence iorw,iorw         fence ir,r

Author: MartinHusemann

sys/arch/riscv/riscv/bus_dma.c

@@ -1,4 +1,4 @@
-/*	$NetBSD: bus_dma.c,v 1.10 2025/03/02 01:23:11 riastradh Exp $	*/
+/*	$NetBSD: bus_dma.c,v 1.10.2.1 2025/10/01 16:37:05 martin Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
 #define _RISCV_NEED_BUS_DMA_BOUNCE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.10 2025/03/02 01:23:11 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.10.2.1 2025/10/01 16:37:05 martin Exp $");
 
 #include <sys/param.h>
 
@@ -1166,38 +1166,77 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
 		}
 	}
 
-	/* Skip cache frobbing if mapping was COHERENT */
+	/*
+	 * Provide appropriate memory barriers, and skip cache frobbing
+	 * if mapping is COHERENT.
+	 *
+	 * The case of PREREAD is as follows:
+	 *
+	 * 1. loads and stores before DMA buffer may be allocated for the
+	 *    purpose
+	 * 2. bus_dmamap_sync(BUS_DMASYNC_PREREAD)
+	 * 3. store to register or DMA descriptor to trigger DMA
+	 *
+	 * The load/store-before-store ordering is ensured by fence rw, ow.
+	 *
+	 * The case of PREWRITE is as follows:
+	 *
+	 * 1. stores to DMA buffer. loads can happen later as the buffer is
+	 *    not changed by the device.
+	 * 2. bus_dmamap_sync(BUS_DMASYNC_PREWRITE)
+	 * 3. store to register or DMA descriptor to trigger DMA
+	 *
+	 * The store-before-store ordering is ensured by fence w,ow.
+	 *
+	 * The case of POSTREAD is as follows:
+	 *
+	 * 1. load from register or DMA descriptor notifying DMA completion
+	 * 2. bus_dmamap_sync(BUS_DMASYNC_POSTREAD)
+	 * 3. loads from DMA buffer to use data, and stores to reuse buffer
+	 *
+	 * The stores in (3) will not be speculated and, therefore, don't need
+	 * specific handling. The load-before-load ordering is provided by
+	 * fence ir,r.
+	 *
+	 * The case of POSTWRITE is as follows:
+	 *
+	 * 1. load from register or DMA descriptor notifying DMA completion
+	 * 2. bus_dmamap_sync(BUS_DMASYNC_POSTWRITE)
+	 * 3. loads and stores to reuse buffer
+	 *
+	 * The stores in (3) will not be speculated, and the load can happen
+	 * at any time as the DMA buffer is not changed by the device so no
+	 * barrier is required.
+	 */
 	if ((map->_dm_flags & _BUS_DMAMAP_COHERENT)) {
 		switch (ops) {
 		case BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE:
+			asm volatile ("fence rw,ow" ::: "memory");
 			STAT_INCR(sync_coherent_prereadwrite);
 			break;
 
 		case BUS_DMASYNC_PREREAD:
+			asm volatile ("fence rw,ow" ::: "memory");
 			STAT_INCR(sync_coherent_preread);
 			break;
 
 		case BUS_DMASYNC_PREWRITE:
+			asm volatile ("fence w,ow" ::: "memory");
 			STAT_INCR(sync_coherent_prewrite);
 			break;
 
 		case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
+			asm volatile ("fence ir,r" ::: "memory");
 			STAT_INCR(sync_coherent_postreadwrite);
 			break;
 
 		case BUS_DMASYNC_POSTREAD:
+			asm volatile ("fence ir,r" ::: "memory");
 			STAT_INCR(sync_coherent_postread);
 			break;
 
 		/* BUS_DMASYNC_POSTWRITE was aleady handled as a fastpath */
 		}
-		/*
-		 * Drain the write buffer of DMA operators.
-		 * 1) when cpu->device (prewrite)
-		 * 2) when device->cpu (postread)
-		 */
-		if ((pre_ops & BUS_DMASYNC_PREWRITE) || (post_ops & BUS_DMASYNC_POSTREAD))
-			asm volatile ("fence iorw,iorw" ::: "memory");
 
 		/*
 		 * Only thing left to do for COHERENT mapping is copy from bounce