Wr Enable Implemented and Passed through Stages - Unwated Reg update after Branch error mitigated

Author: MKhizerButt

03_RV32I-pipeline/src/main/scala/EXbarrier.scala

@@ -38,23 +38,28 @@ class EXBarrier extends Module {
     val inAluResult = Input(UInt(32.W))
     val inRD = Input(UInt(5.W))
     val inXcptInvalid = Input(Bool())
+    val inWrEn = Input(Bool())
 
     val outAluResult = Output(UInt(32.W))
     val outRD = Output(UInt(5.W))
     val outXcptInvalid = Output(Bool())
+    val outWrEn = Output(Bool())
   })
 
   val aluResult = RegInit(0.U(32.W))
   val rd = RegInit(0.U(5.W))
   val xcptInvalid = RegInit(false.B)
+  val wrEnReg = RegInit(false.B)
 
   aluResult := io.inAluResult
   rd := io.inRD
   xcptInvalid := io.inXcptInvalid
+  wrEnReg := io.inWrEn
 
   io.outAluResult := aluResult
   io.outRD := rd
   io.outXcptInvalid := xcptInvalid
+  io.outWrEn := wrEnReg
 }
 //ToDo: Add your implementation according to the specification above here 
 

03_RV32I-pipeline/src/main/scala/FUnit.scala

@@ -14,8 +14,8 @@ class ForwardingUnit extends Module{
     val idBarRegFileReq_A = Input(UInt(5.W)) // RegisterRs
     val idBarRegFileReq_B = Input(UInt(5.W)) // RegisterRt
 
-    val wbStageWrEn = Input(Bool())
-    //     val memBarWrEn  = Input(Bool()) // Does not exist currently, write enable is only sent via wb stage to the regFile
+    val exBarWrEn = Input(Bool())   // NEW: Is the instruction in MEM writing?
+    val wbStageWrEn = Input(Bool()) // Is the instruction in WB writing?    //     val memBarWrEn  = Input(Bool()) // Does not exist currently, write enable is only sent via wb stage to the regFile
     // no mem module in task 3, hence there were no load instr (or store), write enable was always "set"
     // Also no branche or jump as of now
 
@@ -27,7 +27,7 @@ class ForwardingUnit extends Module{
   io.regSelect_Rt := 0.U
 
   // EX Hazard
-  when(io.idBarRegFileReq_A === io.exBarRd && io.idBarRegFileReq_A =/= 0.U) {
+  when(io.idBarRegFileReq_A === io.exBarRd && io.idBarRegFileReq_A =/= 0.U && io.exBarWrEn) {
     io.regSelect_Rs := 1.U
   }
   // MEM Hazard 
@@ -37,7 +37,7 @@ class ForwardingUnit extends Module{
     }
   }
 
-  when(io.idBarRegFileReq_B === io.exBarRd && io.idBarRegFileReq_B =/= 0.U) {
+  when(io.idBarRegFileReq_B === io.exBarRd && io.idBarRegFileReq_B =/= 0.U && io.exBarWrEn) {
     io.regSelect_Rt := 1.U
   }
   .elsewhen(io.idBarRegFileReq_B === io.memBarRd && io.idBarRegFileReq_B =/= 0.U && io.wbStageWrEn) {

03_RV32I-pipeline/src/main/scala/IDbarrier.scala

@@ -48,6 +48,7 @@ class IDBarrier extends Module {
     val inOperandB = Input(UInt(32.W))
     val inXcptInvalid = Input(Bool())
     val inTargetPC = Input(UInt(32.W))
+    val inWrEn = Input(Bool())
 
     val outUOP = Output(UInt(7.W))
     val outRD = Output(UInt(5.W))
@@ -57,6 +58,7 @@ class IDBarrier extends Module {
     val outOperandB = Output(UInt(32.W))
     val outXcptInvalid = Output(Bool())
     val outTargetPC = Output(UInt(32.W))
+    val outWrEn = Output(Bool())
   })
 
   val uopReg = RegInit(0.U(7.W)) // Assuming 0 is NOP
@@ -67,7 +69,8 @@ class IDBarrier extends Module {
   val operandB = RegInit(0.U(32.W))
   val xcptInvalid = RegInit(false.B)
   val targetPC = RegInit(0.U(32.W))
-
+  val wrEnReg = RegInit(false.B) 
+  
 
   uopReg := io.inUOP
   operandA := io.inOperandA
@@ -77,6 +80,8 @@ class IDBarrier extends Module {
   rs2 := io.inrs2
   xcptInvalid := io.inXcptInvalid
   targetPC := io.inTargetPC // Pass target 
+  wrEnReg := io.inWrEn
+
 
   io.outUOP := uopReg
   io.outOperandA := operandA
@@ -86,7 +91,8 @@ class IDBarrier extends Module {
   io.outrs2 := rs2
   io.outXcptInvalid := xcptInvalid
   io.outTargetPC := targetPC
-
+  io.outWrEn := wrEnReg
+  
 //RegNext means: "Create a register, feed this input into it, initialize it to this default value, and connect it to this output"
 //   io.outUOP         := RegNext(io.inUOP, 0.U)
 //   io.outRD          := RegNext(io.inRD, 0.U)

03_RV32I-pipeline/src/main/scala/IDstage.scala

@@ -63,6 +63,7 @@ class ID extends Module {
 
     val pcSel = Output(Bool()) // Input for PC selection signal from EX stage (for branch/jump)
     val targetPC = Output(UInt(32.W)) // Output for target PC to IF stage for branch/jump
+    val wr_en = Output(Bool()) //
   })
 
   val opcode = io.inst(6, 0) // Extract opcode from instruction
@@ -76,7 +77,6 @@ class ID extends Module {
   val immB = Cat(io.inst(31), io.inst(7), io.inst(30, 25), io.inst(11, 8), 0.U(1.W)).asSInt.pad(32).asUInt // Extract immediate for B-type instructions, Bit 0 as it is a multiples of 2 bytes
 
   io.uop := NOP.asUInt // Default to NOP
-  io.rd_idx := rd // Output destination register index
   io.XcptInvalid := true.B // Default to invalid instruction, will be cleared for valid instructions
 
   io.regFileReq_A.addr := rs1 // Set read address for rs1
@@ -93,6 +93,13 @@ class ID extends Module {
                  Mux(opcode === "b1100111".U, ((io.regFileResp_A.data + immI).asUInt & "hfffffffe".U(32.W)), 
                  Mux(opcode === "b1100011".U, (io.pc + immB), 0.U(32.W)))) // Calculate target PC for JALR and B-type instructions, will be used in IF stage for PC update
 
+  // Branches (B-type) and Stores (S-type) do NOT write to registers!
+  val isBranch = (opcode === "b1100011".U)
+  // val isStore  = (opcode === "b0100011".U) // Not Implemented right now
+  
+  io.wr_en := !(isBranch) // || isStore) 
+  io.rd_idx := rd // Output destination register index
+
   when(opcode === "b0110011".U) { // R-type instructions
     switch(funct3) {
       is("b000".U) { // ADD/SUB

03_RV32I-pipeline/src/main/scala/MEMbarrier.scala

@@ -38,22 +38,27 @@ class MEMBarrier extends Module {
     val inAluResult = Input(UInt(32.W))
     val inRD = Input(UInt(5.W))
     val inXcptInvalid = Input(Bool())
+    val inWrEn = Input(Bool())
 
     val outAluResult = Output(UInt(32.W))
     val outRD = Output(UInt(5.W))
     val outXcptInvalid = Output(Bool())
+    val outWrEn = Output(Bool())
   })
 
   val aluResult = RegInit(0.U(32.W))
   val rd = RegInit(0.U(5.W))
   val xcptInvalid = RegInit(false.B)
-    
+  val wrEnReg = RegInit(false.B)
+
   aluResult := io.inAluResult
   rd := io.inRD
   xcptInvalid := io.inXcptInvalid
+  wrEnReg := io.inWrEn
 
   io.outAluResult := aluResult
   io.outRD := rd
   io.outXcptInvalid := xcptInvalid
+  io.outWrEn := wrEnReg
 }
 //ToDo: Add your implementation according to the specification above here 

03_RV32I-pipeline/src/main/scala/WBstage.scala

@@ -43,14 +43,15 @@ class WB extends Module {
   val io = IO(new Bundle {
     val aluResult = Input(UInt(32.W))
     val rd = Input(UInt(5.W))
+    val inWrEn = Input(Bool())
 
     val regFileReq = Output(new RegFileWriteReq) // Write request to register file
     val check_res = Output(UInt(32.W)) // Output for verification and debugging
   })
 
   io.regFileReq.addr := io.rd // Set write address to rd
   io.regFileReq.data := io.aluResult // Forward aluResult to register file write port
-  io.regFileReq.wr_en := true.B // Enable write for all R-type and I-type instructions (to be refined with instruction decoding)
+  io.regFileReq.wr_en := io.inWrEn // Enable write for all R-type and I-type instructions, set in the ID Stage (False only in Branches and Store {not implemented yet})
 
   io.check_res := io.aluResult // Output result for verification and debugging
 }

03_RV32I-pipeline/src/main/scala/core.scala

@@ -127,7 +127,9 @@ class PipelinedRV32Icore (BinaryFile: String) extends Module {
   idBarrier.io.inOperandB := idStage.io.operandB
   idBarrier.io.inXcptInvalid := idStage.io.XcptInvalid
   idBarrier.io.inTargetPC := idStage.io.targetPC 
-
+  // CRITICAL: If a branch is taken, force wr_en to false so the flushed Ghost instruction doesn't write!
+  idBarrier.io.inWrEn := Mux(exStage.io.isBranch, false.B, idStage.io.wr_en)
+  
   // Connect ID barrier to EX stage
   exStage.io.uop := idBarrier.io.outUOP
   exStage.io.rd := idBarrier.io.outRD
@@ -139,15 +141,18 @@ class PipelinedRV32Icore (BinaryFile: String) extends Module {
   exBarrier.io.inAluResult := exStage.io.aluResult
   exBarrier.io.inRD := exStage.io.outRD
   exBarrier.io.inXcptInvalid := exStage.io.xcptInvalid
+  exBarrier.io.inWrEn := idBarrier.io.outWrEn // Pass write enable from ID barrier to EX barrier (critical for correct forwarding behavior and to prevent hazards from writing instructions)
 
   // Connect EX barrier to MEM Barrier 
   memBarrier.io.inAluResult := exBarrier.io.outAluResult
   memBarrier.io.inRD := exBarrier.io.outRD
   memBarrier.io.inXcptInvalid := exBarrier.io.outXcptInvalid
+  memBarrier.io.inWrEn := exBarrier.io.outWrEn // Pass write enable from EX barrier to MEM barrier (critical for correct forwarding behavior and to prevent hazards from writing instructions)
 
   // Connect MEM barrier to WB Stage
   wbStage.io.aluResult := memBarrier.io.outAluResult
   wbStage.io.rd := memBarrier.io.outRD
+  wbStage.io.inWrEn := memBarrier.io.outWrEn // Pass write enable from MEM barrier to WB stage (critical for correct forwarding behavior and to prevent hazards from writing instructions)
 
   // Connect WB stage & MEM barrier to WB barrier
   wbBarrier.io.inCheckRes := wbStage.io.check_res
@@ -163,5 +168,5 @@ class PipelinedRV32Icore (BinaryFile: String) extends Module {
   fUnit.io.idBarRegFileReq_A := idBarrier.io.outrs1
   fUnit.io.idBarRegFileReq_B := idBarrier.io.outrs2
   fUnit.io.wbStageWrEn := wbStage.io.regFileReq.wr_en
-
+  fUnit.io.exBarWrEn := exBarrier.io.outWrEn // Check if the instruction in EX stage is writing (coming out of EX Barrier)
 }