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Update, fix and reorganize hostmot2 PktUART to support V3.
1 parent df7a294 commit 86974fe

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Lines changed: 1108 additions & 843 deletions

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‎src/hal/drivers/mesa-hostmot2/hostmot2-serial.h‎

Lines changed: 197 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
//
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// Copyright (C) 2007-2008 Sebastian Kuzminsky
3+
// Copyright (C) 2015 B.Stultiens
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
@@ -21,25 +22,209 @@
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2223
#include <rtapi.h>
2324

25+
/*
26+
* http://freeby.mesanet.com/regmap
27+
* The PktUARTxMode register is used for setting and checking the
28+
* PktUARTx's operation mode, timing and status:
29+
* Bit 21 RO FrameBuffer Has Data
30+
* Bits 20..16 RO Frames to send (input and output ports can overlap with an FPGA)
31+
* Bit 20 WO Scale inter-frame delay by 4 (0=x1, 1=x4) (V3+)
32+
* Bit 19 WO Number of stopbits (0=one, 1=two) (V3+)
33+
* Bit 18 WO Odd Parity (1=odd, 0=even)
34+
* Bit 17 WO Parity enable
35+
* Bits 15..8 RW InterFrame delay in bit times
36+
* Bit 7 RO Transmit Logic active, not an error
37+
* Bit 6 RW Drive Enable bit (enables external RS-422/485 Driver when set)
38+
* Bit 5 RW Drive enable Auto (Automatic external drive enable)
39+
* Bit 4 RO SCFIFO Error
40+
* Bits 3..0 RW Drive enable delay (delay from asserting drive enable
41+
* to start of data transmit). In CLock Low periods
42+
*/
43+
#define HM2_PKTUART_TXMODE_MASK ((1u << 22) - 1)
44+
#define HM2_PKTUART_TXMODE_HASDATA_BIT 21 // RO
45+
#define HM2_PKTUART_TXMODE_IFSCALE_BIT 20 // WO (v3+)
46+
#define HM2_PKTUART_TXMODE_STOPBITS2_BIT 19 // WO (v3+)
47+
#define HM2_PKTUART_TXMODE_PARITYODD_BIT 18 // WO
48+
#define HM2_PKTUART_TXMODE_PARITYEN_BIT 17 // WO
49+
#define HM2_PKTUART_TXMODE_NFRAMES_BIT 16 // RO (16..20)
50+
#define HM2_PKTUART_TXMODE_INTERFRAMEDLY_BIT 8 // RW ( 8..15)
51+
#define HM2_PKTUART_TXMODE_TXBUSY_BIT 7 // RO
52+
#define HM2_PKTUART_TXMODE_DRIVEEN_BIT 6 // RW
53+
#define HM2_PKTUART_TXMODE_DRIVEAUTO_BIT 5 // RW
54+
#define HM2_PKTUART_TXMODE_ERRORSCFIFO_BIT 4 // RO
55+
#define HM2_PKTUART_TXMODE_DRIVEENDLY_BIT 0 // RW ( 0..3)
56+
#define HM2_PKTUART_TXMODE_HASDATA (1u << HM2_PKTUART_TXMODE_HASDATA_BIT)
57+
#define HM2_PKTUART_TXMODE_IFSCALE (1u << HM2_PKTUART_TXMODE_IFSCALE_BIT)
58+
#define HM2_PKTUART_TXMODE_STOPBITS2 (1u << HM2_PKTUART_TXMODE_STOPBITS2_BIT)
59+
#define HM2_PKTUART_TXMODE_NFRAMES_MASK (0x1fu << HM2_PKTUART_TXMODE_NFRAMES_BIT)
60+
#define HM2_PKTUART_TXMODE_NFRAMES(x) (((x) & 0x1fu) << HM2_PKTUART_TXMODE_NFRAMES_BIT)
61+
#define HM2_PKTUART_TXMODE_NFRAMES_VAL(x) (((x) >> HM2_PKTUART_TXMODE_NFRAMES_BIT) & 0x1fu)
62+
#define HM2_PKTUART_TXMODE_PARITYEN (1u << HM2_PKTUART_TXMODE_PARITYEN_BIT)
63+
#define HM2_PKTUART_TXMODE_PARITYODD (1u << HM2_PKTUART_TXMODE_PARITYODD_BIT)
64+
#define HM2_PKTUART_TXMODE_INTERFRAMEDLY_MASK (0xffu << HM2_PKTUART_TXMODE_INTERFRAMEDLY_BIT)
65+
#define HM2_PKTUART_TXMODE_INTERFRAMEDLY(x) (((x) & 0xffu) << HM2_PKTUART_TXMODE_INTERFRAMEDLY_BIT)
66+
#define HM2_PKTUART_TXMODE_INTERFRAMEDLY_VAL(x) (((x) >> HM2_PKTUART_TXMODE_INTERFRAMEDLY_BIT) & 0xffu)
67+
#define HM2_PKTUART_TXMODE_TXBUSY (1u << HM2_PKTUART_TXMODE_TXBUSY_BIT)
68+
#define HM2_PKTUART_TXMODE_DRIVEEN (1u << HM2_PKTUART_TXMODE_DRIVEEN_BIT)
69+
#define HM2_PKTUART_TXMODE_DRIVEAUTO (1u << HM2_PKTUART_TXMODE_DRIVEAUTO_BIT)
70+
#define HM2_PKTUART_TXMODE_ERRORSCFIFO (1u << HM2_PKTUART_TXMODE_ERRORSCFIFO_BIT)
71+
#define HM2_PKTUART_TXMODE_DRIVEENDLY_MASK (0xfu << HM2_PKTUART_TXMODE_DRIVEENDLY_BIT)
72+
#define HM2_PKTUART_TXMODE_DRIVEENDLY(x) (((x) & 0xfu) << HM2_PKTUART_TXMODE_DRIVEENDLY_BIT)
73+
#define HM2_PKTUART_TXMODE_DRIVEENDLY_VAL(x) (((x) >> HM2_PKTUART_TXMODE_DRIVEENDLY_BIT) & 0xfu)
74+
75+
/*
76+
* http://freeby.mesanet.com/regmap
77+
* The PktUARTrMode register is used for setting and checking the PktUARTr's
78+
* operation mode, timing, and status
79+
* Bit 30 RO BadPop Error (read data FIFO with no data) RO
80+
* Bits 29..22 RW RX data digital filter (in ClockLow periods)
81+
* Should be set to 1/2 bit time
82+
* (or max=255 if it cannot be set long enough)
83+
* Bit 21 RO FrameBuffer has data
84+
* Bit 20 WO Scale inter-frame delay by 4 (0=x1, 1=x4) (V3+)
85+
* Bit 19 WO Number of stopbits (0=one, 1=two) (V3+)
86+
* Bit 18 WO Odd Parity WO (1=odd, 0=even)
87+
* Bit 17 WO Parity enable WO
88+
* Bits 20..16 RW Frames received
89+
* Bits 15..8 RW InterFrame delay in bit times
90+
* Bit 7 RO Receive Logic active, not an error
91+
* Bit 6 RO RXMask
92+
* Bit 5 RW Parity error
93+
* Bit 4 RW RCFIFO Error
94+
* Bit 3 RW RXEnable (must be set to receive packets)
95+
* Bit 2 RW RXMask Enable (enables input data masking when transmitting)
96+
* Bit 1 RW Overrun error (no stop bit when expected) (sticky)
97+
* Bit 0 RW False Start bit error (sticky)
98+
*/
99+
#define HM2_PKTUART_RXMODE_MASK ((1u << 31) - 1)
100+
#define HM2_PKTUART_RXMODE_ERRORBADPOP_BIT 30 // RO
101+
#define HM2_PKTUART_RXMODE_RXFILTER_BIT 22 // RW (22..29)
102+
#define HM2_PKTUART_RXMODE_HASDATA_BIT 21 // RO
103+
#define HM2_PKTUART_RXMODE_IFSCALE_BIT 20 // WO (v3+)
104+
#define HM2_PKTUART_RXMODE_STOPBITS2_BIT 19 // WO (v3+)
105+
#define HM2_PKTUART_RXMODE_PARITYODD_BIT 18 // WO
106+
#define HM2_PKTUART_RXMODE_PARITYEN_BIT 17 // WO
107+
#define HM2_PKTUART_RXMODE_NFRAMES_BIT 16 // RO (16..20)
108+
#define HM2_PKTUART_RXMODE_INTERFRAMEDLY_BIT 8 // RW ( 8..15)
109+
#define HM2_PKTUART_RXMODE_RXBUSY_BIT 7 // RO
110+
#define HM2_PKTUART_RXMODE_RXMASK_BIT 6 // RO
111+
#define HM2_PKTUART_RXMODE_ERRORPARITY_BIT 5 // RW
112+
#define HM2_PKTUART_RXMODE_ERRORRCFIFO_BIT 4 // RW
113+
#define HM2_PKTUART_RXMODE_RXEN_BIT 3 // RW
114+
#define HM2_PKTUART_RXMODE_RXMASKEN_BIT 2 // RW
115+
#define HM2_PKTUART_RXMODE_ERROROVERRUN_BIT 1 // RW
116+
#define HM2_PKTUART_RXMODE_ERRORSTARTBIT_BIT 0 // RW
117+
#define HM2_PKTUART_RXMODE_ERRORBADPOP (1u << HM2_PKTUART_RXMODE_ERRORBADPOP_BIT)
118+
#define HM2_PKTUART_RXMODE_RXFILTER_MASK (0xffu << HM2_PKTUART_RXMODE_RXFILTER_BIT)
119+
#define HM2_PKTUART_RXMODE_RXFILTER(x) (((x) & 0xffu) << HM2_PKTUART_RXMODE_RXFILTER_BIT)
120+
#define HM2_PKTUART_RXMODE_RXFILTER_VAL(x) (((x) >> HM2_PKTUART_RXMODE_RXFILTER_BIT) & 0xffu)
121+
#define HM2_PKTUART_RXMODE_HASDATA (1u << HM2_PKTUART_RXMODE_HASDATA_BIT)
122+
#define HM2_PKTUART_RXMODE_IFSCALE (1u << HM2_PKTUART_RXMODE_IFSCALE_BIT)
123+
#define HM2_PKTUART_RXMODE_STOPBITS2 (1u << HM2_PKTUART_RXMODE_STOPBITS2_BIT)
124+
#define HM2_PKTUART_RXMODE_NFRAMES_MASK (0x1fu << HM2_PKTUART_RXMODE_NFRAMES_BIT)
125+
#define HM2_PKTUART_RXMODE_NFRAMES(x) (((x) & 0x1fu) << HM2_PKTUART_RXMODE_NFRAMES_BIT)
126+
#define HM2_PKTUART_RXMODE_NFRAMES_VAL(x) (((x) >> HM2_PKTUART_RXMODE_NFRAMES_BIT) & 0x1fu)
127+
#define HM2_PKTUART_RXMODE_PARITYEN (1u << HM2_PKTUART_RXMODE_PARITYEN_BIT)
128+
#define HM2_PKTUART_RXMODE_PARITYODD (1u << HM2_PKTUART_RXMODE_PARITYODD_BIT)
129+
#define HM2_PKTUART_RXMODE_INTERFRAMEDLY_MASK (0xffu << HM2_PKTUART_RXMODE_INTERFRAMEDLY_BIT)
130+
#define HM2_PKTUART_RXMODE_INTERFRAMEDLY(x) (((x) & 0xffu) << HM2_PKTUART_RXMODE_INTERFRAMEDLY_BIT)
131+
#define HM2_PKTUART_RXMODE_INTERFRAMEDLY_VAL(x) (((x) >> HM2_PKTUART_RXMODE_INTERFRAMEDLY_BIT) & 0xffu)
132+
#define HM2_PKTUART_RXMODE_RXBUSY (1u << HM2_PKTUART_RXMODE_RXBUSY_BIT)
133+
#define HM2_PKTUART_RXMODE_RXMASK (1u << HM2_PKTUART_RXMODE_RXMASK_BIT)
134+
#define HM2_PKTUART_RXMODE_ERRORPARITY (1u << HM2_PKTUART_RXMODE_ERRORPARITY_BIT)
135+
#define HM2_PKTUART_RXMODE_ERRORRCFIFO (1u << HM2_PKTUART_RXMODE_ERRORRCFIFO_BIT)
136+
#define HM2_PKTUART_RXMODE_RXEN (1u << HM2_PKTUART_RXMODE_RXEN_BIT)
137+
#define HM2_PKTUART_RXMODE_RXMASKEN (1u << HM2_PKTUART_RXMODE_RXMASKEN_BIT)
138+
#define HM2_PKTUART_RXMODE_ERROROVERRUN (1u << HM2_PKTUART_RXMODE_ERROROVERRUN_BIT)
139+
#define HM2_PKTUART_RXMODE_ERRORSTARTBIT (1u << HM2_PKTUART_RXMODE_ERRORSTARTBIT_BIT)
140+
141+
/*
142+
* http://freeby.mesanet.com/regmap
143+
* The PktUARTx/PktUARTr mode register has a special data command that clears
144+
* the PktUARTx/PktUARTr Clearing aborts any sends/receives in process, clears
145+
* the data FIFO and clears the send count FIFO. To issue a clear command, you
146+
* write 0x80010000 to the PktUARTx/PktUARTr mode register.
147+
*/
148+
#define HM2_PKTUART_CLEAR 0x80010000
149+
150+
// Receive count register
151+
#define HM2_PKTUART_RCR_MASK 0xff00c3ff
152+
#define HM2_PKTUART_RCR_ICHARBITS_BIT 24 // bits 24..31 Max inter-character bit-times (V3+ only)
153+
#define HM2_PKTUART_RCR_ERROROVERRUN_BIT 15
154+
#define HM2_PKTUART_RCR_ERRORSTARTBIT_BIT 14
155+
#define HM2_PKTUART_RCR_NBYTES_BIT 0 // bits 0..9 Frame size
156+
#define HM2_PKTUART_RCR_ICHARBITS_MASK (0xffu << HM2_PKTUART_RCR_ICHARBITS_BIT)
157+
#define HM2_PKTUART_RCR_ICHARBITS(x) (((x) & 0xffu) << HM2_PKTUART_RCR_ICHARBITS_BIT)
158+
#define HM2_PKTUART_RCR_ICHARBITS_VAL(x) (((x) >> HM2_PKTUART_RCR_ICHARBITS_BIT) & 0xffu)
159+
#define HM2_PKTUART_RCR_ERROROVERRUN (1u << HM2_PKTUART_RCR_ERROROVERRUN_BIT)
160+
#define HM2_PKTUART_RCR_ERRORSTARTBIT (1u << HM2_PKTUART_RCR_ERRORSTARTBIT_BIT)
161+
#define HM2_PKTUART_RCR_NBYTES_MASK (0x3ffu << HM2_PKTUART_RCR_NBYTES_BIT)
162+
#define HM2_PKTUART_RCR_NBYTES(x) (((x) & 0x3ffu) << HM2_PKTUART_RCR_NBYTES_BIT)
163+
#define HM2_PKTUART_RCR_NBYTES_VAL(x) (((x) >> HM2_PKTUART_RCR_NBYTES_BIT) & 0x3ffu)
164+
165+
/* Exported PktUART functions */
24166
RTAPI_BEGIN_DECLS
25167

168+
typedef struct {
169+
rtapi_u32 baudrate; // RX+TX
170+
rtapi_u32 filterrate; // RX only: (set to zero for 2*baudrate)
171+
rtapi_u32 drivedelay; // TX only: delay before transmit ([0..31])
172+
rtapi_u32 ifdelay; // RX+TX: Inter-frame delay in bit times ([0..255] or V3+ [0..1020])
173+
rtapi_u32 flags; // RX+TX: enable flags (see HM2_PKTUART_CONFIG_*)
174+
rtapi_u32 unused[3]; // Future proof, probably
175+
} hm2_pktuart_config_t;
176+
177+
#define HM2_PKTUART_CONFIG_DRIVEEN 0x0001 // TX-only Output driver enable
178+
#define HM2_PKTUART_CONFIG_DRIVEAUTO 0x0002 // TX-only Output drive auto-on on send
179+
#define HM2_PKTUART_CONFIG_RXEN 0x0010 // RX-only Receiver enable
180+
#define HM2_PKTUART_CONFIG_RXMASKEN 0x0020 // RX-only Receiver masked when sending (half-duplex)
181+
#define HM2_PKTUART_CONFIG_PARITYEN 0x0100 // RX+TX Parity enable
182+
#define HM2_PKTUART_CONFIG_PARITYODD 0x0200 // RX+TX Parity Odd (even when unset and parity enabled)
183+
#define HM2_PKTUART_CONFIG_STOPBITS2 0x0400 // RX+TX Set two stopbits (V3+)
184+
#define HM2_PKTUART_CONFIG_FLUSH 0x4000 // RX+TX flag (flush fifo and count regs)
185+
#define HM2_PKTUART_CONFIG_FORCECONFIG 0x8000 // RX+TX Always write the config to the board, even when not changed
186+
187+
// hm2_pktuart_config() replaces previous pktuart serial setup functions
188+
// Changes can now be done without changing the prototype
189+
int hm2_pktuart_config(const char *name, const hm2_pktuart_config_t *rxcfg, const hm2_pktuart_config_t *txcfg, int queue);
190+
191+
// DEPRECATED: hm2_pktuart_setup()
192+
// DEPRECATED: hm2_pktuart_setup_tx()
193+
// DEPRECATED: hm2_pktuart_setup_rx()
194+
// Is replaced by hm2_pktuart_config()
195+
int hm2_pktuart_setup(const char *name, unsigned bitrate, rtapi_s32 tx_mode, rtapi_s32 rx_mode, int txclear, int rxclear) __attribute__((deprecated));
196+
int hm2_pktuart_setup_rx(const char *name, unsigned int bitrate, unsigned int filter_hz, unsigned int parity, int frame_delay, bool rx_enable, bool rx_mask) __attribute__((deprecated));
197+
int hm2_pktuart_setup_tx(const char *name, unsigned int bitrate, unsigned int parity, int frame_delay, bool drive_enable, bool drive_auto, int enable_delay) __attribute__((deprecated));
198+
199+
// Immediate out-of-band reset
200+
void hm2_pktuart_reset(const char *name);
201+
// Reset but with normal queue processing
202+
void hm2_pktuart_queue_reset(const char *name);
203+
204+
int hm2_pktuart_send(const char *name, const unsigned char data[], rtapi_u8 *num_frames, const rtapi_u16 frame_sizes[]);
205+
// The hm2_pkuart_read() function should be declared deprecated because it
206+
// reads directly bypassing the queue_read function.
207+
// Unfortunately, it is still used in hal/components/mesa_pktgyro_test.comp
208+
int hm2_pktuart_read(const char *name, unsigned char data[], rtapi_u8 *num_frames, rtapi_u16 *max_frame_length, rtapi_u16 frame_sizes[]);
209+
int hm2_pktuart_queue_get_frame_sizes(const char *name, rtapi_u32 fsizes[]);
210+
int hm2_pktuart_queue_read_data(const char *name, rtapi_u32 *data, int bytes);
211+
int hm2_pktuart_get_clock(const char *name);
212+
int hm2_pktuart_get_version(const char *name);
213+
rtapi_u32 hm2_pktuart_get_rx_status(const char *name);
214+
rtapi_u32 hm2_pktuart_get_tx_status(const char *name);
215+
RTAPI_END_DECLS
216+
217+
218+
/* Exported UART functions */
219+
RTAPI_BEGIN_DECLS
26220
int hm2_uart_setup(char *name, int bitrate, rtapi_s32 tx_mode, rtapi_s32 rx_mode);
27221
int hm2_uart_send(char *name, unsigned char data[], int count);
28222
int hm2_uart_read(char *name, unsigned char data[]);
223+
RTAPI_END_DECLS
29224

30-
int hm2_pktuart_setup(char *name, int bitrate, rtapi_s32 tx_mode, rtapi_s32 rx_mode, int txclear, int rxclear); // deprecated after v2
31-
int hm2_pktuart_setup_rx(char *name, unsigned int bitrate, unsigned int filter_hz, unsigned int parity, int frame_delay, bool rx_enable, bool rx_mask);
32-
int hm2_pktuart_setup_tx(char *name, unsigned int bitrate, unsigned int parity, int frame_delay, bool drive_enable, bool drive_auto, int enable_delay);
33-
void hm2_pktuart_reset(char *name);
34-
int hm2_pktuart_send(char *name, unsigned char data[], rtapi_u8 *num_frames, rtapi_u16 frame_sizes[]);
35-
int hm2_pktuart_read(char *name, unsigned char data[], rtapi_u8 *num_frames, rtapi_u16 *max_frame_length, rtapi_u16 frame_sizes[]);
36-
int hm2_pktuart_queue_get_frame_sizes(char *name, rtapi_u32 fsizes[]);
37-
int hm2_pktuart_queue_read_data(char *name, rtapi_u32 *data, int bytes);
38-
int hm2_pktuart_get_clock(char *name);
39-
int hm2_pktuart_get_version(char *name);
40-
rtapi_u32 hm2_pktuart_get_rx_status(char *name);
41-
rtapi_u32 hm2_pktuart_get_tx_status(char *name);
42225

226+
/* Exported Buffered SPI functions */
227+
RTAPI_BEGIN_DECLS
43228
int hm2_bspi_setup_chan(char *name, int chan, int cs, int bits, double mhz,
44229
int delay, int cpol, int cpha, int noclear, int noecho,
45230
int samplelate);
@@ -49,7 +234,6 @@ int hm2_bspi_write_chan(char* name, int chan, rtapi_u32 val);
49234
int hm2_allocate_bspi_tram(char* name);
50235
int hm2_tram_add_bspi_frame(char *name, int chan, rtapi_u32 **wbuff, rtapi_u32 **rbuff);
51236
int hm2_bspi_clear_fifo(char * name);
52-
53237
RTAPI_END_DECLS
54238

55239
#endif

‎src/hal/drivers/mesa-hostmot2/hostmot2.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1895,12 +1895,6 @@ void hm2_pktuart_write(hostmot2_t *hm2);
18951895
void hm2_pktuart_force_write(hostmot2_t *hm2); // ??
18961896
void hm2_pktuart_prepare_tram_write(hostmot2_t *hm2, long period); //??
18971897
void hm2_pktuart_process_tram_read(hostmot2_t *hm2, long period); // ??
1898-
int hm2_pktuart_setup(char *name, unsigned int bitrate, rtapi_s32 tx_mode, rtapi_s32 rx_mode, int txclear, int rxclear);
1899-
int hm2_pktuart_setup_rx(char *name, unsigned int bitrate, unsigned int filter_hz, unsigned int parity, int frame_delay, bool rx_enable, bool rx_mask);
1900-
int hm2_pktuart_setup_tx(char *name, unsigned int bitrate, unsigned int parity, int frame_delay, bool drive_enable, bool drive_auto, int enable_delay);
1901-
void hm2_pktuart_reset(char *name);
1902-
int hm2_pktuart_send(char *name, unsigned char data[], rtapi_u8 *num_frames, rtapi_u16 frame_sizes[]);
1903-
int hm2_pktuart_read(char *name, unsigned char data[], rtapi_u8 *num_frames, rtapi_u16 *max_frame_length, rtapi_u16 frame_sizes[]);
19041898

19051899
//
19061900
// hm2dpll functions

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