Merge pull request #257 from tclamb/master

Update additional PSP VFPU instructions

Author: Kingcom

Archs/MIPS/CMipsInstruction.cpp

@@ -31,6 +31,8 @@ int getImmediateBits(MipsImmediateType type)
 		return 5;
 	case MipsImmediateType::Immediate7:
 		return 7;
+	case MipsImmediateType::Immediate8:
+		return 8;
 	case MipsImmediateType::Immediate10:
 		return 10;
 	case MipsImmediateType::Immediate16:
@@ -285,6 +287,7 @@ void CMipsInstruction::encodeNormal() const
 	case MipsImmediateType::Immediate26:
 	case MipsImmediateType::Immediate20_0:
 	case MipsImmediateType::Immediate7:
+	case MipsImmediateType::Immediate8:
 	case MipsImmediateType::ImmediateHalfFloat:
 		encoding |= immediateData.primary.value;
 		break;
@@ -344,6 +347,9 @@ void CMipsInstruction::encodeVfpu() const
 	case MipsImmediateType::Immediate7:
 		encoding |= immediateData.primary.value << 0;
 		break;
+	case MipsImmediateType::Immediate8:
+		encoding |= immediateData.primary.value << 16;
+		break;
 	default:
 		// TODO: Assert?
 		break;

Archs/MIPS/CMipsInstruction.h

@@ -39,7 +39,8 @@ enum class MipsImmediateType
 	CacheOp,
 	Ext,
 	Ins,
-	Cop2BranchType
+	Cop2BranchType,
+	Immediate8
 };
 
 struct MipsRegisterValue

Archs/MIPS/MipsOpcodes.cpp

@@ -698,7 +698,7 @@ const tMipsOpcode MipsOpcodes[] = {
 	{ "vi2f.S",		"vd,vs,i5",	MIPS_VFPU4(0x14),			MA_PSP,		MO_VFPU },
 	{ "vcmovt.S",	"vd,vs,i5",	MIPS_VFPU4(0x15)|0,  		MA_PSP,		MO_VFPU },
 	{ "vcmovf.S",	"vd,vs,i5",	MIPS_VFPU4(0x15)|(1<<19),	MA_PSP,		MO_VFPU },
-	{ "vwbn.S",		"vd,vs,i5",	MIPS_VFPU4(0x18),			MA_PSP,		MO_VFPU },
+	{ "vwbn.s",		"vd,vs,i8",	MIPS_VFPU4(0x18),			MA_PSP,		MO_VFPU|MO_VFPU_SINGLE },
 
 //     31-------------21-------16--------------------------------------0
 //     |= VF4-1.1      |   rt  |                                       |
@@ -771,7 +771,7 @@ const tMipsOpcode MipsOpcodes[] = {
 	{ "vbfy1.S",	"vd,vs",	MIPS_VFPU4_13(0x02),		MA_PSP,		MO_VFPU },
 	{ "vbfy2.S",	"vd,vs",	MIPS_VFPU4_13(0x03),		MA_PSP,		MO_VFPU },
 	{ "vocp.S",		"vd,vs",	MIPS_VFPU4_13(0x04),		MA_PSP,		MO_VFPU },
-	{ "vsocp.S",	"vd,vs",	MIPS_VFPU4_13(0x05),		MA_PSP,		MO_VFPU },
+	{ "vsocp.S",	"vDd,vs",	MIPS_VFPU4_13(0x05),		MA_PSP,		MO_VFPU },
 	{ "vfad.p",		"vSd,vs",	MIPS_VFPU4_13(0x06)|MIPS_VFPUSIZE(1),	MA_PSP,		MO_VFPU|MO_VFPU_PAIR },
 	{ "vfad.t",		"vSd,vs",	MIPS_VFPU4_13(0x06)|MIPS_VFPUSIZE(2),	MA_PSP,		MO_VFPU|MO_VFPU_TRIPLE },
 	{ "vfad.q",		"vSd,vs",	MIPS_VFPU4_13(0x06)|MIPS_VFPUSIZE(3),	MA_PSP,		MO_VFPU|MO_VFPU_QUAD },
@@ -810,10 +810,11 @@ const tMipsOpcode MipsOpcodes[] = {
 //		*1: vcrsp.t/vqmul.q
 	{ "vmmul.S",	"md,ms,mt",		MIPS_VFPU6(0),					MA_PSP,	MO_VFPU|MO_VFPU_TRANSPOSE_VS },
 	{ "vtfm2.p",	"vd,ms,vt",		MIPS_VFPU6(1)|MIPS_VFPUSIZE(1),	MA_PSP,	MO_VFPU|MO_VFPU_PAIR },
-	{ "vhtfm2.p",	"vd,ms,vt",		MIPS_VFPU6(2)|MIPS_VFPUSIZE(1),	MA_PSP,	MO_VFPU|MO_VFPU_PAIR },
+	{ "vhtfm2.p",	"vd,ms,vt",		MIPS_VFPU6(1)|MIPS_VFPUSIZE(0),	MA_PSP,	MO_VFPU|MO_VFPU_PAIR },
 	{ "vtfm3.t",	"vd,ms,vt",		MIPS_VFPU6(2)|MIPS_VFPUSIZE(2),	MA_PSP,	MO_VFPU|MO_VFPU_TRIPLE },
-	{ "vhtfm3.t",	"vd,ms,vt",		MIPS_VFPU6(3)|MIPS_VFPUSIZE(2),	MA_PSP,	MO_VFPU|MO_VFPU_TRIPLE },
+	{ "vhtfm3.t",	"vd,ms,vt",		MIPS_VFPU6(2)|MIPS_VFPUSIZE(1),	MA_PSP,	MO_VFPU|MO_VFPU_TRIPLE },
 	{ "vtfm4.q",	"vd,ms,vt",		MIPS_VFPU6(3)|MIPS_VFPUSIZE(3),	MA_PSP,	MO_VFPU|MO_VFPU_QUAD },
+	{ "vhtfm4.q",	"vd,ms,vt",		MIPS_VFPU6(3)|MIPS_VFPUSIZE(2),	MA_PSP,	MO_VFPU|MO_VFPU_QUAD },
 	{ "vmscl.S",	"md,ms,vSt",	MIPS_VFPU6(4),					MA_PSP,	MO_VFPU },
 	{ "vcrsp.t",	"vd,vs,vt",		MIPS_VFPU6(5)|MIPS_VFPUSIZE(2),	MA_PSP,	MO_VFPU|MO_VFPU_TRIPLE },
 	{ "vqmul.q",	"vd,vs,vt",		MIPS_VFPU6(5)|MIPS_VFPUSIZE(3),	MA_PSP,	MO_VFPU|MO_VFPU_QUAD },

Archs/MIPS/MipsParser.cpp

@@ -520,6 +520,7 @@ bool MipsParser::parseVfpuRegister(Parser& parser, MipsRegisterValue& reg, int s
 		break;
 	case 'e':					// transposed matrix
 		reg.num |= (1 << 5);
+		std::swap(col,row);
 		[[fallthrough]];
 	case 'm':					// matrix
 		reg.type = MipsRegisterType::VfpuMatrix;
@@ -1139,6 +1140,9 @@ static bool decodeImmediateSize(const char*& encoding, MipsImmediateType& dest)
 		case 7:
 			dest = MipsImmediateType::Immediate7;
 			break;
+		case 8:
+			dest = MipsImmediateType::Immediate8;
+			break;
 		case 10:
 			dest = MipsImmediateType::Immediate10;
 			break;

Readme.md

@@ -1182,8 +1182,10 @@ will align the memory address to a multiple of 4, then create a label named `Mai
 
 * Current Development Version
     * *BREAKING* changes to PSP VFPU instruction parsing
+      * fixed transposed matrix register encoding (e.g. `vmidt.p E220` was assembling to `vmidt.p E202`)
       * renamed `vuc2i.s` to [`vuc2ifs.s`](https://pspdev.github.io/vfpu-docs/#vuc2ifs.s)
       * changed [`vfim.s`](https://pspdev.github.io/vfpu-docs/#vfim.s) half float immediate parsing from binary representation to float literals (was:`vfim.s S100,0x3f800000`, now: `vfim.s S100,1.0`)
+      * removed invalid instructions `vwbn.p`/`vwbn.t`/`vwbn.q`
       * removed invalid instructions `vsbn.p`/`vsbn.t`/`vsbn.q`
       * removed invalid instructions `vdet.s`/`vdet.t`/`vdet.q`
       * removed invalid instructions `vcrs.s`/`vcrs.p`/`vcrs.q`
@@ -1193,6 +1195,8 @@ will align the memory address to a multiple of 4, then create a label named `Mai
       * removed invalid instruction `vavg.s`
       * removed invalid instruction `vfad.s`
       * corrected output encodings for [`vdet.p`](https://pspdev.github.io/vfpu-docs/#vdet.p) & [`vcrs.t`](https://pspdev.github.io/vfpu-docs/#vcrs.t)
+      * corrected output encodings for [`vhtfm2.p`](https://pspdev.github.io/vfpu-docs/#vhtfm2.p) & [`vhtfm3.t`](https://pspdev.github.io/vfpu-docs/#vhtfm3.t)
+      * fixed `vd` register size for [`vsocp.s`](https://pspdev.github.io/vfpu-docs/#vsocp.s) & [`vsocp.p`](https://pspdev.github.io/vfpu-docs/#vsocp.p)
       * fixed `vd` register size for [`vdot.p`](https://pspdev.github.io/vfpu-docs/#vdot.p)/[`vdot.t`](https://pspdev.github.io/vfpu-docs/#vdot.q)/[`vdot.t`](https://pspdev.github.io/vfpu-docs/#vdot.q) (was: `vdot.t C103,C201,C201`, now: `vdot.t S103,C201,C201`)
       * fixed `vd` register size for [`vhdp.p`](https://pspdev.github.io/vfpu-docs/#vhdp.p)/[`vhdp.t`](https://pspdev.github.io/vfpu-docs/#vhdp.q)/[`vhdp.t`](https://pspdev.github.io/vfpu-docs/#vhdp.q) (was: `vhdp.t C103,C201,C201`, now: `vhdp.t S103,C201,C201`)
       * fixed `vd` register size for [`vdet.p`](https://pspdev.github.io/vfpu-docs/#vdet.p) (was: `vdet.p C103,C202,C212`, now: `vdet.p S103,C202,C212`)
@@ -1226,6 +1230,8 @@ will align the memory address to a multiple of 4, then create a label named `Mai
       * fixed numeric constant operations for `vpfxs`/`vpfxt` (e.g. `vpfxs 1,1/2,1,0`)
       * added write mask operation to `vpfxd` to skip writing a channel (e.g. `vpfxd ,,,m` prevents writing the last channel)
       * added empty prefix to `vpfxd` to leave a channel unmodified (e.g. `vpfxd ,,,m` leaves the first three channels unmodified)
+      * fixed immediate size for [`vwbn.s`](https://pspdev.github.io/vfpu-docs/#vwbn.s) (is 8 bits, was limited to 5 bits)
+      * added missing instruction [`vhtfm4.q`](https://pspdev.github.io/vfpu-docs/#vhtfm4.q)
 * Version 0.11
     * new `.aligna` directive for absolute address alignment
     * new expression functions: `org(label)`, `orga(label)`, `headersize(label)`