Memory access fault on gfx90a/gfx942 (upstream LLVM AMDGPU miscompile)

[luraess]

A device-side loop over a triangular range whose both endpoints are dynamic is miscompiled on CDNA (MI250, MI300) when bounds checks are off.

x-ref upstream llvm bug llvm/llvm-project#215745

discovered in SpeedyWeather/SpeedyWeather.jl#1187 (comment)

using AMDGPU

function plain!(out, A, R, n)
    lm = AMDGPU.workitemIdx().x + (AMDGPU.workgroupIdx().x - 1) * AMDGPU.workgroupDim().x
    if lm <= size(out, 1)
        @inbounds for k in 1:n
            v = zero(eltype(out))
            for r in k:n                       # <-- triangular, both ends dynamic
                v += R[k, r] * A[lm, r]
            end
            out[lm, k] = v
        end
    end
    return
end

n, lm = 8, 594
A   = ROCArray(rand(ComplexF32, lm, n))
out = ROCArray(zeros(ComplexF32, lm, n))
R   = ROCArray(rand(Float32, n, n))
AMDGPU.@roc groupsize=256 gridsize=768 plain!(out, A, R, n)
AMDGPU.synchronize()
# Memory access fault by GPU node-4 (Agent handle: 0x...) on address 0x...  Reason: Unknown.

The issue comes from a buggy emitted device (gfx942) ISA from a seemingly correct LLVM IR.

Environment: Julia 1.12.6, AMDGPU.jl 2.7.1, GPUCompiler 2.1.1,
AMDGPU_LLVM_Backend_jll 22.1.8+0, MI300A (gfx942:sramecc+). Also reproduces on MI250 (gfx90a)
and with ROCm 6.3's own llc.

Not reproducible on RDNA (7900XTX / gfx1100) — the same faulty pattern is emitted but is benign there because of wave32 (instead of wave64) branch lowering.

Workarounds:

# rectangular loop + predicate
for r in 1:n
    if r >= k
        v += R[k, r] * A[lm, r]
    end
end

# or a while loop
r = k
while r <= n
    v += R[k, r] * A[lm, r]
    r += 1
end

# or a compile-time trip count: pass Val(n) and loop `for r in k:N`

[luraess]

Closing this as addressed in llvm/llvm-project#215829

[vchuravy]

Backport to the AMDGPU backend used JuliaPackaging/Yggdrasil#14465