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I:/ECE554/ECE554-Capstone-Project/VerilogTests/coordinate_latch_tb.sv {1 {vlog -work work -vopt -sv -stats=none I:/ECE554/ECE554-Capstone-Project/VerilogTests/coordinate_latch_tb.sv
Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
-- Compiling module coordinate_latch_tb
Top level modules:
coordinate_latch_tb
} {} {}} I:/ECE554/ECE554-Capstone-Project/Verilog/coordinate_latch.sv {1 {vlog -work work -vopt -sv -stats=none I:/ECE554/ECE554-Capstone-Project/Verilog/coordinate_latch.sv
Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
-- Compiling module coordinate_latch
Top level modules:
coordinate_latch
} {} {}} I:/ECE554/ECE554-Capstone-Project/Verilog/tracking_buffer.sv {1 {vlog -work work -vopt -sv -stats=none I:/ECE554/ECE554-Capstone-Project/Verilog/tracking_buffer.sv
Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
-- Compiling module tracking_buffer
Top level modules:
tracking_buffer
} {} {}} I:/ECE554/ECE554-Capstone-Project/VerilogTests/tracking_buffer_tb.sv {1 {vlog -work work -vopt -sv -stats=none I:/ECE554/ECE554-Capstone-Project/VerilogTests/tracking_buffer_tb.sv
Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
-- Compiling module tracking_buffer_tb
Top level modules:
tracking_buffer_tb
} {} {}} I:/ECE554/ECE554-Capstone-Project/Verilog/timer.sv {1 {vlog -work work -vopt -sv -stats=none I:/ECE554/ECE554-Capstone-Project/Verilog/timer.sv
Questa Intel Starter FPGA Edition-64 vlog 2023.3 Compiler 2023.07 Jul 17 2023
-- Compiling module timer
Top level modules:
timer
} {} {}}