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| 1 | +/* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | +/* |
| 3 | + * Copyright (C) 2025 Advanced Micro Devices, Inc. |
| 4 | + */ |
| 5 | + |
| 6 | +#ifndef _ISP4_HW_REG_H_ |
| 7 | +#define _ISP4_HW_REG_H_ |
| 8 | + |
| 9 | +#include <linux/io.h> |
| 10 | + |
| 11 | +#define ISP_SOFT_RESET 0x62000 |
| 12 | +#define ISP_SYS_INT0_EN 0x62010 |
| 13 | +#define ISP_SYS_INT0_STATUS 0x62014 |
| 14 | +#define ISP_SYS_INT0_ACK 0x62018 |
| 15 | +#define ISP_CCPU_CNTL 0x62054 |
| 16 | +#define ISP_STATUS 0x62058 |
| 17 | +#define ISP_LOG_RB_BASE_LO0 0x62148 |
| 18 | +#define ISP_LOG_RB_BASE_HI0 0x6214c |
| 19 | +#define ISP_LOG_RB_SIZE0 0x62150 |
| 20 | +#define ISP_LOG_RB_RPTR0 0x62154 |
| 21 | +#define ISP_LOG_RB_WPTR0 0x62158 |
| 22 | +#define ISP_RB_BASE_LO1 0x62170 |
| 23 | +#define ISP_RB_BASE_HI1 0x62174 |
| 24 | +#define ISP_RB_SIZE1 0x62178 |
| 25 | +#define ISP_RB_RPTR1 0x6217c |
| 26 | +#define ISP_RB_WPTR1 0x62180 |
| 27 | +#define ISP_RB_BASE_LO2 0x62184 |
| 28 | +#define ISP_RB_BASE_HI2 0x62188 |
| 29 | +#define ISP_RB_SIZE2 0x6218c |
| 30 | +#define ISP_RB_RPTR2 0x62190 |
| 31 | +#define ISP_RB_WPTR2 0x62194 |
| 32 | +#define ISP_RB_BASE_LO3 0x62198 |
| 33 | +#define ISP_RB_BASE_HI3 0x6219c |
| 34 | +#define ISP_RB_SIZE3 0x621a0 |
| 35 | +#define ISP_RB_RPTR3 0x621a4 |
| 36 | +#define ISP_RB_WPTR3 0x621a8 |
| 37 | +#define ISP_RB_BASE_LO4 0x621ac |
| 38 | +#define ISP_RB_BASE_HI4 0x621b0 |
| 39 | +#define ISP_RB_SIZE4 0x621b4 |
| 40 | +#define ISP_RB_RPTR4 0x621b8 |
| 41 | +#define ISP_RB_WPTR4 0x621bc |
| 42 | +#define ISP_RB_BASE_LO5 0x621c0 |
| 43 | +#define ISP_RB_BASE_HI5 0x621c4 |
| 44 | +#define ISP_RB_SIZE5 0x621c8 |
| 45 | +#define ISP_RB_RPTR5 0x621cc |
| 46 | +#define ISP_RB_WPTR5 0x621d0 |
| 47 | +#define ISP_RB_BASE_LO6 0x621d4 |
| 48 | +#define ISP_RB_BASE_HI6 0x621d8 |
| 49 | +#define ISP_RB_SIZE6 0x621dc |
| 50 | +#define ISP_RB_RPTR6 0x621e0 |
| 51 | +#define ISP_RB_WPTR6 0x621e4 |
| 52 | +#define ISP_RB_BASE_LO7 0x621e8 |
| 53 | +#define ISP_RB_BASE_HI7 0x621ec |
| 54 | +#define ISP_RB_SIZE7 0x621f0 |
| 55 | +#define ISP_RB_RPTR7 0x621f4 |
| 56 | +#define ISP_RB_WPTR7 0x621f8 |
| 57 | +#define ISP_RB_BASE_LO8 0x621fc |
| 58 | +#define ISP_RB_BASE_HI8 0x62200 |
| 59 | +#define ISP_RB_SIZE8 0x62204 |
| 60 | +#define ISP_RB_RPTR8 0x62208 |
| 61 | +#define ISP_RB_WPTR8 0x6220c |
| 62 | +#define ISP_RB_BASE_LO9 0x62210 |
| 63 | +#define ISP_RB_BASE_HI9 0x62214 |
| 64 | +#define ISP_RB_SIZE9 0x62218 |
| 65 | +#define ISP_RB_RPTR9 0x6221c |
| 66 | +#define ISP_RB_WPTR9 0x62220 |
| 67 | +#define ISP_RB_BASE_LO10 0x62224 |
| 68 | +#define ISP_RB_BASE_HI10 0x62228 |
| 69 | +#define ISP_RB_SIZE10 0x6222c |
| 70 | +#define ISP_RB_RPTR10 0x62230 |
| 71 | +#define ISP_RB_WPTR10 0x62234 |
| 72 | +#define ISP_RB_BASE_LO11 0x62238 |
| 73 | +#define ISP_RB_BASE_HI11 0x6223c |
| 74 | +#define ISP_RB_SIZE11 0x62240 |
| 75 | +#define ISP_RB_RPTR11 0x62244 |
| 76 | +#define ISP_RB_WPTR11 0x62248 |
| 77 | +#define ISP_RB_BASE_LO12 0x6224c |
| 78 | +#define ISP_RB_BASE_HI12 0x62250 |
| 79 | +#define ISP_RB_SIZE12 0x62254 |
| 80 | +#define ISP_RB_RPTR12 0x62258 |
| 81 | +#define ISP_RB_WPTR12 0x6225c |
| 82 | + |
| 83 | +#define ISP_POWER_STATUS 0x60000 |
| 84 | + |
| 85 | +/* ISP_SOFT_RESET */ |
| 86 | +#define ISP_SOFT_RESET__CCPU_SOFT_RESET_MASK 0x00000001UL |
| 87 | + |
| 88 | +/* ISP_CCPU_CNTL */ |
| 89 | +#define ISP_CCPU_CNTL__CCPU_HOST_SOFT_RST_MASK 0x00040000UL |
| 90 | + |
| 91 | +/* ISP_STATUS */ |
| 92 | +#define ISP_STATUS__CCPU_REPORT_MASK 0x000000feUL |
| 93 | + |
| 94 | +/* ISP_SYS_INT0_STATUS */ |
| 95 | +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT9_INT_MASK 0x00010000UL |
| 96 | +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT10_INT_MASK 0x00040000UL |
| 97 | +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT11_INT_MASK 0x00100000UL |
| 98 | +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT12_INT_MASK 0x00400000UL |
| 99 | + |
| 100 | +/* ISP_SYS_INT0_EN */ |
| 101 | +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT9_EN_MASK 0x00010000UL |
| 102 | +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT10_EN_MASK 0x00040000UL |
| 103 | +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT11_EN_MASK 0x00100000UL |
| 104 | +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT12_EN_MASK 0x00400000UL |
| 105 | + |
| 106 | +/* ISP_SYS_INT0_ACK */ |
| 107 | +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT9_ACK_MASK 0x00010000UL |
| 108 | +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT10_ACK_MASK 0x00040000UL |
| 109 | +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT11_ACK_MASK 0x00100000UL |
| 110 | +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT12_ACK_MASK 0x00400000UL |
| 111 | + |
| 112 | +/* Helper functions for reading isp registers */ |
| 113 | +static inline u32 isp4hw_rreg(void __iomem *base, u32 reg) |
| 114 | +{ |
| 115 | + return readl(base + reg); |
| 116 | +} |
| 117 | + |
| 118 | +/* Helper functions for writing isp registers */ |
| 119 | +static inline void isp4hw_wreg(void __iomem *base, u32 reg, u32 val) |
| 120 | +{ |
| 121 | + return writel(val, base + reg); |
| 122 | +} |
| 123 | + |
| 124 | +#endif /* _ISP4_HW_REG_H_ */ |
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