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airliedairlied
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Merge tag 'amd-drm-fixes-7.0-2026-04-01' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-7.0-2026-04-01: amdgpu: - UserQ fixes - PASID handling fix - S4 fix for smu11 chips - Misc small fixes amdkfd: - Non-4K page fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260401174731.3576021-1-alexander.deucher@amd.com
2 parents 7aaa804 + 78746a4 commit 2aa5a6d

16 files changed

Lines changed: 115 additions & 46 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2703,8 +2703,12 @@ static int amdgpu_pmops_freeze(struct device *dev)
27032703
if (r)
27042704
return r;
27052705

2706-
if (amdgpu_acpi_should_gpu_reset(adev))
2707-
return amdgpu_asic_reset(adev);
2706+
if (amdgpu_acpi_should_gpu_reset(adev)) {
2707+
amdgpu_device_lock_reset_domain(adev->reset_domain);
2708+
r = amdgpu_asic_reset(adev);
2709+
amdgpu_device_unlock_reset_domain(adev->reset_domain);
2710+
return r;
2711+
}
27082712
return 0;
27092713
}
27102714

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -403,6 +403,50 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
403403
drm_dev_exit(idx);
404404
}
405405

406+
/**
407+
* amdgpu_gart_map_gfx9_mqd - map mqd and ctrl_stack dma_addresses into GART entries
408+
*
409+
* @adev: amdgpu_device pointer
410+
* @offset: offset into the GPU's gart aperture
411+
* @pages: number of pages to bind
412+
* @dma_addr: DMA addresses of pages
413+
* @flags: page table entry flags
414+
*
415+
* Map the MQD and control stack addresses into GART entries with the correct
416+
* memory types on gfxv9. The MQD occupies the first 4KB and is followed by
417+
* the control stack. The MQD uses UC (uncached) memory, while the control stack
418+
* uses NC (non-coherent) memory.
419+
*/
420+
void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset,
421+
int pages, dma_addr_t *dma_addr, uint64_t flags)
422+
{
423+
uint64_t page_base;
424+
unsigned int i, j, t;
425+
int idx;
426+
uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
427+
void *dst;
428+
429+
if (!adev->gart.ptr)
430+
return;
431+
432+
if (!drm_dev_enter(adev_to_drm(adev), &idx))
433+
return;
434+
435+
t = offset / AMDGPU_GPU_PAGE_SIZE;
436+
dst = adev->gart.ptr;
437+
for (i = 0; i < pages; i++) {
438+
page_base = dma_addr[i];
439+
for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
440+
if ((i == 0) && (j == 0))
441+
amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
442+
else
443+
amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, ctrl_flags);
444+
page_base += AMDGPU_GPU_PAGE_SIZE;
445+
}
446+
}
447+
drm_dev_exit(idx);
448+
}
449+
406450
/**
407451
* amdgpu_gart_bind - bind pages into the gart page table
408452
*

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,8 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
6262
void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
6363
int pages, dma_addr_t *dma_addr, uint64_t flags,
6464
void *dst);
65+
void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset,
66+
int pages, dma_addr_t *dma_addr, uint64_t flags);
6567
void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
6668
int pages, dma_addr_t *dma_addr, uint64_t flags);
6769
void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,11 @@ int amdgpu_pasid_alloc(unsigned int bits)
6868
return -EINVAL;
6969

7070
spin_lock(&amdgpu_pasid_idr_lock);
71+
/* TODO: Need to replace the idr with an xarry, and then
72+
* handle the internal locking with ATOMIC safe paths.
73+
*/
7174
pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1,
72-
1U << bits, GFP_KERNEL);
75+
1U << bits, GFP_ATOMIC);
7376
spin_unlock(&amdgpu_pasid_idr_lock);
7477

7578
if (pasid >= 0)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c‎

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -853,25 +853,15 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
853853
int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
854854
uint64_t page_idx, pages_per_xcc;
855855
int i;
856-
uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
857856

858857
pages_per_xcc = total_pages;
859858
do_div(pages_per_xcc, num_xcc);
860859

861860
for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
862-
/* MQD page: use default flags */
863-
amdgpu_gart_bind(adev,
861+
amdgpu_gart_map_gfx9_mqd(adev,
864862
gtt->offset + (page_idx << PAGE_SHIFT),
865-
1, &gtt->ttm.dma_address[page_idx], flags);
866-
/*
867-
* Ctrl pages - modify the memory type to NC (ctrl_flags) from
868-
* the second page of the BO onward.
869-
*/
870-
amdgpu_gart_bind(adev,
871-
gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
872-
pages_per_xcc - 1,
873-
&gtt->ttm.dma_address[page_idx + 1],
874-
ctrl_flags);
863+
pages_per_xcc, &gtt->ttm.dma_address[page_idx],
864+
flags);
875865
}
876866
}
877867

‎drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -600,6 +600,13 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr,
600600
goto unpin_bo;
601601
}
602602

603+
/* Validate doorbell_offset is within the doorbell BO */
604+
if ((u64)db_info->doorbell_offset * db_size + db_size >
605+
amdgpu_bo_size(db_obj->obj)) {
606+
r = -EINVAL;
607+
goto unpin_bo;
608+
}
609+
603610
index = amdgpu_doorbell_index_on_bar(uq_mgr->adev, db_obj->obj,
604611
db_info->doorbell_offset, db_size);
605612
drm_dbg_driver(adev_to_drm(uq_mgr->adev),

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ struct amdgpu_bo_vm;
173173
#define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20)
174174
#define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \
175175
- AMDGPU_VA_RESERVED_SEQ64_SIZE)
176-
#define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12)
176+
#define AMDGPU_VA_RESERVED_TRAP_SIZE (1ULL << 16)
177177
#define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \
178178
- AMDGPU_VA_RESERVED_TRAP_SIZE)
179179
#define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16)

‎drivers/gpu/drm/amd/amdgpu/mes_userqueue.c‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -324,8 +324,10 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue,
324324

325325
r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va,
326326
2048);
327-
if (r)
327+
if (r) {
328+
kfree(compute_mqd);
328329
goto free_mqd;
330+
}
329331

330332
userq_props->eop_gpu_addr = compute_mqd->eop_va;
331333
userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;
@@ -365,12 +367,16 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue,
365367

366368
r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va,
367369
shadow_info.shadow_size);
368-
if (r)
370+
if (r) {
371+
kfree(mqd_gfx_v11);
369372
goto free_mqd;
373+
}
370374
r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va,
371375
shadow_info.csa_size);
372-
if (r)
376+
if (r) {
377+
kfree(mqd_gfx_v11);
373378
goto free_mqd;
379+
}
374380

375381
kfree(mqd_gfx_v11);
376382
} else if (queue->queue_type == AMDGPU_HW_IP_DMA) {
@@ -390,8 +396,10 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue,
390396
}
391397
r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va,
392398
32);
393-
if (r)
399+
if (r) {
400+
kfree(mqd_sdma_v11);
394401
goto free_mqd;
402+
}
395403

396404
userq_props->csa_addr = mqd_sdma_v11->csa_va;
397405
kfree(mqd_sdma_v11);

‎drivers/gpu/drm/amd/amdgpu/psp_v11_0.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,8 @@ static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
170170
int retry_loop;
171171

172172
/* For a reset done at the end of S3, only wait for TOS to be unloaded */
173-
if (adev->in_s3 && !(adev->flags & AMD_IS_APU) && amdgpu_in_reset(adev))
173+
if ((adev->in_s4 || adev->in_s3) && !(adev->flags & AMD_IS_APU) &&
174+
amdgpu_in_reset(adev))
174175
return psp_v11_wait_for_tos_unload(psp);
175176

176177
for (retry_loop = 0; retry_loop < 20; retry_loop++) {

‎drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c‎

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -42,9 +42,16 @@ static uint64_t mqd_stride_v9(struct mqd_manager *mm,
4242
struct queue_properties *q)
4343
{
4444
if (mm->dev->kfd->cwsr_enabled &&
45-
q->type == KFD_QUEUE_TYPE_COMPUTE)
46-
return ALIGN(q->ctl_stack_size, PAGE_SIZE) +
47-
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE);
45+
q->type == KFD_QUEUE_TYPE_COMPUTE) {
46+
47+
/* On gfxv9, the MQD resides in the first 4K page,
48+
* followed by the control stack. Align both to
49+
* AMDGPU_GPU_PAGE_SIZE to maintain the required 4K boundary.
50+
*/
51+
52+
return ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) +
53+
ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE);
54+
}
4855

4956
return mm->mqd_size;
5057
}
@@ -151,8 +158,8 @@ static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
151158
if (!mqd_mem_obj)
152159
return NULL;
153160
retval = amdgpu_amdkfd_alloc_kernel_mem(node->adev,
154-
(ALIGN(q->ctl_stack_size, PAGE_SIZE) +
155-
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
161+
(ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) +
162+
ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE)) *
156163
NUM_XCC(node->xcc_mask),
157164
mqd_on_vram(node->adev) ? AMDGPU_GEM_DOMAIN_VRAM :
158165
AMDGPU_GEM_DOMAIN_GTT,
@@ -360,7 +367,7 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd,
360367
struct kfd_context_save_area_header header;
361368

362369
/* Control stack is located one page after MQD. */
363-
void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
370+
void *mqd_ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE);
364371

365372
m = get_mqd(mqd);
366373

@@ -397,7 +404,7 @@ static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, voi
397404
{
398405
struct v9_mqd *m;
399406
/* Control stack is located one page after MQD. */
400-
void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
407+
void *ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE);
401408

402409
m = get_mqd(mqd);
403410

@@ -443,7 +450,7 @@ static void restore_mqd(struct mqd_manager *mm, void **mqd,
443450
*gart_addr = addr;
444451

445452
/* Control stack is located one page after MQD. */
446-
ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE);
453+
ctl_stack = (void *)((uintptr_t)*mqd + AMDGPU_GPU_PAGE_SIZE);
447454
memcpy(ctl_stack, ctl_stack_src, ctl_stack_size);
448455

449456
m->cp_hqd_pq_doorbell_control =

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